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(unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id E1B203F7092; Mon, 2 Mar 2026 00:58:14 -0800 (PST) From: Ratheesh Kannoth To: , CC: , , , , , , , , , , , , "Ratheesh Kannoth" Subject: [PATCH net-next 1/5] octeontx2-af: npc: cn20k: debugfs enhancements Date: Mon, 2 Mar 2026 14:27:59 +0530 Message-ID: <20260302085803.2449828-2-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260302085803.2449828-1-rkannoth@marvell.com> References: <20260302085803.2449828-1-rkannoth@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzAyMDA3NyBTYWx0ZWRfX2z79t/PpFZNk G5AC+V3795Z+4qZYSMjRnwZ+eG0gfgs7AygryiyaJGoBymYteXEYli2W7viaNhZ2dnVEgxj+rFM 4HQ/G3W2Z9zOXZApTzSgJEt0hRAt56jOm08cJAF9PZQ+f2v7zm7ERjqtrN13MScVbUV5oxVpTyV xUAeNrXI7FQx3C8Gfar0nNpIv+KvNZ94LAy8jsSPyq/16t5ag7zLeiUcwYiPZTc6j4RMKraocwT 6RnsQSsNeIe2ccfhcbYPnyJ06oMAVqM+nu2E2BPYX2ppaea7UNTYeWWExQzHoqp0pP3XfrYfAqx 0rsadl8gWxV6YCnspvbsvufv4pInRTCf6TwGbXro+NQar84tG9iJtoANs0UxVPiYHPthH1mjsa0 tZ8u5ZqGaRxnNm00xUGpxIlSOfkXtfSCEH19brXFSSjQh2OvszLAZqj0UMXwJRq1yYt46QSjyZw vnHkuKC7smbX7dli3DQ== X-Proofpoint-ORIG-GUID: xeQMXQqI1Tefq6gdGXwXMK9OrxsxArDZ X-Authority-Analysis: v=2.4 cv=TtrrRTXh c=1 sm=1 tr=0 ts=69a5512d cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=Yq5XynenixoA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=qit2iCtTFQkLgVSMPQTB:22 a=M5GUcnROAAAA:8 a=Ci00bJMBAOu-zhm_1uQA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: xeQMXQqI1Tefq6gdGXwXMK9OrxsxArDZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-02_02,2026-02-27_03,2025-10-01_01 Content-Type: text/plain; charset="utf-8" Improve MCAM visibility and field debugging for CN20K NPC. - Extend "mcam_layout" to show enabled (+) or disabled state per entry so status can be verified without parsing the full "mcam_entry" dump. - Add "dstats" debugfs entry: reports recently hit MCAM indices with packet counts; stats are cleared on read so each read shows deltas. - Add "mismatch" debugfs entry: lists MCAM entries that are enabled but not explicitly allocated, helping diagnose allocation/field issues. Signed-off-by: Ratheesh Kannoth --- .../marvell/octeontx2/af/cn20k/debugfs.c | 126 +++++++++++++++++- .../ethernet/marvell/octeontx2/af/cn20k/npc.c | 16 ++- .../ethernet/marvell/octeontx2/af/cn20k/npc.h | 7 + 3 files changed, 135 insertions(+), 14 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.c b/dr= ivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.c index 3debf2fae1a4..7414986c3fdd 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.c @@ -13,6 +13,7 @@ #include "struct.h" #include "rvu.h" #include "debugfs.h" +#include "cn20k/reg.h" #include "cn20k/npc.h" =20 static int npc_mcam_layout_show(struct seq_file *s, void *unused) @@ -58,7 +59,8 @@ static int npc_mcam_layout_show(struct seq_file *s, void = *unused) "v:%u", vidx0); } =20 - seq_printf(s, "\t%u(%#x) %s\n", idx0, pf1, + seq_printf(s, "\t%u(%#x)%c %s\n", idx0, pf1, + test_bit(idx0, npc_priv->en_map) ? '+' : 0, map ? buf0 : " "); } goto next; @@ -101,9 +103,13 @@ static int npc_mcam_layout_show(struct seq_file *s, vo= id *unused) vidx1); } =20 - seq_printf(s, "%05u(%#x) %s\t\t%05u(%#x) %s\n", - idx1, pf2, v1 ? buf1 : " ", - idx0, pf1, v0 ? buf0 : " "); + seq_printf(s, "%05u(%#x)%c %s\t\t%05u(%#x)%c %s\n", + idx1, pf2, + test_bit(idx1, npc_priv->en_map) ? '+' : 0, + v1 ? buf1 : " ", + idx0, pf1, + test_bit(idx0, npc_priv->en_map) ? '+' : 0, + v0 ? buf0 : " "); =20 continue; } @@ -120,8 +126,9 @@ static int npc_mcam_layout_show(struct seq_file *s, voi= d *unused) vidx0); } =20 - seq_printf(s, "\t\t \t\t%05u(%#x) %s\n", idx0, - pf1, map ? buf0 : " "); + seq_printf(s, "\t\t \t\t%05u(%#x)%c %s\n", idx0, pf1, + test_bit(idx0, npc_priv->en_map) ? '+' : 0, + map ? buf0 : " "); continue; } =20 @@ -134,7 +141,8 @@ static int npc_mcam_layout_show(struct seq_file *s, voi= d *unused) snprintf(buf1, sizeof(buf1), "v:%05u", vidx1); } =20 - seq_printf(s, "%05u(%#x) %s\n", idx1, pf1, + seq_printf(s, "%05u(%#x)%c %s\n", idx1, pf1, + test_bit(idx1, npc_priv->en_map) ? '+' : 0, map ? buf1 : " "); } next: @@ -145,6 +153,100 @@ static int npc_mcam_layout_show(struct seq_file *s, v= oid *unused) =20 DEFINE_SHOW_ATTRIBUTE(npc_mcam_layout); =20 +static u64 dstats[MAX_NUM_BANKS][MAX_SUBBANK_DEPTH * MAX_NUM_SUB_BANKS] = =3D {}; +static int npc_mcam_dstats_show(struct seq_file *s, void *unused) +{ + struct npc_priv_t *npc_priv; + int blkaddr, pf, mcam_idx; + u64 stats, delta; + struct rvu *rvu; + u8 key_type; + void *map; + + npc_priv =3D npc_priv_get(); + rvu =3D s->private; + blkaddr =3D rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); + if (blkaddr < 0) + return 0; + + seq_puts(s, "idx\tpfunc\tstats\n"); + for (int bank =3D npc_priv->num_banks - 1; bank >=3D 0; bank--) { + for (int idx =3D npc_priv->bank_depth - 1; idx >=3D 0; idx--) { + mcam_idx =3D bank * npc_priv->bank_depth + idx; + + npc_mcam_idx_2_key_type(rvu, mcam_idx, &key_type); + if (key_type =3D=3D NPC_MCAM_KEY_X4 && bank !=3D 0) + continue; + + if (!test_bit(mcam_idx, npc_priv->en_map)) + continue; + + stats =3D rvu_read64(rvu, blkaddr, + NPC_AF_CN20K_MCAMEX_BANKX_STAT_EXT(idx, bank)); + if (!stats) + continue; + if (stats =3D=3D dstats[bank][idx]) + continue; + + if (stats < dstats[bank][idx]) + dstats[bank][idx] =3D 0; + + pf =3D 0xFFFF; + map =3D xa_load(&npc_priv->xa_idx2pf_map, mcam_idx); + if (map) + pf =3D xa_to_value(map); + + if (stats > dstats[bank][idx]) + delta =3D stats - dstats[bank][idx]; + else + delta =3D stats; + + seq_printf(s, "%u\t%#04x\t%llu\n", + mcam_idx, pf, delta); + dstats[bank][idx] =3D stats; + } + } + return 0; +} +DEFINE_SHOW_ATTRIBUTE(npc_mcam_dstats); + +static int npc_mcam_mismatch_show(struct seq_file *s, void *unused) +{ + struct npc_priv_t *npc_priv; + struct npc_subbank *sb; + int mcam_idx, sb_off; + struct rvu *rvu; + void *map; + int rc; + + npc_priv =3D npc_priv_get(); + rvu =3D s->private; + + seq_puts(s, "index\tsb idx\tkw type\n"); + for (int bank =3D npc_priv->num_banks - 1; bank >=3D 0; bank--) { + for (int idx =3D npc_priv->bank_depth - 1; idx >=3D 0; idx--) { + mcam_idx =3D bank * npc_priv->bank_depth + idx; + + if (!test_bit(mcam_idx, npc_priv->en_map)) + continue; + + map =3D xa_load(&npc_priv->xa_idx2pf_map, mcam_idx); + if (map) + continue; + + rc =3D npc_mcam_idx_2_subbank_idx(rvu, mcam_idx, + &sb, &sb_off); + if (rc) + continue; + + seq_printf(s, "%u\t%d\t%u\n", mcam_idx, sb->idx, + sb->key_type); + } + } + return 0; +} +DEFINE_SHOW_ATTRIBUTE(npc_mcam_mismatch); + static int npc_mcam_default_show(struct seq_file *s, void *unused) { struct npc_priv_t *npc_priv; @@ -257,6 +359,16 @@ int npc_cn20k_debugfs_init(struct rvu *rvu) if (!npc_dentry) return -EFAULT; =20 + npc_dentry =3D debugfs_create_file("dstats", 0444, rvu->rvu_dbg.npc, rvu, + &npc_mcam_dstats_fops); + if (!npc_dentry) + return -EFAULT; + + npc_dentry =3D debugfs_create_file("mismatch", 0444, rvu->rvu_dbg.npc, rv= u, + &npc_mcam_mismatch_fops); + if (!npc_dentry) + return -EFAULT; + npc_dentry =3D debugfs_create_file("mcam_default", 0444, rvu->rvu_dbg.npc, rvu, &npc_mcam_default_fops); =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c b/driver= s/net/ethernet/marvell/octeontx2/af/cn20k/npc.c index 7291fdb89b03..e854b85ced9e 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c @@ -808,6 +808,9 @@ npc_cn20k_enable_mcam_entry(struct rvu *rvu, int blkadd= r, u64 cfg, hw_prio; u8 kw_type; =20 + enable ? set_bit(index, npc_priv.en_map) : + clear_bit(index, npc_priv.en_map); + npc_mcam_idx_2_key_type(rvu, index, &kw_type); if (kw_type =3D=3D NPC_MCAM_KEY_X2) { cfg =3D rvu_read64(rvu, blkaddr, @@ -1016,14 +1019,12 @@ static void npc_cn20k_config_kw_x4(struct rvu *rvu,= struct npc_mcam *mcam, =20 static void npc_cn20k_set_mcam_bank_cfg(struct rvu *rvu, int blkaddr, int mcam_idx, - int bank, u8 kw_type, bool enable, u8 hw_prio) + int bank, u8 kw_type, u8 hw_prio) { struct npc_mcam *mcam =3D &rvu->hw->mcam; u64 bank_cfg; =20 bank_cfg =3D (u64)hw_prio << 24; - if (enable) - bank_cfg |=3D 0x1; =20 if (kw_type =3D=3D NPC_MCAM_KEY_X2) { rvu_write64(rvu, blkaddr, @@ -1119,7 +1120,8 @@ void npc_cn20k_config_mcam_entry(struct rvu *rvu, int= blkaddr, int index, /* TODO: */ /* PF installing VF rule */ npc_cn20k_set_mcam_bank_cfg(rvu, blkaddr, mcam_idx, bank, - kw_type, enable, hw_prio); + kw_type, hw_prio); + npc_cn20k_enable_mcam_entry(rvu, blkaddr, index, enable); } =20 void npc_cn20k_copy_mcam_entry(struct rvu *rvu, int blkaddr, u16 src, u16 = dest) @@ -1735,9 +1737,9 @@ static int npc_subbank_idx_2_mcam_idx(struct rvu *rvu= , struct npc_subbank *sb, return 0; } =20 -static int npc_mcam_idx_2_subbank_idx(struct rvu *rvu, u16 mcam_idx, - struct npc_subbank **sb, - int *sb_off) +int npc_mcam_idx_2_subbank_idx(struct rvu *rvu, u16 mcam_idx, + struct npc_subbank **sb, + int *sb_off) { int bank_off, sb_id; =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h b/driver= s/net/ethernet/marvell/octeontx2/af/cn20k/npc.h index 815d0b257a7e..004a556c7b90 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h @@ -170,6 +170,7 @@ struct npc_defrag_show_node { * @num_banks: Number of banks. * @num_subbanks: Number of subbanks. * @subbank_depth: Depth of subbank. + * @en_map: Enable/disable status. * @kw: Kex configured key type. * @sb: Subbank array. * @xa_sb_used: Array of used subbanks. @@ -193,6 +194,9 @@ struct npc_priv_t { const int num_banks; int num_subbanks; int subbank_depth; + DECLARE_BITMAP(en_map, MAX_NUM_BANKS * + MAX_NUM_SUB_BANKS * + MAX_SUBBANK_DEPTH); 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(unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id 0CC233F7064; Mon, 2 Mar 2026 00:58:19 -0800 (PST) From: Ratheesh Kannoth To: , CC: , , , , , , , , , , , , "Saeed Mahameed" , Ratheesh Kannoth Subject: [PATCH net-next 2/5] devlink: Implement devlink param multi attribute nested data values Date: Mon, 2 Mar 2026 14:28:00 +0530 Message-ID: <20260302085803.2449828-3-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260302085803.2449828-1-rkannoth@marvell.com> References: <20260302085803.2449828-1-rkannoth@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: CJUjNzFOuRPYedNReegtuwSkDmW_00P0 X-Authority-Analysis: v=2.4 cv=eYUwvrEH c=1 sm=1 tr=0 ts=69a55132 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=Yq5XynenixoA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=EAYMVhzMl8SCOHhVQcBL:22 a=Ikd4Dj_1AAAA:8 a=M5GUcnROAAAA:8 a=sSlqG2hmm6If27J4_lgA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-ORIG-GUID: CJUjNzFOuRPYedNReegtuwSkDmW_00P0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzAyMDA3NyBTYWx0ZWRfXwGW84hvPR0mp Qvt5RRm8QKT+2PtQDps08WY4ZNkUkOZ9zYWmp+qgwTWMV2UjlpMtBMHpq16DsJTyvQVk4KfEtw7 v3l97fQkhg47a0yNERRSsBnwsiPCq/wYo6icDAgGT785n+wbeXq6sVnjOCrTtFOGD7L2Lh4GURr UpSyn2GyxCVtlhGb1REUwBmvbDXzwgecO2ACr2axV+QGxY5Z0VwQw897YAzOs8ONMX7ncANU5GJ SNN+qu0C/AIC9VkXosJltv6BpJ6n7JSCPsVa55J1KHb6OM9Bfve4WpEQCZZiCATIplQzdHMSNqt DEkASwh+aRdoiBjJfdWmGvpj1zzalWVzNsCQtjTQOqMVNT1PBbkgE0eArVYAT49ZtCqIcSr9ie9 IkQmKwNEihnP3Ymsy6sGN8ZwbfP/0AKGwYyOhgbualvPnZzfbZqnd3wMGRJc69Bpn8KlEiAeWgy PypUkEEQ2CfGDV6Ovbw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-02_02,2026-02-27_03,2025-10-01_01 Content-Type: text/plain; charset="utf-8" From: Saeed Mahameed Devlink param value attribute is not defined since devlink is handling the value validating and parsing internally, this allows us to implement multi attribute values without breaking any policies. Devlink param multi-attribute values are considered to be dynamically sized arrays of u32 values, by introducing a new devlink param type DEVLINK_PARAM_TYPE_U32_ARRAY, driver and user space can set a variable count of u32 values into the DEVLINK_ATTR_PARAM_VALUE_DATA attribute. Implement get/set parsing and add to the internal value structure passed to drivers. This is useful for devices that need to configure a list of values for a specific configuration. example: $ devlink dev param show pci/... name multi-value-param name multi-value-param type driver-specific values: cmode permanent value: 0,1,2,3,4,5,6,7 $ devlink dev param set pci/... name multi-value-param \ value 4,5,6,7,0,1,2,3 cmode permanent Signed-off-by: Saeed Mahameed Signed-off-by: Ratheesh Kannoth --- Documentation/netlink/specs/devlink.yaml | 4 ++ include/net/devlink.h | 8 +++ include/uapi/linux/devlink.h | 1 + net/devlink/netlink_gen.c | 2 + net/devlink/param.c | 78 ++++++++++++++++++------ 5 files changed, 75 insertions(+), 18 deletions(-) diff --git a/Documentation/netlink/specs/devlink.yaml b/Documentation/netli= nk/specs/devlink.yaml index 837112da6738..e8a8287c4f19 100644 --- a/Documentation/netlink/specs/devlink.yaml +++ b/Documentation/netlink/specs/devlink.yaml @@ -226,6 +226,10 @@ definitions: value: 10 - name: binary + - + name: u32-array + value: 129 + - name: rate-tc-index-max type: const diff --git a/include/net/devlink.h b/include/net/devlink.h index cb839e0435a1..0a496715da99 100644 --- a/include/net/devlink.h +++ b/include/net/devlink.h @@ -432,6 +432,13 @@ enum devlink_param_type { DEVLINK_PARAM_TYPE_U64 =3D DEVLINK_VAR_ATTR_TYPE_U64, DEVLINK_PARAM_TYPE_STRING =3D DEVLINK_VAR_ATTR_TYPE_STRING, DEVLINK_PARAM_TYPE_BOOL =3D DEVLINK_VAR_ATTR_TYPE_FLAG, + DEVLINK_PARAM_TYPE_U32_ARRAY =3D DEVLINK_VAR_ATTR_TYPE_U32_ARRAY, +}; + +#define __DEVLINK_PARAM_MAX_ARRAY_SIZE 32 +struct devlink_param_u32_array { + u32 size; + u32 val[__DEVLINK_PARAM_MAX_ARRAY_SIZE]; }; =20 union devlink_param_value { @@ -441,6 +448,7 @@ union devlink_param_value { u64 vu64; char vstr[__DEVLINK_PARAM_MAX_STRING_VALUE]; bool vbool; + struct devlink_param_u32_array u32arr; }; =20 struct devlink_param_gset_ctx { diff --git a/include/uapi/linux/devlink.h b/include/uapi/linux/devlink.h index e7d6b6d13470..768d0d88710f 100644 --- a/include/uapi/linux/devlink.h +++ b/include/uapi/linux/devlink.h @@ -404,6 +404,7 @@ enum devlink_var_attr_type { DEVLINK_VAR_ATTR_TYPE_BINARY, __DEVLINK_VAR_ATTR_TYPE_CUSTOM_BASE =3D 0x80, /* Any possible custom types, unrelated to NLA_* values go below */ + DEVLINK_VAR_ATTR_TYPE_U32_ARRAY, }; =20 enum devlink_attr { diff --git a/net/devlink/netlink_gen.c b/net/devlink/netlink_gen.c index f4c61c2b4f22..e5a80eb467b8 100644 --- a/net/devlink/netlink_gen.c +++ b/net/devlink/netlink_gen.c @@ -32,6 +32,8 @@ devlink_attr_param_type_validate(const struct nlattr *att= r, case DEVLINK_VAR_ATTR_TYPE_NUL_STRING: fallthrough; case DEVLINK_VAR_ATTR_TYPE_BINARY: + fallthrough; + case DEVLINK_VAR_ATTR_TYPE_U32_ARRAY: return 0; } NL_SET_ERR_MSG_ATTR(extack, attr, "invalid enum value"); diff --git a/net/devlink/param.c b/net/devlink/param.c index cf95268da5b0..8bb83a0a134c 100644 --- a/net/devlink/param.c +++ b/net/devlink/param.c @@ -252,6 +252,14 @@ devlink_nl_param_value_put(struct sk_buff *msg, enum d= evlink_param_type type, return -EMSGSIZE; } break; + case DEVLINK_PARAM_TYPE_U32_ARRAY: + if (val.u32arr.size > __DEVLINK_PARAM_MAX_ARRAY_SIZE) + return -EMSGSIZE; + + for (int i =3D 0; i < val.u32arr.size; i++) + if (nla_put_u32(msg, nla_type, val.u32arr.val[i])) + return -EMSGSIZE; + break; } return 0; } @@ -304,8 +312,8 @@ static int devlink_nl_param_fill(struct sk_buff *msg, s= truct devlink *devlink, u32 portid, u32 seq, int flags, struct netlink_ext_ack *extack) { - union devlink_param_value default_value[DEVLINK_PARAM_CMODE_MAX + 1]; - union devlink_param_value param_value[DEVLINK_PARAM_CMODE_MAX + 1]; + union devlink_param_value (*default_value)[DEVLINK_PARAM_CMODE_MAX + 1]; + union devlink_param_value (*param_value)[DEVLINK_PARAM_CMODE_MAX + 1]; bool default_value_set[DEVLINK_PARAM_CMODE_MAX + 1] =3D {}; bool param_value_set[DEVLINK_PARAM_CMODE_MAX + 1] =3D {}; const struct devlink_param *param =3D param_item->param; @@ -316,44 +324,57 @@ static int devlink_nl_param_fill(struct sk_buff *msg,= struct devlink *devlink, int err; int i; =20 + default_value =3D kmalloc_obj(*default_value); + if (!default_value) + return -ENOMEM; + + param_value =3D kmalloc_obj(*param_value); + if (!param_value) { + kfree(default_value); + return -ENOMEM; + } + /* Get value from driver part to driverinit configuration mode */ for (i =3D 0; i <=3D DEVLINK_PARAM_CMODE_MAX; i++) { if (!devlink_param_cmode_is_supported(param, i)) continue; if (i =3D=3D DEVLINK_PARAM_CMODE_DRIVERINIT) { - if (param_item->driverinit_value_new_valid) - param_value[i] =3D param_item->driverinit_value_new; - else if (param_item->driverinit_value_valid) - param_value[i] =3D param_item->driverinit_value; - else - return -EOPNOTSUPP; + if (param_item->driverinit_value_new_valid) { + (*param_value)[i] =3D param_item->driverinit_value_new; + } else if (param_item->driverinit_value_valid) { + (*param_value)[i] =3D param_item->driverinit_value; + } else { + err =3D -EOPNOTSUPP; + goto get_put_fail; + } =20 if (param_item->driverinit_value_valid) { - default_value[i] =3D param_item->driverinit_default; + (*default_value)[i] =3D param_item->driverinit_default; default_value_set[i] =3D true; } } else { ctx.cmode =3D i; err =3D devlink_param_get(devlink, param, &ctx, extack); if (err) - return err; - param_value[i] =3D ctx.val; + goto get_put_fail; + (*param_value)[i] =3D ctx.val; =20 err =3D devlink_param_get_default(devlink, param, &ctx, extack); if (!err) { - default_value[i] =3D ctx.val; + (*default_value)[i] =3D ctx.val; default_value_set[i] =3D true; } else if (err !=3D -EOPNOTSUPP) { - return err; + goto get_put_fail; } } param_value_set[i] =3D true; } =20 + err =3D -EMSGSIZE; hdr =3D genlmsg_put(msg, portid, seq, &devlink_nl_family, flags, cmd); if (!hdr) - return -EMSGSIZE; + goto get_put_fail; =20 if (devlink_nl_put_handle(msg, devlink)) goto genlmsg_cancel; @@ -383,8 +404,8 @@ static int devlink_nl_param_fill(struct sk_buff *msg, s= truct devlink *devlink, if (!param_value_set[i]) continue; err =3D devlink_nl_param_value_fill_one(msg, param->type, - i, param_value[i], - default_value[i], + i, (*param_value)[i], + (*default_value)[i], default_value_set[i]); if (err) goto values_list_nest_cancel; @@ -393,6 +414,8 @@ static int devlink_nl_param_fill(struct sk_buff *msg, s= truct devlink *devlink, nla_nest_end(msg, param_values_list); nla_nest_end(msg, param_attr); genlmsg_end(msg, hdr); + kfree(default_value); + kfree(param_value); return 0; =20 values_list_nest_cancel: @@ -401,7 +424,10 @@ static int devlink_nl_param_fill(struct sk_buff *msg, = struct devlink *devlink, nla_nest_cancel(msg, param_attr); genlmsg_cancel: genlmsg_cancel(msg, hdr); - return -EMSGSIZE; +get_put_fail: + kfree(default_value); + kfree(param_value); + return err; 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(unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id 674DF3F7064; Mon, 2 Mar 2026 00:58:25 -0800 (PST) From: Ratheesh Kannoth To: , CC: , , , , , , , , , , , , "Ratheesh Kannoth" Subject: [PATCH net-next 3/5] octeontx2-af: npc: cn20k: add subbank search order control Date: Mon, 2 Mar 2026 14:28:01 +0530 Message-ID: <20260302085803.2449828-4-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260302085803.2449828-1-rkannoth@marvell.com> References: <20260302085803.2449828-1-rkannoth@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: Te5Cox2MsR-jFtBdUVtxttr_jUiSRVaF X-Proofpoint-GUID: Te5Cox2MsR-jFtBdUVtxttr_jUiSRVaF X-Authority-Analysis: v=2.4 cv=UeZciaSN c=1 sm=1 tr=0 ts=69a55137 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=Yq5XynenixoA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=TtqV-g6YmW1Jfm2GSLaY:22 a=M5GUcnROAAAA:8 a=aXqwZ0b04EARCeQHczgA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzAyMDA3NyBTYWx0ZWRfX+yAj2o+Spn05 9KYgA0Ehly+jFSiJBjpSQCnYbKCELoMvoYfyS++hLVAUMfJ/7/0rzN+TF5YC/F8YfgYUr3Ko3n9 sq8K+1oV47xsx/2YHfH5JlSGTlZlfP0zcvpewXtRCNVowEQaW4qHZKXxTu1XXflTMKWdPlv9EDB uABubiWq/WkB4CviprqXxuPk2I6tjNa6yT3biCpwRFw6MjjJ9bpHFFgikrx34ugYLiHIx0BL0Of 6+X6t99y2EYXtbzgAYcpLfeg/3ZA9LVRwxhbyk7pkenpYzBuKg4vJD3NfZ54Qt5XIhzYmdtteX+ lhCk0ay1iq/7Is2gMDaWOsu5KcTsWFcZ3746CoP80hOsKk4HIwDHn/mzqGIJ7s07WXP7dSEQpLr pJT2TzxHoIO5a/D1RZLGqlNNRnxy2uXQ3Ys6qmqYi6aUMBMp2fIclojhXzEoKtUcvlPw5yTCfHq eLOcBo0UNcnkPGqRdIQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-02_02,2026-02-27_03,2025-10-01_01 Content-Type: text/plain; charset="utf-8" CN20K NPC MCAM is split into 32 subbanks that are searched in a predefined order during allocation. Lower-numbered subbanks have higher priority than higher-numbered ones. Add a runtime devlink parameter "srch_order" ( DEVLINK_PARAM_TYPE_U32_ARRAY) to control the order in which subbanks are searched during MCAM allocation. Signed-off-by: Ratheesh Kannoth --- .../ethernet/marvell/octeontx2/af/cn20k/npc.c | 70 ++++++++++++++ .../ethernet/marvell/octeontx2/af/cn20k/npc.h | 2 + .../marvell/octeontx2/af/rvu_devlink.c | 92 +++++++++++++++++-- 3 files changed, 154 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c b/driver= s/net/ethernet/marvell/octeontx2/af/cn20k/npc.c index e854b85ced9e..7f014b414d68 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c @@ -3809,6 +3809,76 @@ static void npc_unlock_all_subbank(void) mutex_unlock(&npc_priv.sb[i].lock); } =20 +int npc_cn20k_search_order_set(struct rvu *rvu, + u32 arr[MAX_NUM_SUB_BANKS], int cnt) +{ + struct npc_mcam *mcam =3D &rvu->hw->mcam; + u32 fslots[MAX_NUM_SUB_BANKS][2]; + u32 uslots[MAX_NUM_SUB_BANKS][2]; + int fcnt =3D 0, ucnt =3D 0; + struct npc_subbank *sb; + unsigned long index; + int idx, val; + void *v; + + if (cnt !=3D npc_priv.num_subbanks) { + dev_err(rvu->dev, "Number of entries(%u) !=3D %u\n", + cnt, npc_priv.num_subbanks); + return -EINVAL; + } + + npc_lock_all_subbank(); + mutex_lock(&mcam->lock); + restrict_valid =3D false; + + for (int i =3D 0; i < cnt; i++) + subbank_srch_order[i] =3D arr[i]; + + xa_for_each(&npc_priv.xa_sb_used, index, v) { + val =3D xa_to_value(v); + uslots[ucnt][0] =3D index; + uslots[ucnt][1] =3D val; + xa_erase(&npc_priv.xa_sb_used, index); + ucnt++; + } + + xa_for_each(&npc_priv.xa_sb_free, index, v) { + val =3D xa_to_value(v); + fslots[fcnt][0] =3D index; + fslots[fcnt][1] =3D val; + xa_erase(&npc_priv.xa_sb_free, index); + fcnt++; + } + + for (int i =3D 0; i < ucnt; i++) { + idx =3D uslots[i][1]; + sb =3D &npc_priv.sb[idx]; + sb->arr_idx =3D subbank_srch_order[sb->idx]; + xa_store(&npc_priv.xa_sb_used, sb->arr_idx, + xa_mk_value(sb->idx), GFP_KERNEL); + } + + for (int i =3D 0; i < fcnt; i++) { + idx =3D fslots[i][1]; + sb =3D &npc_priv.sb[idx]; + sb->arr_idx =3D subbank_srch_order[sb->idx]; + xa_store(&npc_priv.xa_sb_free, sb->arr_idx, + xa_mk_value(sb->idx), GFP_KERNEL); + } + + npc_unlock_all_subbank(); + mutex_unlock(&mcam->lock); + + return 0; +} + +const u32 *npc_cn20k_search_order_get(bool *restricted_order, u32 *sz) +{ + *restricted_order =3D restrict_valid; + *sz =3D npc_priv.num_subbanks; + return subbank_srch_order; +} + /* Only non-ref non-contigous mcam indexes * are picked for defrag process */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h b/driver= s/net/ethernet/marvell/octeontx2/af/cn20k/npc.h index 004a556c7b90..b168ecfbc5c8 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h @@ -343,5 +343,7 @@ int npc_cn20k_defrag(struct rvu *rvu); int npc_mcam_idx_2_subbank_idx(struct rvu *rvu, u16 mcam_idx, struct npc_subbank **sb, int *sb_off); +const u32 *npc_cn20k_search_order_get(bool *restricted_order, u32 *sz); +int npc_cn20k_search_order_set(struct rvu *rvu, u32 arr[32], int cnt); =20 #endif /* NPC_CN20K_H */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c b/driv= ers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c index 287ff0eda152..420cda6d5d5f 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c @@ -1258,6 +1258,7 @@ enum rvu_af_dl_param_id { RVU_AF_DEVLINK_PARAM_ID_NPC_EXACT_FEATURE_DISABLE, RVU_AF_DEVLINK_PARAM_ID_NPC_DEF_RULE_CNTR_ENABLE, RVU_AF_DEVLINK_PARAM_ID_NPC_DEFRAG, + RVU_AF_DEVLINK_PARAM_ID_NPC_SRCH_ORDER, RVU_AF_DEVLINK_PARAM_ID_NIX_MAXLF, }; =20 @@ -1619,12 +1620,83 @@ static int rvu_devlink_eswitch_mode_set(struct devl= ink *devlink, u16 mode, return 0; } =20 +static int rvu_af_dl_npc_srch_order_set(struct devlink *devlink, u32 id, + struct devlink_param_gset_ctx *ctx, + struct netlink_ext_ack *extack) +{ + struct rvu_devlink *rvu_dl =3D devlink_priv(devlink); + struct rvu *rvu =3D rvu_dl->rvu; + + return npc_cn20k_search_order_set(rvu, + ctx->val.u32arr.val, + ctx->val.u32arr.size); +} + +static int rvu_af_dl_npc_srch_order_get(struct devlink *devlink, u32 id, + struct devlink_param_gset_ctx *ctx, + struct netlink_ext_ack *extack) +{ + bool restricted_order; + const u32 *order; + u32 sz; + + order =3D npc_cn20k_search_order_get(&restricted_order, &sz); + ctx->val.u32arr.size =3D sz; + for (int i =3D 0; i < sz; i++) + ctx->val.u32arr.val[i] =3D order[i]; + + return 0; +} + +static int rvu_af_dl_npc_srch_order_validate(struct devlink *devlink, u32 = id, + union devlink_param_value val, + struct netlink_ext_ack *extack) +{ + struct rvu_devlink *rvu_dl =3D devlink_priv(devlink); + struct rvu *rvu =3D rvu_dl->rvu; + bool restricted_order; + unsigned long w =3D 0; + u32 *arr; + u32 sz; + + npc_cn20k_search_order_get(&restricted_order, &sz); + if (sz !=3D val.u32arr.size) { + dev_err(rvu->dev, + "Wrong size %u, should be %u\n", + val.u32arr.size, sz); + return -EINVAL; + } + + arr =3D val.u32arr.val; + for (int i =3D 0; i < sz; i++) { + if (arr[i] >=3D sz) + return -EINVAL; + + w |=3D BIT_ULL(arr[i]); + } + + if (bitmap_weight(&w, sz) !=3D sz) { + dev_err(rvu->dev, + "Duplicate or out-of-range subbank index. %lu\n", + find_first_zero_bit(&w, sz)); + return -EINVAL; + } + + return 0; +} + static const struct devlink_ops rvu_devlink_ops =3D { .eswitch_mode_get =3D rvu_devlink_eswitch_mode_get, .eswitch_mode_set =3D rvu_devlink_eswitch_mode_set, }; =20 -static const struct devlink_param rvu_af_dl_param_defrag[] =3D { +static const struct devlink_param rvu_af_dl_cn20k_params[] =3D { + DEVLINK_PARAM_DRIVER(RVU_AF_DEVLINK_PARAM_ID_NPC_SRCH_ORDER, + "npc_srch_order", DEVLINK_PARAM_TYPE_U32_ARRAY, + BIT(DEVLINK_PARAM_CMODE_RUNTIME), + rvu_af_dl_npc_srch_order_get, + rvu_af_dl_npc_srch_order_set, + rvu_af_dl_npc_srch_order_validate), DEVLINK_PARAM_DRIVER(RVU_AF_DEVLINK_PARAM_ID_NPC_DEFRAG, "npc_defrag", DEVLINK_PARAM_TYPE_STRING, BIT(DEVLINK_PARAM_CMODE_RUNTIME), @@ -1666,13 +1738,13 @@ int rvu_register_dl(struct rvu *rvu) } =20 if (is_cn20k(rvu->pdev)) { - err =3D devlink_params_register(dl, rvu_af_dl_param_defrag, - ARRAY_SIZE(rvu_af_dl_param_defrag)); + err =3D devlink_params_register(dl, rvu_af_dl_cn20k_params, + ARRAY_SIZE(rvu_af_dl_cn20k_params)); if (err) { dev_err(rvu->dev, - "devlink defrag params register failed with error %d", + "devlink cn20k params register failed with error %d", err); - goto err_dl_defrag; + goto err_dl_cn20k_params; } } =20 @@ -1695,10 +1767,10 @@ int rvu_register_dl(struct rvu *rvu) =20 err_dl_exact_match: if (is_cn20k(rvu->pdev)) - devlink_params_unregister(dl, rvu_af_dl_param_defrag, - ARRAY_SIZE(rvu_af_dl_param_defrag)); + devlink_params_unregister(dl, rvu_af_dl_cn20k_params, + ARRAY_SIZE(rvu_af_dl_cn20k_params)); =20 -err_dl_defrag: +err_dl_cn20k_params: devlink_params_unregister(dl, rvu_af_dl_params, ARRAY_SIZE(rvu_af_dl_para= ms)); =20 err_dl_health: @@ -1717,8 +1789,8 @@ void rvu_unregister_dl(struct rvu *rvu) devlink_params_unregister(dl, rvu_af_dl_params, ARRAY_SIZE(rvu_af_dl_para= ms)); =20 if (is_cn20k(rvu->pdev)) - devlink_params_unregister(dl, rvu_af_dl_param_defrag, - ARRAY_SIZE(rvu_af_dl_param_defrag)); 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(unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id 811FD3F7064; Mon, 2 Mar 2026 00:58:30 -0800 (PST) From: Ratheesh Kannoth To: , CC: , , , , , , , , , , , , "Ratheesh Kannoth" Subject: [PATCH net-next 4/5] cteontx2-af: npc: cn20k: dynamically allocate and free default MCAM entries Date: Mon, 2 Mar 2026 14:28:02 +0530 Message-ID: <20260302085803.2449828-5-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260302085803.2449828-1-rkannoth@marvell.com> References: <20260302085803.2449828-1-rkannoth@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: cA1r3zwpJcLJSza5bAZYHsdngq9_GMx8 X-Authority-Analysis: v=2.4 cv=eYUwvrEH c=1 sm=1 tr=0 ts=69a5513c cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=Yq5XynenixoA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=EAYMVhzMl8SCOHhVQcBL:22 a=M5GUcnROAAAA:8 a=4Jugf0Ae5p6shP1wP-EA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-ORIG-GUID: cA1r3zwpJcLJSza5bAZYHsdngq9_GMx8 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzAyMDA3NyBTYWx0ZWRfXzJ0ikHV85izs pRTtzj0NOTP/ZQjussqtWD8vApfT0tsrsak7tbvGWRYIo+aCHIpFx1A1/2X35r+l06ui7JytLjs NLxds5H4kVkrA+WmwHCQj29BKOXTJuNAbjbFwm+qze13yhAvEcOvn0/2ED1NOJyK353zxJqoPuG WvgXwn+O9YcrNSR8BXmlz9LYwQHJpJc7JhReRgOn7RomKN22dMhz1nZNsV8hF9y2aODCib20D1L i7msJ+YFwnJl1gzYi/X+NpJiSDA1yDvTi96uQzLTIKac+IabOHqjUOk3tnfuXSLmfM+M/UEg6Uv 4ap4yEEsWjGXfUqaTJxYS2vvmGPABrpnx6xKkCUR4pRjZ4ig/GbEGgh540jmy2L1K/XOWesBG+T 1WvpE2sljFsHXjBFDoRtold5cMh+sE99PDPCQDos9fYWlufIv3pm3+s6f7gtmcBvSm5W+Ipi276 ojYG/KAZhpoh4CTihBg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-02_02,2026-02-27_03,2025-10-01_01 Content-Type: text/plain; charset="utf-8" Improve MCAM utilization by tying default (broadcast, multicast, promisc, ucast) entry lifetime to NIX LF usage. - On NIX LF alloc (e.g. kernel or DPDK), allocate default MCAM entries if missing; on NIX LF free, release them so they return to the pool. - Add NIX_LF_DONT_FREE_DFT_IDXS so the kernel PF driver can free the NIX LF without releasing default entries (e.g. across suspend/resume). - When NIX LF is used by DPDK, default entries are allocated on first use and freed when the LF is released if NIX_LF_DONT_FREE_DFT_IDXS is not set Signed-off-by: Ratheesh Kannoth --- .../ethernet/marvell/octeontx2/af/cn20k/npc.c | 107 ++++++++++++----- .../ethernet/marvell/octeontx2/af/cn20k/npc.h | 1 + .../net/ethernet/marvell/octeontx2/af/mbox.h | 1 + .../ethernet/marvell/octeontx2/af/rvu_nix.c | 14 +++ .../ethernet/marvell/octeontx2/af/rvu_npc.c | 113 ++++++++++++------ .../ethernet/marvell/octeontx2/nic/otx2_pf.c | 6 +- 6 files changed, 174 insertions(+), 68 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c b/driver= s/net/ethernet/marvell/octeontx2/af/cn20k/npc.c index 7f014b414d68..7ddad605b92d 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c @@ -808,6 +808,11 @@ npc_cn20k_enable_mcam_entry(struct rvu *rvu, int blkad= dr, u64 cfg, hw_prio; u8 kw_type; =20 + if (index < 0 || index >=3D mcam->total_entries) { + WARN(1, "Wrong mcam index %d\n", index); + return; + } + enable ? set_bit(index, npc_priv.en_map) : clear_bit(index, npc_priv.en_map); =20 @@ -1053,6 +1058,11 @@ void npc_cn20k_config_mcam_entry(struct rvu *rvu, in= t blkaddr, int index, int kw =3D 0; u8 kw_type; =20 + if (index < 0 || index >=3D mcam->total_entries) { + WARN(1, "Wrong mcam index %d\n", index); + return; + } + /* Disable before mcam entry update */ npc_cn20k_enable_mcam_entry(rvu, blkaddr, index, false); =20 @@ -1132,6 +1142,11 @@ void npc_cn20k_copy_mcam_entry(struct rvu *rvu, int = blkaddr, u16 src, u16 dest) int bank, i, sb, db; int dbank, sbank; =20 + if (src >=3D mcam->total_entries || dest >=3D mcam->total_entries) { + WARN(1, "Wrong mcam index src=3D%u dest=3D%u\n", src, dest); + return; + } + dbank =3D npc_get_bank(mcam, dest); sbank =3D npc_get_bank(mcam, src); npc_mcam_idx_2_key_type(rvu, src, &src_kwtype); @@ -1190,11 +1205,24 @@ void npc_cn20k_read_mcam_entry(struct rvu *rvu, int= blkaddr, u16 index, int kw =3D 0, bank; u8 kw_type; =20 + if (index >=3D mcam->total_entries) { + WARN(1, "Wrong mcam index %u\n", index); + return; + } + npc_mcam_idx_2_key_type(rvu, index, &kw_type); =20 bank =3D npc_get_bank(mcam, index); index &=3D (mcam->banksize - 1); =20 + cfg =3D rvu_read64(rvu, blkaddr, + NPC_AF_CN20K_MCAMEX_BANKX_ACTIONX_EXT(index, bank, 0)); + entry->action =3D cfg; + + cfg =3D rvu_read64(rvu, blkaddr, + NPC_AF_CN20K_MCAMEX_BANKX_ACTIONX_EXT(index, bank, 1)); + entry->vtag_action =3D cfg; + cfg =3D rvu_read64(rvu, blkaddr, NPC_AF_CN20K_MCAMEX_BANKX_CAMX_INTF_EXT(index, bank, 1)) & 3; @@ -1244,7 +1272,7 @@ void npc_cn20k_read_mcam_entry(struct rvu *rvu, int b= lkaddr, u16 index, bank, 0)); npc_cn20k_fill_entryword(entry, kw + 3, cam0, cam1); - goto read_action; + return; } =20 for (bank =3D 0; bank < mcam->banks_per_entry; bank++, kw =3D kw + 4) { @@ -1289,17 +1317,6 @@ void npc_cn20k_read_mcam_entry(struct rvu *rvu, int = blkaddr, u16 index, npc_cn20k_fill_entryword(entry, kw + 3, cam0, cam1); } =20 -read_action: - /* 'action' is set to same value for both bank '0' and '1'. - * Hence, reading bank '0' should be enough. - */ - cfg =3D rvu_read64(rvu, blkaddr, - NPC_AF_CN20K_MCAMEX_BANKX_ACTIONX_EXT(index, 0, 0)); - entry->action =3D cfg; - - cfg =3D rvu_read64(rvu, blkaddr, - NPC_AF_CN20K_MCAMEX_BANKX_ACTIONX_EXT(index, 0, 1)); - entry->vtag_action =3D cfg; } =20 int rvu_mbox_handler_npc_cn20k_mcam_write_entry(struct rvu *rvu, @@ -1671,8 +1688,8 @@ int npc_mcam_idx_2_key_type(struct rvu *rvu, u16 mcam= _idx, u8 *key_type) =20 /* mcam_idx should be less than (2 * bank depth) */ if (mcam_idx >=3D npc_priv.bank_depth * 2) { - dev_err(rvu->dev, "%s: bad params\n", - __func__); + dev_err(rvu->dev, "%s: bad params mcam_idx=3D%u\n", + __func__, mcam_idx); return -EINVAL; } =20 @@ -4007,6 +4024,13 @@ int npc_cn20k_dft_rules_idx_get(struct rvu *rvu, u16= pcifunc, u16 *bcast, void *val; int i, j; =20 + for (int i =3D 0; i < ARRAY_SIZE(ptr); i++) { + if (!ptr[i]) + continue; + + *ptr[i] =3D USHRT_MAX; + } + if (!npc_priv.init_done) return 0; =20 @@ -4022,7 +4046,6 @@ int npc_cn20k_dft_rules_idx_get(struct rvu *rvu, u16 = pcifunc, u16 *bcast, npc_dft_rule_name[NPC_DFT_RULE_PROMISC_ID], pcifunc); =20 - *ptr[0] =3D USHRT_MAX; return -ESRCH; } =20 @@ -4042,7 +4065,6 @@ int npc_cn20k_dft_rules_idx_get(struct rvu *rvu, u16 = pcifunc, u16 *bcast, npc_dft_rule_name[NPC_DFT_RULE_UCAST_ID], pcifunc); =20 - *ptr[3] =3D USHRT_MAX; return -ESRCH; } =20 @@ -4062,7 +4084,6 @@ int npc_cn20k_dft_rules_idx_get(struct rvu *rvu, u16 = pcifunc, u16 *bcast, __func__, npc_dft_rule_name[i], pcifunc); =20 - *ptr[j] =3D USHRT_MAX; continue; } =20 @@ -4157,7 +4178,7 @@ int rvu_mbox_handler_npc_get_dft_rl_idxs(struct rvu *= rvu, struct msg_req *req, return 0; } =20 -static bool npc_is_cgx_or_lbk(struct rvu *rvu, u16 pcifunc) +bool npc_is_cgx_or_lbk(struct rvu *rvu, u16 pcifunc) { return is_pf_cgxmapped(rvu, rvu_get_pf(rvu->pdev, pcifunc)) || is_lbk_vf(rvu, pcifunc); @@ -4165,9 +4186,10 @@ static bool npc_is_cgx_or_lbk(struct rvu *rvu, u16 p= cifunc) =20 void npc_cn20k_dft_rules_free(struct rvu *rvu, u16 pcifunc) { - struct npc_mcam_free_entry_req free_req =3D { 0 }; + struct npc_mcam *mcam =3D &rvu->hw->mcam; + struct rvu_npc_mcam_rule *rule, *tmp; unsigned long index; - struct msg_rsp rsp; + int blkaddr; u16 ptr[4]; int rc, i; void *map; @@ -4192,7 +4214,7 @@ void npc_cn20k_dft_rules_free(struct rvu *rvu, u16 pc= ifunc) index =3D NPC_DFT_RULE_ID_MK(pcifunc, NPC_DFT_RULE_PROMISC_ID); map =3D xa_erase(&npc_priv.xa_pf2dfl_rmap, index); if (!map) - dev_dbg(rvu->dev, + dev_err(rvu->dev, "%s: Err from delete %s mcam idx from xarray (pcifunc=3D%#x\n", __func__, npc_dft_rule_name[NPC_DFT_RULE_PROMISC_ID], @@ -4206,7 +4228,7 @@ void npc_cn20k_dft_rules_free(struct rvu *rvu, u16 pc= ifunc) index =3D NPC_DFT_RULE_ID_MK(pcifunc, NPC_DFT_RULE_UCAST_ID); map =3D xa_erase(&npc_priv.xa_pf2dfl_rmap, index); if (!map) - dev_dbg(rvu->dev, + dev_err(rvu->dev, "%s: Err from delete %s mcam idx from xarray (pcifunc=3D%#x\n", __func__, npc_dft_rule_name[NPC_DFT_RULE_UCAST_ID], @@ -4220,21 +4242,46 @@ void npc_cn20k_dft_rules_free(struct rvu *rvu, u16 = pcifunc) index =3D NPC_DFT_RULE_ID_MK(pcifunc, i); map =3D xa_erase(&npc_priv.xa_pf2dfl_rmap, index); if (!map) - dev_dbg(rvu->dev, + dev_err(rvu->dev, "%s: Err from delete %s mcam idx from xarray (pcifunc=3D%#x\n", __func__, npc_dft_rule_name[i], pcifunc); } =20 free_rules: + blkaddr =3D rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); + if (blkaddr < 0) + return; =20 - free_req.hdr.pcifunc =3D pcifunc; - free_req.all =3D 1; - rc =3D rvu_mbox_handler_npc_mcam_free_entry(rvu, &free_req, &rsp); - if (rc) - dev_err(rvu->dev, - "%s: Error deleting default entries (pcifunc=3D%#x\n", - __func__, pcifunc); + for (int i =3D 0; i < 4; i++) { + if (ptr[i] =3D=3D USHRT_MAX) + continue; + + mutex_lock(&mcam->lock); + npc_mcam_clear_bit(mcam, ptr[i]); + mcam->entry2pfvf_map[ptr[i]] =3D NPC_MCAM_INVALID_MAP; + npc_cn20k_enable_mcam_entry(rvu, blkaddr, ptr[i], false); + mcam->entry2target_pffunc[ptr[i]] =3D 0x0; + mutex_unlock(&mcam->lock); + + rc =3D npc_cn20k_idx_free(rvu, &ptr[i], 1); + if (rc) + dev_err(rvu->dev, + "%s:%d Error deleting default entries (pcifunc=3D%#x) mcam_idx=3D%u\n", + __func__, __LINE__, pcifunc, ptr[i]); + } + + mutex_lock(&mcam->lock); + list_for_each_entry_safe(rule, tmp, &mcam->mcam_rules, list) { + for (int i =3D 0; i < 4; i++) { + if (ptr[i] !=3D rule->entry) + continue; + + list_del(&rule->list); + kfree(rule); + } + } + mutex_unlock(&mcam->lock); } =20 int npc_cn20k_dft_rules_alloc(struct rvu *rvu, u16 pcifunc) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h b/driver= s/net/ethernet/marvell/octeontx2/af/cn20k/npc.h index b168ecfbc5c8..0fa56f5382b4 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h @@ -345,5 +345,6 @@ int npc_mcam_idx_2_subbank_idx(struct rvu *rvu, u16 mca= m_idx, int *sb_off); const u32 *npc_cn20k_search_order_get(bool *restricted_order, u32 *sz); int npc_cn20k_search_order_set(struct rvu *rvu, u32 arr[32], int cnt); +bool npc_is_cgx_or_lbk(struct rvu *rvu, u16 pcifunc); =20 #endif /* NPC_CN20K_H */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net= /ethernet/marvell/octeontx2/af/mbox.h index dc42c81c0942..e07fbf842b94 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -1009,6 +1009,7 @@ struct nix_lf_free_req { struct mbox_msghdr hdr; #define NIX_LF_DISABLE_FLOWS BIT_ULL(0) #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1) +#define NIX_LF_DONT_FREE_DFT_IDXS BIT_ULL(2) u64 flags; }; =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_nix.c index badfa1d64252..68eb25e7074c 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c @@ -16,6 +16,7 @@ #include "cgx.h" #include "lmac_common.h" #include "rvu_npc_hash.h" +#include "cn20k/npc.h" =20 static void nix_free_tx_vtag_entries(struct rvu *rvu, u16 pcifunc); static int rvu_nix_get_bpid(struct rvu *rvu, struct nix_bp_cfg_req *req, @@ -1684,6 +1685,12 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu, if (is_sdp_pfvf(rvu, pcifunc)) intf =3D NIX_INTF_TYPE_SDP; =20 + if (is_cn20k(rvu->pdev)) { + rc =3D npc_cn20k_dft_rules_alloc(rvu, pcifunc); + if (rc) + goto free_dft; + } + err =3D nix_interface_init(rvu, pcifunc, intf, nixlf, rsp, !!(req->flags & NIX_LF_LBK_BLK_SEL)); if (err) @@ -1703,6 +1710,10 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu, nix_ctx_free(rvu, pfvf); rc =3D -ENOMEM; =20 +free_dft: + if (is_cn20k(rvu->pdev)) + npc_cn20k_dft_rules_free(rvu, pcifunc); + exit: /* Set macaddr of this PF/VF */ ether_addr_copy(rsp->mac_addr, pfvf->mac_addr); @@ -1775,6 +1786,9 @@ int rvu_mbox_handler_nix_lf_free(struct rvu *rvu, str= uct nix_lf_free_req *req, =20 nix_ctx_free(rvu, pfvf); =20 + if (is_cn20k(rvu->pdev) && !(req->flags & NIX_LF_DONT_FREE_DFT_IDXS)) + npc_cn20k_dft_rules_free(rvu, pcifunc); + return 0; } =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_npc.c index c2ca5ed1d028..d4ccb966b4f5 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c @@ -165,12 +165,20 @@ int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, =20 switch (type) { case NIXLF_BCAST_ENTRY: + if (bcast =3D=3D USHRT_MAX) + return -EINVAL; return bcast; case NIXLF_ALLMULTI_ENTRY: + if (mcast =3D=3D USHRT_MAX) + return -EINVAL; return mcast; case NIXLF_PROMISC_ENTRY: + if (promisc =3D=3D USHRT_MAX) + return -EINVAL; return promisc; case NIXLF_UCAST_ENTRY: + if (ucast =3D=3D USHRT_MAX) + return -EINVAL; return ucast; default: return -EINVAL; @@ -237,12 +245,8 @@ void npc_enable_mcam_entry(struct rvu *rvu, struct npc= _mcam *mcam, int bank =3D npc_get_bank(mcam, index); int actbank =3D bank; =20 - if (is_cn20k(rvu->pdev)) { - if (index < 0 || index >=3D mcam->banksize * mcam->banks) - return; - + if (is_cn20k(rvu->pdev)) return npc_cn20k_enable_mcam_entry(rvu, blkaddr, index, enable); - } =20 index &=3D (mcam->banksize - 1); for (; bank < (actbank + mcam->banks_per_entry); bank++) { @@ -1158,16 +1162,18 @@ void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu= , u16 pcifunc, int nixlf, /* If PF's promiscuous entry is enabled, * Set RSS action for that entry as well */ - npc_update_rx_action_with_alg_idx(rvu, action, pfvf, index, - blkaddr, alg_idx); + if (index >=3D 0) + npc_update_rx_action_with_alg_idx(rvu, action, pfvf, + index, blkaddr, alg_idx); =20 index =3D npc_get_nixlf_mcam_index(mcam, pcifunc, nixlf, NIXLF_ALLMULTI_ENTRY); /* If PF's allmulti entry is enabled, * Set RSS action for that entry as well */ - npc_update_rx_action_with_alg_idx(rvu, action, pfvf, index, - blkaddr, alg_idx); + if (index >=3D 0) + npc_update_rx_action_with_alg_idx(rvu, action, pfvf, + index, blkaddr, alg_idx); } } =20 @@ -1212,8 +1218,13 @@ static void npc_enadis_default_entries(struct rvu *r= vu, u16 pcifunc, { struct rvu_pfvf *pfvf =3D rvu_get_pfvf(rvu, pcifunc); struct npc_mcam *mcam =3D &rvu->hw->mcam; + int type =3D NIXLF_UCAST_ENTRY; int index, blkaddr; =20 + /* only CGX or LBK interfaces have default entries */ + if (is_cn20k(rvu->pdev) && !npc_is_cgx_or_lbk(rvu, pcifunc)) + return; + blkaddr =3D rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); if (blkaddr < 0) return; @@ -1221,8 +1232,11 @@ static void npc_enadis_default_entries(struct rvu *r= vu, u16 pcifunc, /* Ucast MCAM match entry of this PF/VF */ if (npc_is_feature_supported(rvu, BIT_ULL(NPC_DMAC), pfvf->nix_rx_intf)) { + if (is_cn20k(rvu->pdev) && is_lbk_vf(rvu, pcifunc)) + type =3D NIXLF_PROMISC_ENTRY; + index =3D npc_get_nixlf_mcam_index(mcam, pcifunc, - nixlf, NIXLF_UCAST_ENTRY); + nixlf, type); npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); } =20 @@ -1232,9 +1246,13 @@ static void npc_enadis_default_entries(struct rvu *r= vu, u16 pcifunc, if ((pcifunc & RVU_PFVF_FUNC_MASK) && !rvu->hw->cap.nix_rx_multicast) return; =20 + type =3D NIXLF_BCAST_ENTRY; + if (is_cn20k(rvu->pdev) && is_lbk_vf(rvu, pcifunc)) + type =3D NIXLF_PROMISC_ENTRY; + /* add/delete pf_func to broadcast MCE list */ npc_enadis_default_mce_entry(rvu, pcifunc, nixlf, - NIXLF_BCAST_ENTRY, enable); + type, enable); } =20 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nix= lf) @@ -1244,6 +1262,9 @@ void rvu_npc_disable_default_entries(struct rvu *rvu,= u16 pcifunc, int nixlf) =20 npc_enadis_default_entries(rvu, pcifunc, nixlf, false); =20 + if (is_cn20k(rvu->pdev) && is_vf(pcifunc)) + return; + /* Delete multicast and promisc MCAM entries */ npc_enadis_default_mce_entry(rvu, pcifunc, nixlf, NIXLF_ALLMULTI_ENTRY, false); @@ -1345,6 +1366,8 @@ void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 p= cifunc, int nixlf) /* Free all MCAM counters owned by this 'pcifunc' */ npc_mcam_free_all_counters(rvu, mcam, pcifunc); =20 + rvu_npc_disable_default_entries(rvu, pcifunc, nixlf); + /* Delete MCAM entries owned by this 'pcifunc' */ list_for_each_entry_safe(rule, tmp, &mcam->mcam_rules, list) { if (rule->owner =3D=3D pcifunc && !rule->default_rule) { @@ -1355,7 +1378,6 @@ void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 p= cifunc, int nixlf) =20 mutex_unlock(&mcam->lock); =20 - rvu_npc_disable_default_entries(rvu, pcifunc, nixlf); } =20 static void npc_program_mkex_rx(struct rvu *rvu, int blkaddr, @@ -2504,32 +2526,46 @@ void npc_mcam_clear_bit(struct npc_mcam *mcam, u16 = index) static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mc= am, int blkaddr, u16 pcifunc) { + u16 dft_idxs[NPC_DFT_RULE_MAX_ID] =3D {[0 ... NPC_DFT_RULE_MAX_ID - 1] = =3D USHRT_MAX}; u16 index, cntr; int rc; =20 + npc_cn20k_dft_rules_idx_get(rvu, pcifunc, + &dft_idxs[NPC_DFT_RULE_BCAST_ID], + &dft_idxs[NPC_DFT_RULE_MCAST_ID], + &dft_idxs[NPC_DFT_RULE_PROMISC_ID], + &dft_idxs[NPC_DFT_RULE_UCAST_ID]); + /* Scan all MCAM entries and free the ones mapped to 'pcifunc' */ for (index =3D 0; index < mcam->bmap_entries; index++) { - if (mcam->entry2pfvf_map[index] =3D=3D pcifunc) { - mcam->entry2pfvf_map[index] =3D NPC_MCAM_INVALID_MAP; - /* Free the entry in bitmap */ - npc_mcam_clear_bit(mcam, index); - /* Disable the entry */ - npc_enable_mcam_entry(rvu, mcam, blkaddr, index, false); - - /* Update entry2counter mapping */ - cntr =3D mcam->entry2cntr_map[index]; - if (cntr !=3D NPC_MCAM_INVALID_MAP) - npc_unmap_mcam_entry_and_cntr(rvu, mcam, - blkaddr, index, - cntr); - mcam->entry2target_pffunc[index] =3D 0x0; - if (is_cn20k(rvu->pdev)) { - rc =3D npc_cn20k_idx_free(rvu, &index, 1); - if (rc) - dev_err(rvu->dev, - "Failed to free mcam idx=3D%u pcifunc=3D%#x\n", - index, pcifunc); - } + if (mcam->entry2pfvf_map[index] !=3D pcifunc) + continue; + + mcam->entry2pfvf_map[index] =3D NPC_MCAM_INVALID_MAP; + /* Free the entry in bitmap */ + npc_mcam_clear_bit(mcam, index); + /* Disable the entry */ + npc_enable_mcam_entry(rvu, mcam, blkaddr, index, false); + + /* Update entry2counter mapping */ + cntr =3D mcam->entry2cntr_map[index]; + if (cntr !=3D NPC_MCAM_INVALID_MAP) + npc_unmap_mcam_entry_and_cntr(rvu, mcam, + blkaddr, index, + cntr); + mcam->entry2target_pffunc[index] =3D 0x0; + if (is_cn20k(rvu->pdev)) { + if (dft_idxs[NPC_DFT_RULE_BCAST_ID] =3D=3D index || + dft_idxs[NPC_DFT_RULE_MCAST_ID] =3D=3D index || + dft_idxs[NPC_DFT_RULE_PROMISC_ID] =3D=3D index || + dft_idxs[NPC_DFT_RULE_UCAST_ID] =3D=3D index) + continue; + + rc =3D npc_cn20k_idx_free(rvu, &index, 1); + if (rc) + dev_err(rvu->dev, + "Failed to free mcam idx=3D%u pcifunc=3D%#x\n", + index, pcifunc); } } } @@ -3917,13 +3953,22 @@ void rvu_npc_clear_ucast_entry(struct rvu *rvu, int= pcifunc, int nixlf) struct npc_mcam *mcam =3D &rvu->hw->mcam; struct rvu_npc_mcam_rule *rule; int ucast_idx, blkaddr; + u8 type; =20 blkaddr =3D rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); if (blkaddr < 0) return; =20 + type =3D NIXLF_UCAST_ENTRY; + if (is_cn20k(rvu->pdev) && is_lbk_vf(rvu, pcifunc)) + type =3D NIXLF_PROMISC_ENTRY; + ucast_idx =3D npc_get_nixlf_mcam_index(mcam, pcifunc, - nixlf, NIXLF_UCAST_ENTRY); + nixlf, type); + + /* In cn20k, default rules are freed before detach rsrc */ + if (ucast_idx < 0) + return; =20 npc_enable_mcam_entry(rvu, mcam, blkaddr, ucast_idx, false); =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers= /net/ethernet/marvell/octeontx2/nic/otx2_pf.c index ee623476e5ff..81b088f5a016 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c @@ -1053,7 +1053,6 @@ irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void= *pf_irq) /* Clear the IRQ */ otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); =20 - mbox_data =3D otx2_read64(pf, RVU_PF_PFAF_MBOX0); =20 if (mbox_data & MBOX_UP_MSG) { @@ -1729,7 +1728,7 @@ int otx2_init_hw_resources(struct otx2_nic *pf) mutex_lock(&mbox->lock); free_req =3D otx2_mbox_alloc_msg_nix_lf_free(mbox); if (free_req) { - free_req->flags =3D NIX_LF_DISABLE_FLOWS; + free_req->flags =3D NIX_LF_DISABLE_FLOWS | NIX_LF_DONT_FREE_DFT_IDXS; if (otx2_sync_mbox_msg(mbox)) dev_err(pf->dev, "%s failed to free nixlf\n", __func__); } @@ -1803,7 +1802,7 @@ void otx2_free_hw_resources(struct otx2_nic *pf) /* Reset NIX LF */ free_req =3D otx2_mbox_alloc_msg_nix_lf_free(mbox); if (free_req) { - free_req->flags =3D NIX_LF_DISABLE_FLOWS; + free_req->flags =3D NIX_LF_DISABLE_FLOWS | NIX_LF_DONT_FREE_DFT_IDXS; if (!(pf->flags & OTX2_FLAG_PF_SHUTDOWN)) free_req->flags |=3D NIX_LF_DONT_FREE_TX_VTAG; if (otx2_sync_mbox_msg(mbox)) @@ -1926,7 +1925,6 @@ int otx2_alloc_queue_mem(struct otx2_nic *pf) struct otx2_qset *qset =3D &pf->qset; struct otx2_cq_poll *cq_poll; =20 - /* RQ and SQs are mapped to different CQs, * so find out max CQ IRQs (i.e CINTs) needed. */ --=20 2.43.0 From nobody Thu Apr 16 06:47:03 2026 Received: from mx0a-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B9F838CFE5; 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(unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id F09313F7064; Mon, 2 Mar 2026 00:58:35 -0800 (PST) From: Ratheesh Kannoth To: , CC: , , , , , , , , , , , , "Ratheesh Kannoth" Subject: [PATCH net-next 5/5] octeontx2-af: Add support for loading custom KPU profile from filesystem Date: Mon, 2 Mar 2026 14:28:03 +0530 Message-ID: <20260302085803.2449828-6-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260302085803.2449828-1-rkannoth@marvell.com> References: <20260302085803.2449828-1-rkannoth@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: PrFm2Y0sgJZOR6gpMXQoO_va1Awp2pYp X-Proofpoint-GUID: PrFm2Y0sgJZOR6gpMXQoO_va1Awp2pYp X-Authority-Analysis: v=2.4 cv=UeZciaSN c=1 sm=1 tr=0 ts=69a55142 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=Yq5XynenixoA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=TtqV-g6YmW1Jfm2GSLaY:22 a=M5GUcnROAAAA:8 a=zDq0wIghxDI9MWVYsr4A:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzAyMDA3NyBTYWx0ZWRfX4DrS3flFsk0Z 4GKYf2/6DYs7mdhyZP5OlWy9oI9yTOcHJLEhSxQB677HXzHxmylbRFOlAtUeE9M5GHwIYGBfAgt q2uQIeayeT82TI7vfvv2bAI7dWjgmw50vViV2fCexHHcNQ26NoAtl3DMZRKjU/w7HUKU0isGy2P KNzH7iD+ow+MoTdUMxArS61nkxpbNkFz8hwpx7CBa6Oa1MDrm/m0tpJw7ysNqpyo+z2shRIUsMA 3+hjQ9VzTuQ0d+P4SS85GG684pJLq5vldm5lCqtV2dVAbcG6jhY8bG9UHSfH73sfahBtXC1pj0G oSK8Ue7G3KL3zNGYHJGvdYd+x9mOCwqq3PoZdBhxv9ZXqz9yqVFLVqMgGeoCXs0ZJ8p1I29Df67 9SxC77Iz7emXwbrFVybVlwk5fizUf+ACfMugWtxBV7eRhCNBdwNTRiy493ImZPyKbS4KR9D3+Jr SYFdnhBQjO1rJFS8epg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-02_02,2026-02-27_03,2025-10-01_01 Content-Type: text/plain; charset="utf-8" Flashing updated firmware on deployed devices is cumbersome. Provide a mechanism to load a custom KPU (Key Parse Unit) profile directly from the filesystem at module load time. When the rvu_af module is loaded with the kpu_profile parameter, the specified profile is read from /lib/firmware/kpu and programmed into the KPU registers. Add npc_kpu_profile_cam2 for the extended cam format used by filesystem-loaded profiles and support ptype/ptype_mask in npc_config_kpucam when profile->from_fs is set. Usage: 1. Copy the KPU profile file to /lib/firmware/kpu. 2. Build OCTEONTX2_AF as a module. 3. Load: insmod rvu_af.ko kpu_profile=3D Signed-off-by: Ratheesh Kannoth --- .../net/ethernet/marvell/octeontx2/af/npc.h | 14 ++ .../net/ethernet/marvell/octeontx2/af/rvu.h | 3 +- .../ethernet/marvell/octeontx2/af/rvu_npc.c | 163 +++++++++++++++--- .../ethernet/marvell/octeontx2/af/rvu_reg.h | 1 + 4 files changed, 153 insertions(+), 28 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/npc.h b/drivers/net/= ethernet/marvell/octeontx2/af/npc.h index cefc5d70f3e4..5928c4d3cc8b 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/npc.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/npc.h @@ -265,6 +265,19 @@ struct npc_kpu_profile_cam { u16 dp2_mask; } __packed; =20 +struct npc_kpu_profile_cam2 { + u8 state; + u8 state_mask; + u16 dp0; + u16 dp0_mask; + u16 dp1; + u16 dp1_mask; + u16 dp2; + u16 dp2_mask; + u8 ptype; + u8 ptype_mask; +} __packed; + struct npc_kpu_profile_action { u8 errlev; u8 errcode; @@ -290,6 +303,7 @@ struct npc_kpu_profile { int action_entries; struct npc_kpu_profile_cam *cam; struct npc_kpu_profile_action *action; + struct npc_kpu_profile_cam2 *cam2; }; =20 /* NPC KPU register formats */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/= ethernet/marvell/octeontx2/af/rvu.h index a466181cf908..7b663ec0fd8c 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h @@ -554,7 +554,7 @@ struct npc_kpu_profile_adapter { u64 version; const struct npc_lt_def_cfg *lt_def; const struct npc_kpu_profile_action *ikpu; /* array[pkinds] */ - const struct npc_kpu_profile *kpu; /* array[kpus] */ + struct npc_kpu_profile *kpu; /* array[kpus] */ union npc_mcam_key_prfl { struct npc_mcam_kex *mkex; /* used for cn9k and cn10k */ @@ -564,6 +564,7 @@ struct npc_kpu_profile_adapter { bool custom; size_t pkinds; size_t kpus; + bool from_fs; }; =20 #define RVU_SWITCH_LBK_CHAN 63 diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_npc.c index d4ccb966b4f5..9d92ff5e075d 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c @@ -1579,8 +1579,12 @@ static void npc_config_kpucam(struct rvu *rvu, int b= lkaddr, const struct npc_kpu_profile_cam *kpucam, int kpu, int entry) { + const struct npc_kpu_profile_cam2 *kpucam2 =3D (void *)kpucam; + struct npc_kpu_profile_adapter *profile =3D &rvu->kpu; struct npc_kpu_cam cam0 =3D {0}; struct npc_kpu_cam cam1 =3D {0}; + u64 *val =3D (u64 *)&cam1; + u64 *mask =3D (u64 *)&cam0; =20 cam1.state =3D kpucam->state & kpucam->state_mask; cam1.dp0_data =3D kpucam->dp0 & kpucam->dp0_mask; @@ -1592,6 +1596,14 @@ static void npc_config_kpucam(struct rvu *rvu, int b= lkaddr, cam0.dp1_data =3D ~kpucam->dp1 & kpucam->dp1_mask; cam0.dp2_data =3D ~kpucam->dp2 & kpucam->dp2_mask; =20 + if (profile->from_fs) { + u8 ptype =3D kpucam2->ptype; + u8 pmask =3D kpucam2->ptype_mask; + + *val |=3D FIELD_PREP(GENMASK_ULL(57, 56), ptype & pmask); + *mask |=3D FIELD_PREP(GENMASK_ULL(57, 56), ~ptype & pmask); + } + rvu_write64(rvu, blkaddr, NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 0), *(u64 *)&cam0); rvu_write64(rvu, blkaddr, @@ -1606,6 +1618,7 @@ u64 npc_enable_mask(int count) static void npc_program_kpu_profile(struct rvu *rvu, int blkaddr, int kpu, const struct npc_kpu_profile *profile) { + struct npc_kpu_profile_adapter *adapter =3D &rvu->kpu; int entry, num_entries, max_entries; u64 entry_mask; =20 @@ -1617,10 +1630,15 @@ static void npc_program_kpu_profile(struct rvu *rvu= , int blkaddr, int kpu, =20 max_entries =3D rvu->hw->npc_kpu_entries; =20 + WARN(profile->cam_entries > max_entries, + "KPU%u: err: hw max entries=3D%u, input entries=3D%u\n", + kpu, rvu->hw->npc_kpu_entries, profile->cam_entries); + /* Program CAM match entries for previous KPU extracted data */ num_entries =3D min_t(int, profile->cam_entries, max_entries); for (entry =3D 0; entry < num_entries; entry++) npc_config_kpucam(rvu, blkaddr, + adapter->from_fs ? (void *)&profile->cam2[entry] : &profile->cam[entry], kpu, entry); =20 /* Program this KPU's actions */ @@ -1674,22 +1692,44 @@ static void npc_prepare_default_kpu(struct rvu *rvu, npc_cn20k_update_action_entries_n_flags(rvu, profile); } =20 +static int npc_alloc_kpu_cam2_n_action(struct rvu *rvu, int kpu_num, + int num_entries) +{ + struct npc_kpu_profile_adapter *adapter =3D &rvu->kpu; + struct npc_kpu_profile *kpu; + + kpu =3D &adapter->kpu[kpu_num]; + + kpu->cam2 =3D devm_kcalloc(rvu->dev, num_entries, + sizeof(*kpu->cam2), GFP_KERNEL); + if (!kpu->cam2) + return -ENOMEM; + + kpu->action =3D devm_kcalloc(rvu->dev, num_entries, + sizeof(*kpu->action), GFP_KERNEL); + if (!kpu->action) + return -ENOMEM; + + return 0; +} + static int npc_apply_custom_kpu(struct rvu *rvu, - struct npc_kpu_profile_adapter *profile) + struct npc_kpu_profile_adapter *profile, + bool from_fs) { size_t hdr_sz =3D sizeof(struct npc_kpu_profile_fwdata), offset =3D 0; struct npc_kpu_profile_action *action; + struct npc_kpu_profile_fwdata *sfw; struct npc_kpu_profile_fwdata *fw; + struct npc_kpu_profile_cam2 *cam2; struct npc_kpu_profile_cam *cam; struct npc_kpu_fwdata *fw_kpu; - int entries; + int entries, ret; u16 kpu, entry; =20 if (is_cn20k(rvu->pdev)) return npc_cn20k_apply_custom_kpu(rvu, profile); =20 - fw =3D rvu->kpu_fwdata; - if (rvu->kpu_fwdata_sz < hdr_sz) { dev_warn(rvu->dev, "Invalid KPU profile size\n"); return -EINVAL; @@ -1727,31 +1767,77 @@ static int npc_apply_custom_kpu(struct rvu *rvu, return -EINVAL; } =20 + sfw =3D devm_kcalloc(rvu->dev, 1, sizeof(*sfw), GFP_KERNEL); + if (!sfw) + return -ENOMEM; + + fw =3D rvu->kpu_fwdata; + memcpy(sfw, fw, sizeof(*sfw)); + profile->custom =3D 1; - profile->name =3D fw->name; + profile->name =3D sfw->name; profile->version =3D le64_to_cpu(fw->version); - profile->mcam_kex_prfl.mkex =3D &fw->mkex; - profile->lt_def =3D &fw->lt_def; + profile->mcam_kex_prfl.mkex =3D &sfw->mkex; + profile->lt_def =3D &sfw->lt_def; + + /* Binary blob contains ikpu actions entries at start of data[0] */ + if (from_fs) { + action =3D (struct npc_kpu_profile_action *)(fw->data + offset); + memcpy((void *)profile->ikpu, action, sizeof(ikpu_action_entries)); + offset +=3D sizeof(ikpu_action_entries); + } =20 for (kpu =3D 0; kpu < fw->kpus; kpu++) { fw_kpu =3D (struct npc_kpu_fwdata *)(fw->data + offset); - if (fw_kpu->entries > KPU_MAX_CST_ENT) - dev_warn(rvu->dev, - "Too many custom entries on KPU%d: %d > %d\n", - kpu, fw_kpu->entries, KPU_MAX_CST_ENT); - entries =3D min(fw_kpu->entries, KPU_MAX_CST_ENT); - cam =3D (struct npc_kpu_profile_cam *)fw_kpu->data; - offset +=3D sizeof(*fw_kpu) + fw_kpu->entries * sizeof(*cam); + if (!from_fs) { + if (fw_kpu->entries > KPU_MAX_CST_ENT) + dev_warn(rvu->dev, + "Too many custom entries on KPU%d: %d > %d\n", + kpu, fw_kpu->entries, KPU_MAX_CST_ENT); + entries =3D min(fw_kpu->entries, KPU_MAX_CST_ENT); + cam =3D (struct npc_kpu_profile_cam *)fw_kpu->data; + offset +=3D sizeof(*fw_kpu) + fw_kpu->entries * sizeof(*cam); + action =3D (struct npc_kpu_profile_action *)(fw->data + offset); + offset +=3D fw_kpu->entries * sizeof(*action); + if (rvu->kpu_fwdata_sz < hdr_sz + offset) { + dev_warn(rvu->dev, + "Profile size mismatch on KPU%i parsing.\n", + kpu + 1); + return -EINVAL; + } + for (entry =3D 0; entry < entries; entry++) { + profile->kpu[kpu].cam[entry] =3D cam[entry]; + profile->kpu[kpu].action[entry] =3D action[entry]; + } + continue; + } + entries =3D fw_kpu->entries; + dev_info(rvu->dev, + "Loading %u entries on KPU%d\n", entries, kpu); + + cam2 =3D (struct npc_kpu_profile_cam2 *)fw_kpu->data; + offset +=3D sizeof(*fw_kpu) + fw_kpu->entries * sizeof(*cam2); action =3D (struct npc_kpu_profile_action *)(fw->data + offset); offset +=3D fw_kpu->entries * sizeof(*action); if (rvu->kpu_fwdata_sz < hdr_sz + offset) { dev_warn(rvu->dev, - "Profile size mismatch on KPU%i parsing.\n", + "profile size mismatch on kpu%i parsing.\n", kpu + 1); return -EINVAL; } + + profile->kpu[kpu].cam_entries =3D entries; + profile->kpu[kpu].action_entries =3D entries; + ret =3D npc_alloc_kpu_cam2_n_action(rvu, kpu, entries); + if (ret) { + dev_warn(rvu->dev, + "profile entry allocation failed for kpu=3D%d for %d entries\n", + kpu, entries); + return -EINVAL; + } + for (entry =3D 0; entry < entries; entry++) { - profile->kpu[kpu].cam[entry] =3D cam[entry]; + profile->kpu[kpu].cam2[entry] =3D cam2[entry]; profile->kpu[kpu].action[entry] =3D action[entry]; } } @@ -1849,7 +1935,10 @@ void npc_load_kpu_profile(struct rvu *rvu) struct npc_kpu_profile_adapter *profile =3D &rvu->kpu; const char *kpu_profile =3D rvu->kpu_pfl_name; const struct firmware *fw =3D NULL; - bool retry_fwdb =3D false; + int len, ret; + char *path; + + profile->from_fs =3D false; =20 /* If user not specified profile customization */ if (!strncmp(kpu_profile, def_pfl_name, KPU_NAME_LEN)) @@ -1862,27 +1951,45 @@ void npc_load_kpu_profile(struct rvu *rvu) * Firmware database method. * Default KPU profile. */ - if (!request_firmware_direct(&fw, kpu_profile, rvu->dev)) { + +#define PDIR "kpu/" + len =3D strlen(kpu_profile) + sizeof(PDIR); + path =3D kmalloc(len, GFP_KERNEL); + + strscpy(path, PDIR, len); + strcat(path, kpu_profile); + if (!request_firmware_direct(&fw, path, rvu->dev)) { dev_info(rvu->dev, "Loading KPU profile from firmware: %s\n", - kpu_profile); + path); rvu->kpu_fwdata =3D kzalloc(fw->size, GFP_KERNEL); if (rvu->kpu_fwdata) { memcpy(rvu->kpu_fwdata, fw->data, fw->size); rvu->kpu_fwdata_sz =3D fw->size; } release_firmware(fw); - retry_fwdb =3D true; - goto program_kpu; + kfree(path); + + ret =3D npc_apply_custom_kpu(rvu, profile, true); + kfree(rvu->kpu_fwdata); + rvu->kpu_fwdata =3D NULL; + if (ret) { + rvu->kpu_fwdata_sz =3D 0; + npc_prepare_default_kpu(rvu, profile); + goto load_image_fwdb; + } + + profile->from_fs =3D true; + return; } + kfree(path); =20 load_image_fwdb: /* Loading the KPU profile using firmware database */ if (npc_load_kpu_profile_fwdb(rvu, kpu_profile)) goto revert_to_default; =20 -program_kpu: /* Apply profile customization if firmware was loaded. */ - if (!rvu->kpu_fwdata_sz || npc_apply_custom_kpu(rvu, profile)) { + if (!rvu->kpu_fwdata_sz || npc_apply_custom_kpu(rvu, profile, false)) { /* If image from firmware filesystem fails to load or invalid * retry with firmware database method. */ @@ -1896,10 +2003,6 @@ void npc_load_kpu_profile(struct rvu *rvu) } rvu->kpu_fwdata =3D NULL; rvu->kpu_fwdata_sz =3D 0; - if (retry_fwdb) { - retry_fwdb =3D false; - goto load_image_fwdb; - } } =20 dev_warn(rvu->dev, @@ -1923,6 +2026,7 @@ void npc_load_kpu_profile(struct rvu *rvu) =20 static void npc_parser_profile_init(struct rvu *rvu, int blkaddr) { + struct npc_kpu_profile_adapter *profile =3D &rvu->kpu; struct rvu_hwinfo *hw =3D rvu->hw; int num_pkinds, num_kpus, idx; =20 @@ -1954,6 +2058,11 @@ static void npc_parser_profile_init(struct rvu *rvu,= int blkaddr) =20 for (idx =3D 0; idx < num_kpus; idx++) npc_program_kpu_profile(rvu, blkaddr, idx, &rvu->kpu.kpu[idx]); + + if (profile->from_fs) { + rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_TYPE(54), 0x03); + rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_TYPE(58), 0x03); + } } =20 void npc_mcam_rsrcs_deinit(struct rvu *rvu) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_reg.h index 62cdc714ba57..ab89b8c6e490 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h @@ -596,6 +596,7 @@ #define NPC_AF_INTFX_KEX_CFG(a) (0x01010 | (a) << 8) #define NPC_AF_PKINDX_ACTION0(a) (0x80000ull | (a) << 6) #define NPC_AF_PKINDX_ACTION1(a) (0x80008ull | (a) << 6) +#define NPC_AF_PKINDX_TYPE(a) (0x80010ull | (a) << 6) #define NPC_AF_PKINDX_CPI_DEFX(a, b) (0x80020ull | (a) << 6 | (b) << 3) #define NPC_AF_KPUX_ENTRYX_CAMX(a, b, c) \ (0x100000 | (a) << 14 | (b) << 6 | (c) << 3) --=20 2.43.0