From nobody Thu Apr 16 06:52:57 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B3DE2DB7BE; Mon, 2 Mar 2026 06:33:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772433185; cv=none; b=T+AAknnPQh4WZ0rOYLseV39nZmFRDIxoVTLxLT019StF3isRZliC5aKNoh6HAQBGp6Rm/nnUweJ45CP8C6xc/X1Gbr016ra8RhmCSPfYj4jd49FimmQaagdIU5ZnjYwzgHzcVqBVMXrDp82iQhVCEplB0rFDa0xlZQIKfNfUqgE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772433185; c=relaxed/simple; bh=K+IEkb/8NvymAItniSffOTQbXkrUNTWTZNiqcK3erXU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=On1x0y6moi2ocdpM5e++sESJPcm89bKFlHEraySHcOHYuce6sXYsETUmatXUL8hVQkgISg0xRyR/kcZQ9CRBNBIOw1/SCJ+Izro7r08D3naaM7jVALBfxnllDetzGj19KoOj8/eC8EFjIjhkOPd7e3qS1XhIlTeFm0FLPgrgYuU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realsil.com.cn; spf=pass smtp.mailfrom=realsil.com.cn; dkim=pass (2048-bit key) header.d=realsil.com.cn header.i=@realsil.com.cn header.b=O75lwZEm; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realsil.com.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realsil.com.cn Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realsil.com.cn header.i=@realsil.com.cn header.b="O75lwZEm" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 6226WUKy82520768, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realsil.com.cn; s=dkim; t=1772433150; bh=g9fpf2D8wlRPpSgMTpbeW1qb5Lcbi6ymib/fUSLIje8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=O75lwZEmHBksySHGJkgByJO/tZNA5QDFCquPEQmjzXU0jshQXdi+bwRJ6WqRvOyU2 /iq02ooAOTLVs1mIN31/WxpGYUjEtQc2vvPojRx3vAtMeN+qeb0/krctTsWuyOOVuP Z9uhBwjozShsvRBmjyhol4/exGmECmipkOMJsxAgJN48Cyum/wXhJgQ27+zMLelmVp 9I7d6qhnzlWDENC4lJC5LcWbHzLr4t21R1dAqEzk6O9fV08l2gIpKt0nPqlUf+a+Fb afsYlfp+cQH+PnLTsY4gpndizW5sPt931vjPaN+mkZfIwDrPEB4aAlbRKnL4Kxup+m zZWq/a5JkpYtg== Received: from RS-EX-MBS2.realsil.com.cn ([172.29.17.102]) by rtits2.realtek.com.tw (8.15.2/3.21/5.94) with ESMTPS id 6226WUKy82520768 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 2 Mar 2026 14:32:30 +0800 Received: from RS-EX-MBS1.realsil.com.cn (172.29.17.101) by RS-EX-MBS2.realsil.com.cn (172.29.17.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.39; Mon, 2 Mar 2026 14:32:30 +0800 Received: from 172.29.37.154 (172.29.37.152) by RS-EX-MBS1.realsil.com.cn (172.29.17.101) with Microsoft SMTP Server id 15.2.1748.39 via Frontend Transport; Mon, 2 Mar 2026 14:32:30 +0800 From: javen To: , , , , , , , CC: , , Javen Xu Subject: [PATCH net-next v1 1/4] r8169: add ltr support for RTL8116af Date: Mon, 2 Mar 2026 14:32:11 +0800 Message-ID: <20260302063215.1790-2-javen_xu@realsil.com.cn> X-Mailer: git-send-email 2.50.1.windows.1 In-Reply-To: <20260302063215.1790-1-javen_xu@realsil.com.cn> References: <20260302063215.1790-1-javen_xu@realsil.com.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Javen Xu This patch adds ltr support for RTL8116af, enables RTL8116af enter l1.2 state. This makes sense for the system to enter c10 state. Signed-off-by: Javen Xu --- drivers/net/ethernet/realtek/r8169_main.c | 31 +++++++++++++++++++---- 1 file changed, 26 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethern= et/realtek/r8169_main.c index 58788d196c57..fb2247a20c36 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -330,11 +330,13 @@ enum rtl_registers { ALDPS_LTR =3D 0xe0a2, LTR_OBFF_LOCK =3D 0xe032, LTR_SNOOP =3D 0xe034, + SEND_LTR_MSG =3D 0xe038, =20 #define ALDPS_LTR_EN BIT(0) #define LTR_OBFF_LOCK_EN BIT(0) #define LINK_SPEED_CHANGE_EN BIT(14) #define LTR_SNOOP_EN GENMASK(15, 14) +#define LTR_MSG_EN BIT(0) }; =20 enum rtl8168_8101_registers { @@ -3093,8 +3095,22 @@ static void rtl_enable_ltr(struct rtl8169_private *t= p) r8168_mac_ocp_write(tp, 0xcdf2, 0x9003); r8168_mac_ocp_modify(tp, LTR_OBFF_LOCK, 0x0000, LINK_SPEED_CHANGE_EN); break; - case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: case RTL_GIGA_MAC_VER_52: + r8168_mac_ocp_write(tp, 0xcdd0, 0x9003); + r8168_mac_ocp_modify(tp, LTR_SNOOP, 0x0000, LTR_SNOOP_EN); + r8168_mac_ocp_write(tp, 0xe02c, 0x1880); + r8168_mac_ocp_write(tp, 0xe02e, 0x4880); + r8168_mac_ocp_modify(tp, ALDPS_LTR, 0x0000, ALDPS_LTR_EN); + r8168_mac_ocp_write(tp, 0xcdd8, 0x9003); + r8168_mac_ocp_write(tp, 0xcdda, 0x9003); + r8168_mac_ocp_write(tp, 0xcddc, 0x9003); + r8168_mac_ocp_write(tp, 0xcdd2, 0x883c); + r8168_mac_ocp_write(tp, 0xcdd4, 0x8c12); + r8168_mac_ocp_write(tp, 0xcdd6, 0x9003); + r8168_mac_ocp_write(tp, 0xe0a6, 0x9003); + r8168_mac_ocp_write(tp, 0xe0a8, 0x9003); + break; + case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: r8168_mac_ocp_modify(tp, ALDPS_LTR, 0x0000, ALDPS_LTR_EN); RTL_W8(tp, COMBO_LTR_EXTEND, RTL_R8(tp, COMBO_LTR_EXTEND) | COMBO_LTR_EX= TEND_EN); fallthrough; @@ -3114,6 +3130,7 @@ static void rtl_enable_ltr(struct rtl8169_private *tp) } /* chip can trigger LTR */ r8168_mac_ocp_modify(tp, LTR_OBFF_LOCK, 0x0003, LTR_OBFF_LOCK_EN); + r8168_mac_ocp_modify(tp, SEND_LTR_MSG, 0x0000, LTR_MSG_EN); } =20 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool ena= ble) @@ -3147,6 +3164,7 @@ static void rtl_hw_aspm_clkreq_enable(struct rtl8169_= private *tp, bool enable) rtl_enable_ltr(tp); switch (tp->mac_version) { case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: + case RTL_GIGA_MAC_VER_52: case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: /* reset ephy tx/rx disable timer */ r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); @@ -3159,6 +3177,7 @@ static void rtl_hw_aspm_clkreq_enable(struct rtl8169_= private *tp, bool enable) } else { switch (tp->mac_version) { case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: + case RTL_GIGA_MAC_VER_52: case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); break; @@ -3672,7 +3691,9 @@ static void rtl_hw_start_8117(struct rtl8169_private = *tp) =20 rtl_eri_set_bits(tp, 0xd4, 0x0010); =20 - rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); + rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4000); + + r8168_mac_ocp_write(tp, 0xe098, 0xc302); =20 rtl_disable_rxdvgate(tp); =20 @@ -3697,9 +3718,9 @@ static void rtl_hw_start_8117(struct rtl8169_private = *tp) } =20 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0000); - r8168_mac_ocp_write(tp, 0xea80, 0x0003); - r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); - r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); + r8168_mac_ocp_write(tp, 0xea80, 0x0000); + r8168_mac_ocp_modify(tp, 0xe052, 0x0009, 0x0000); + r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x045f); =20 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); r8168_mac_ocp_write(tp, 0xe63e, 0x0000); --=20 2.43.0 From nobody Thu Apr 16 06:52:57 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35FEB72618; Mon, 2 Mar 2026 06:33:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772433184; cv=none; b=NSVbzy0BcRoH4QGM2faDPWO7aQ1SpBvDTkO51FL6ii0RYOoL5dFg55PBlG3GkPO6GxdvJwVMkzFdjJZy/IW8j6Pgm0IQd8Uo4BndVqcCAyx3AazAvwqthjEcIHDWDMaDe6Ei/8De9nR6ynjBTh4w7eTpTo/eaT+A24o83v07+EA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772433184; c=relaxed/simple; bh=exDKFHuVoPT4I5x8qmQXSY6oH3arKMUls+dSQbROPzI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=C24NuSyM5/uXSuRrIsfsmzyIOXTSwbDcM2JxhylXR2592jk17Z/fuEl4saMI6YWm3zQM0FhBFTWqBlRuT2wlid4JtyrGCijPHKnup4r/ahym4jEYzudfX97b0yJk69xxE/mJOefTbKg8IdLGziXUd43OPr0aABbFJNLt0I8xses= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realsil.com.cn; spf=pass smtp.mailfrom=realsil.com.cn; dkim=pass (2048-bit key) header.d=realsil.com.cn header.i=@realsil.com.cn header.b=hBpNqnGc; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realsil.com.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realsil.com.cn Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realsil.com.cn header.i=@realsil.com.cn header.b="hBpNqnGc" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 6226WVjI42520770, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realsil.com.cn; s=dkim; t=1772433151; bh=cOwMm0LaDEQUXLcTV1g/RYCruMiXcWjqOtGMOxHa7DQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=hBpNqnGcLF1kgT7N9YR0jc4RZXmGmS9hcNqPadZVeSBfp994XG8z2pqNArUwHoZvC c8EYUiv+dqQA+nWuEpxQZ3VgQHhpO62PUQ9vsCpJ7kyUIXTlAE2+qO56SM+nxNwDf2 ALNdO+sUBjIYErQpWL+PAN/p4hShJiaxbcGXj6plaQxJ17+ldIfZPJWvWHM90AFEEK lhfIBEIt9Mhw+gb9tOq2xQA+lhWU5ALZrMAOI/ynxauiofR0qZ5Rg/CB99BYjuLF8V UmlhGmj7PIpBJwZAzStRjpv2OAdamwOff2WDgBhR3/Sg+X9QgCsoM2upuR4MEq80Lo Whu1XrsS3W6vQ== Received: from RS-EX-MBS2.realsil.com.cn ([172.29.17.102]) by rtits2.realtek.com.tw (8.15.2/3.21/5.94) with ESMTPS id 6226WVjI42520770 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 2 Mar 2026 14:32:31 +0800 Received: from RS-EX-MBS1.realsil.com.cn (172.29.17.101) by RS-EX-MBS2.realsil.com.cn (172.29.17.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.39; Mon, 2 Mar 2026 14:32:31 +0800 Received: from 172.29.37.154 (172.29.37.152) by RS-EX-MBS1.realsil.com.cn (172.29.17.101) with Microsoft SMTP Server id 15.2.1748.39 via Frontend Transport; Mon, 2 Mar 2026 14:32:31 +0800 From: javen To: , , , , , , , CC: , , Javen Xu Subject: [PATCH net-next v1 2/4] r8169: add sfp mode for RTL8116af Date: Mon, 2 Mar 2026 14:32:12 +0800 Message-ID: <20260302063215.1790-3-javen_xu@realsil.com.cn> X-Mailer: git-send-email 2.50.1.windows.1 In-Reply-To: <20260302063215.1790-1-javen_xu@realsil.com.cn> References: <20260302063215.1790-1-javen_xu@realsil.com.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Javen Xu RTL8116af is a variation of RTL8168fp. It uses SerDes instead of PHY. But SerDes status will not relect to PHY. So it needs to add sfp mode for quirk to help reflect SerDes status during PHY read. Signed-off-by: Javen Xu --- drivers/net/ethernet/realtek/r8169_main.c | 71 ++++++++++++++++++++--- 1 file changed, 62 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethern= et/realtek/r8169_main.c index fb2247a20c36..a5c0d3995328 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -726,6 +726,12 @@ enum rtl_dash_type { RTL_DASH_25_BP, }; =20 +enum rtl_sfp_mode { + RTL_SFP_NONE, + RTL_SFP_8168_AF, + RTL_SFP_8127_ATF, +}; + struct rtl8169_private { void __iomem *mmio_addr; /* memory map physical address */ struct pci_dev *pci_dev; @@ -734,6 +740,7 @@ struct rtl8169_private { struct napi_struct napi; enum mac_version mac_version; enum rtl_dash_type dash_type; + enum rtl_sfp_mode sfp_mode; u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ u32 dirty_tx; @@ -760,7 +767,6 @@ struct rtl8169_private { unsigned supports_gmii:1; unsigned aspm_manageable:1; unsigned dash_enabled:1; - bool sfp_mode:1; dma_addr_t counters_phys_addr; struct rtl8169_counters *counters; struct rtl8169_tc_offsets tc_offset; @@ -1126,7 +1132,7 @@ static int r8168_phy_ocp_read(struct rtl8169_private = *tp, u32 reg) return 0; =20 /* Return dummy MII_PHYSID2 in SFP mode to match SFP PHY driver */ - if (tp->sfp_mode && reg =3D=3D (OCP_STD_PHY_BASE + 2 * MII_PHYSID2)) + if (tp->sfp_mode =3D=3D RTL_SFP_8127_ATF && reg =3D=3D (OCP_STD_PHY_BASE = + 2 * MII_PHYSID2)) return PHY_ID_RTL_DUMMY_SFP & 0xffff; =20 RTL_W32(tp, GPHY_OCP, reg << 15); @@ -1270,6 +1276,34 @@ static int r8168g_mdio_read(struct rtl8169_private *= tp, int reg) return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); } =20 +/* The quirk reflects RTL8116af SerDes status. */ +static int r8116af_mdio_read_quirk(struct rtl8169_private *tp, int reg) +{ + u8 phyStatus =3D RTL_R8(tp, PHYstatus); + + if (!(phyStatus & LinkStatus)) + return 0; + + /* BMSR */ + if (tp->ocp_base =3D=3D OCP_STD_PHY_BASE && reg =3D=3D MII_BMSR) + return BMSR_ANEGCOMPLETE | BMSR_LSTATUS; + + /* PHYSR */ + if (tp->ocp_base =3D=3D 0xa430 && reg =3D=3D 0x12) { + if (phyStatus & _1000bpsF) + return 0x0028; + else if (phyStatus & _100bps) + return 0x0018; + } + + return 0; +} + +static int r8116af_mdio_read(struct rtl8169_private *tp, int reg) +{ + return r8168g_mdio_read(tp, reg) | r8116af_mdio_read_quirk(tp, reg); +} + static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) { if (reg =3D=3D 0x1f) { @@ -1280,6 +1314,13 @@ static void mac_mcu_write(struct rtl8169_private *tp= , int reg, int value) r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); } =20 +static bool rtl_is_8116af(struct rtl8169_private *tp) +{ + return tp->mac_version =3D=3D RTL_GIGA_MAC_VER_52 && + (r8168_mac_ocp_read(tp, 0xdc00) & 0x0078) =3D=3D 0x0030 && + (r8168_mac_ocp_read(tp, 0xd006) & 0x00ff) =3D=3D 0x0000; +} + static int mac_mcu_read(struct rtl8169_private *tp, int reg) { return r8168_mac_ocp_read(tp, tp->ocp_base + reg); @@ -1386,7 +1427,10 @@ static int rtl_readphy(struct rtl8169_private *tp, i= nt location) case RTL_GIGA_MAC_VER_31: return r8168dp_2_mdio_read(tp, location); case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: - return r8168g_mdio_read(tp, location); + if (tp->sfp_mode =3D=3D RTL_SFP_8168_AF) + return r8116af_mdio_read(tp, location); + else + return r8168g_mdio_read(tp, location); default: return r8169_mdio_read(tp, location); } @@ -1575,6 +1619,20 @@ static bool rtl_dash_is_enabled(struct rtl8169_priva= te *tp) } } =20 +static enum rtl_sfp_mode rtl_get_sfp_mode(struct rtl8169_private *tp) +{ + if (rtl_is_8125(tp)) { + u16 data =3D r8168_mac_ocp_read(tp, 0xd006); + + if ((data & 0xff) =3D=3D 0x07) + return RTL_SFP_8127_ATF; + } else if (rtl_is_8116af(tp)) { + return RTL_SFP_8168_AF; + } + + return RTL_SFP_NONE; +} + static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp) { switch (tp->mac_version) { @@ -5693,12 +5751,7 @@ static int rtl_init_one(struct pci_dev *pdev, const = struct pci_device_id *ent) } tp->aspm_manageable =3D !rc; =20 - if (rtl_is_8125(tp)) { - u16 data =3D r8168_mac_ocp_read(tp, 0xd006); - - if ((data & 0xff) =3D=3D 0x07) - tp->sfp_mode =3D true; - } + tp->sfp_mode =3D rtl_get_sfp_mode(tp); =20 tp->dash_type =3D rtl_get_dash_type(tp); tp->dash_enabled =3D rtl_dash_is_enabled(tp); --=20 2.43.0 From nobody Thu Apr 16 06:52:57 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C64C430BAC; Mon, 2 Mar 2026 06:33:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772433184; cv=none; b=i6XX0wAYmmhbLOWdAnw2XwfHTx3I411tm1vd/JAD+kweCgu0VJHVAAlp7OugGDdkWXCyHXWwiNjN7h5WYrUzI2GkfS5Mhq84w7KATvwPOqP9JI6eKF1y37NzJzlNcxjDKmSsded3fF7X3lWZL21asXSQ6bpv73aYdXnEzLKbHWE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772433184; c=relaxed/simple; bh=QY/yBHcbyE+BX8N8npu0WQnoaNx6ROcCqLwZsh7C5vI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=OswNlDz6pWKLFt1RLgCopyguVEzCyswIl1tvZ5vi23M/rRoj8C236WBZs4f758xKhBAuhLJYkTPKG/fTiltz+QmbSIyohh0lzostz+4Fu/s/W1gRoA9+uGa36+pm0k4yhcCIADSAHsjpxPCfgrdI1Ir3GxA3XWUEMkpGN+jYqtM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realsil.com.cn; spf=pass smtp.mailfrom=realsil.com.cn; dkim=pass (2048-bit key) header.d=realsil.com.cn header.i=@realsil.com.cn header.b=w5pFi7YW; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realsil.com.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realsil.com.cn Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realsil.com.cn header.i=@realsil.com.cn header.b="w5pFi7YW" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 6226WWvpC2520774, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realsil.com.cn; s=dkim; t=1772433152; bh=b7+Sppr22ISpwXZ1gUoe2uKBFl3jh9IbKdbre7frfKQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=w5pFi7YWMEG/YXtocKws8UxXYbL04LOdX/zjE/jW+9bBEAJvRD5/d+fYfDdro/fB4 WILMJHBV1kz9FuJ9FnAX5CQDTU5cv6hG+xeMokWdpqoXXDW3YR4vm8fi3K5k1cR9/j a7OwsiNye4FOPm3FuFBryM/CkHZA8LobxAA5cR7TYiaLEOx8FPBn/XCqtXzaicdxVA b5URa5nnAN3WmfwSB+4TU8imNuMJvBZQQi4T8mORP3B4wKoA6Wpn0ktQpJsxCFIFt7 aAorRk3NOUBsAXWweFSPchz2lBMYr5sDf5TAE8MDbe0CgEWJtkQC3ztIQbbWqpVzKe MMSuyINu4HGJw== Received: from RS-EX-MBS4.realsil.com.cn ([172.29.17.104]) by rtits2.realtek.com.tw (8.15.2/3.21/5.94) with ESMTPS id 6226WWvpC2520774 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 2 Mar 2026 14:32:32 +0800 Received: from RS-EX-MBS1.realsil.com.cn (172.29.17.101) by RS-EX-MBS4.realsil.com.cn (172.29.17.104) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.39; Mon, 2 Mar 2026 14:32:32 +0800 Received: from 172.29.37.154 (172.29.37.152) by RS-EX-MBS1.realsil.com.cn (172.29.17.101) with Microsoft SMTP Server id 15.2.1748.39 via Frontend Transport; Mon, 2 Mar 2026 14:32:32 +0800 From: javen To: , , , , , , , CC: , , Javen Xu Subject: [PATCH net-next v1 3/4] r8169: move DECLARE_RTL_COND() Date: Mon, 2 Mar 2026 14:32:13 +0800 Message-ID: <20260302063215.1790-4-javen_xu@realsil.com.cn> X-Mailer: git-send-email 2.50.1.windows.1 In-Reply-To: <20260302063215.1790-1-javen_xu@realsil.com.cn> References: <20260302063215.1790-1-javen_xu@realsil.com.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Javen Xu There is no functional change. Moving DECLARE_RTL_COND() for the next patch 4/4. Signed-off-by: Javen Xu --- drivers/net/ethernet/realtek/r8169_main.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethern= et/realtek/r8169_main.c index a5c0d3995328..787859b0ab68 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -1052,6 +1052,11 @@ DECLARE_RTL_COND(rtl_eriar_cond) return RTL_R32(tp, ERIAR) & ERIAR_FLAG; } =20 +DECLARE_RTL_COND(rtl_csiar_cond) +{ + return RTL_R32(tp, CSIAR) & CSIAR_FLAG; +} + static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, u32 val, int type) { @@ -2927,11 +2932,6 @@ static void rtl_set_rx_mode(struct net_device *dev) RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); } =20 -DECLARE_RTL_COND(rtl_csiar_cond) -{ - return RTL_R32(tp, CSIAR) & CSIAR_FLAG; -} - static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) { u32 func =3D PCI_FUNC(tp->pci_dev->devfn); --=20 2.43.0 From nobody Thu Apr 16 06:52:57 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35F98430BBA; Mon, 2 Mar 2026 06:33:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772433184; cv=none; b=BqS9Y6puJJi3sNtr9NoJfTfBQdptX10pl0f6nmIkTRIWapkZ9V/e8bTx2PSvtpqQGDJ9J3v+LFV2LhMhFn+FDcyc1CJO1vRtDD05dMwLbwTfsYLkiVlglkdKB7x57HtxJVWVKFogcjFotmI+A9HND0hVVzl/5Of2GHz6Sk8E1Gg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772433184; c=relaxed/simple; bh=AmiDiX3u2FvFSV1ewjNpDCbkSNCwqJ/S6aRddquk3Ak=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QwCnf6hdHrss+17u59TdT1364pSlv8YPZDr3Tn8PIbOAWc71CNERI4o7Yu+ZoESOeYTVGmtanz3MmBGRu5r1/pY2W9lkRKjdBCpgnpDI/Z+oc5foAm47RZVrICXs9jIBaZaYx56rPPO8D1teNXqv8Mme3G+Ea3lxWxhSUdYR01s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realsil.com.cn; spf=pass smtp.mailfrom=realsil.com.cn; dkim=pass (2048-bit key) header.d=realsil.com.cn header.i=@realsil.com.cn header.b=TXMPF4JV; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realsil.com.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realsil.com.cn Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realsil.com.cn header.i=@realsil.com.cn header.b="TXMPF4JV" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 6226WXHc82520776, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realsil.com.cn; s=dkim; t=1772433154; bh=YcvsglXAjNM65+Z3dMzq1amg2E3Wn5iUDNgM8l581C8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=TXMPF4JVRiyQDl0X+J0zbKvH7wmhI/AyLmpjU+ubPfds5GyNx+wccSKg5fGN+Y+Z8 WDHSOI20cFxIHxF8Be8ln5Qo4eZ0oufdchgL0p9X70wPTYFR4FqZFkQwwxut1zSAK7 r6k2OR1sJUbIbcT4zTV6DcTLpdU6fVaBF+4apnfr/9oSDNDM96H/kTaW+3qTb/q+6n K8PehJkBn4tSSYCVX4PvlbNawZjmvZX39O+RrcQDZCJ0gnX8r3p9D3GhceOeDrJ2/D CmsGnsD0L7hF/9T5wX8sbWmISTkv9v+tEuoONBNjkM3gH3Fo+DiZSOtxH8kjbqa6vF 7VRw6m+Seg6gA== Received: from RS-EX-MBS1.realsil.com.cn ([172.29.17.101]) by rtits2.realtek.com.tw (8.15.2/3.21/5.94) with ESMTPS id 6226WXHc82520776 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 2 Mar 2026 14:32:33 +0800 Received: from RS-EX-MBS1.realsil.com.cn (172.29.17.101) by RS-EX-MBS1.realsil.com.cn (172.29.17.101) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.39; Mon, 2 Mar 2026 14:32:33 +0800 Received: from 172.29.37.154 (172.29.37.152) by RS-EX-MBS1.realsil.com.cn (172.29.17.101) with Microsoft SMTP Server id 15.2.1748.39 via Frontend Transport; Mon, 2 Mar 2026 14:32:33 +0800 From: javen To: , , , , , , , CC: , , Javen Xu Subject: [PATCH net-next v1 4/4] r8169: enable system enter c10 with RTL8116af Date: Mon, 2 Mar 2026 14:32:14 +0800 Message-ID: <20260302063215.1790-5-javen_xu@realsil.com.cn> X-Mailer: git-send-email 2.50.1.windows.1 In-Reply-To: <20260302063215.1790-1-javen_xu@realsil.com.cn> References: <20260302063215.1790-1-javen_xu@realsil.com.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Javen Xu RTL8116af is a multi function chip. Function 1 is load with r8169 driver. Function 0 is bmc virual driver which is used for power management. This patch set Function 2 to 7 into d3 state when config hw_config. This helps the whole system enter c10. Signed-off-by: Javen Xu --- drivers/net/ethernet/realtek/r8169_main.c | 95 +++++++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethern= et/realtek/r8169_main.c index 787859b0ab68..d8ffc76186b2 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -1121,6 +1121,100 @@ DECLARE_RTL_COND(rtl_ocp_gphy_cond) return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; } =20 +static u32 rtl_other_csi_read(struct rtl8169_private *tp, u8 multi_fun_sel= _bit, int addr) +{ + RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | multi_fun_sel_bit << 16 | + CSIAR_BYTE_ENABLE); + + return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? + RTL_R32(tp, CSIDR) : ~0; +} + +static void rtl_other_csi_write(struct rtl8169_private *tp, + u8 multi_fun_sel_bit, + int addr, + int value) +{ + RTL_W32(tp, CSIDR, value); + RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | + CSIAR_BYTE_ENABLE | multi_fun_sel_bit << 16); + + rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); +} + +static void rtl8168_clear_and_set_other_fun_pci_bit(struct rtl8169_private= *tp, + u8 multi_fun_sel_bit, + u32 addr, + u32 clearmask, + u32 setmask) +{ + u32 val; + + val =3D rtl_other_csi_read(tp, multi_fun_sel_bit, addr); + val &=3D ~clearmask; + val |=3D setmask; + rtl_other_csi_write(tp, multi_fun_sel_bit, addr, val); +} + +static void rtl8168_other_fun_dev_pci_setting(struct rtl8169_private *tp, + u32 addr, + u32 clearmask, + u32 setmask, + u8 multi_fun_sel_bit) +{ + u32 val; + u8 i; + u8 FunBit; + /* 0: BMC, 1: NIC, 2: TCR, 3: VGA/PCIE_TO_USB, 4: EHCI, 5: WIFI, 6: WIFI,= 7: KCS */ + for (i =3D 0; i < 8; i++) { + FunBit =3D (1 << i); + if (FunBit & multi_fun_sel_bit) { + u8 set_other_fun =3D true; + + if (i =3D=3D 0) { + set_other_fun =3D true; + } else if (i =3D=3D 5 || i =3D=3D 6) { + if (tp->dash_enabled) { + val =3D rtl_eri_read(tp, 0x184); + if (val & BIT(26)) + set_other_fun =3D false; + else + set_other_fun =3D true; + } + } else { + val =3D rtl_other_csi_read(tp, i, 0x00); + if (val =3D=3D 0xffffffff) + set_other_fun =3D true; + else + set_other_fun =3D false; + } + if (set_other_fun) + rtl8168_clear_and_set_other_fun_pci_bit(tp, i, addr, + clearmask, setmask); + } + } +} + +static void rtl8168_set_dash_other_fun_dev_state_change(struct rtl8169_pri= vate *tp, + u8 dev_state, + u8 multi_fun_sel_bit) +{ + u32 clearmask; + u32 setmask; + + if (dev_state =3D=3D 0) { + clearmask =3D (BIT(0) | BIT(1)); + setmask =3D 0; + rtl8168_other_fun_dev_pci_setting(tp, 0x44, clearmask, + setmask, multi_fun_sel_bit); + } else { + clearmask =3D 0; + setmask =3D (BIT(0) | BIT(1)); + rtl8168_other_fun_dev_pci_setting(tp, 0x44, clearmask, + setmask, multi_fun_sel_bit); + } +} + static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 d= ata) { if (rtl_ocp_reg_failure(reg)) @@ -3785,6 +3879,7 @@ static void rtl_hw_start_8117(struct rtl8169_private = *tp) r8168_mac_ocp_write(tp, 0xc094, 0x0000); r8168_mac_ocp_write(tp, 0xc09e, 0x0000); =20 + rtl8168_set_dash_other_fun_dev_state_change(tp, 3, 0xfc); /* firmware is for MAC only */ r8169_apply_firmware(tp); } --=20 2.43.0