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Miller" , Udit Tiwari , Daniel Perez-Zoghbi , Md Sadre Alam , Dmitry Baryshkov , Peter Ujfalusi , Michal Simek , Frank Li Cc: dmaengine@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, linux-arm-kernel@lists.infradead.org, brgl@kernel.org, Bartosz Golaszewski , Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10084; i=bartosz.golaszewski@oss.qualcomm.com; h=from:subject:message-id; bh=xVyXRxFp3hoaIPdmV5W3HruIHEbBK3c+oEfKaj3P3iI=; b=owEBbQKS/ZANAwAKAQWdLsv/NoTDAcsmYgBppbNp3uL1qF09VByovmCxr0BrPF2qt0vumz3w9 4VDWOB+XZGJAjMEAAEKAB0WIQSR5RMt5bVGHXuiZfwFnS7L/zaEwwUCaaWzaQAKCRAFnS7L/zaE w3QWEACVBpmfAzAr7VheSYyio4m2cLxyZN0JpZvXOWcCmYcyKruO1ubprk1VjaXrtxmnqPkJFOA 8Z2G2q0RWqM3m4FtgyR2cXgBh3H8mWh1N7HNbYfe4DXsL2HBwznabEZPjB5lcQNISfLls/a0paU Z5yygOOtjS2O75Z0Y3xqbKacBqbxCkRd5vlQSV9hdQlebDClRP5wZT32tytJzGrXUMK7dtd/eqh lHTjxyF9KIAWBLKBa7PPTFW9XMRdnU/BGS3hwN9G77cZ7vh0TIFV6LbwMpUaIIA3aHaltAO2TSp ufaNp4It7NI71cUM7S3bZgLYHnUvqKUBjNkiLCaeykIbiJflZ8IIACcnZ2xVRdVHo2Jv9sgB3kb UnsqQTh2RC3Pb1/RmrwaJegHk/XCTVNVoVm+zVkbsWCd4IWJx/MZ3M+uh95STXoNAPaCX0eoysP IhMrn8HlnXNt5MtoBfwCHpiwbrfmioXT/6pCCPdcu06zPkCcz2xl1ytMoQJZrJ9Zk8FGEevT6r/ TX1mw84tUvo+l/0Iy+Zx3oCzB/k5mPIfR+Eo88IZ0svKagnxXDauKwFSabFLc+jKx1UCBo+QKNP p7qCAu6MWoIZykAmINl/yY6tYNJzo3aUXg/mO5EVEwsIne9FhKDH3RryvT7/Xbd30U41QLqIXwm yOcuYuvxgovT7pA== X-Developer-Key: i=bartosz.golaszewski@oss.qualcomm.com; a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 X-Proofpoint-GUID: QVfcWqFLvw0cvZ4xG1sVsy8hAxaVvcG0 X-Authority-Analysis: v=2.4 cv=S83UAYsP c=1 sm=1 tr=0 ts=69a5b37d cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=koLDk85rXkRIAoTU0vQA:9 a=QEXdDO2ut3YA:10 a=iYH6xdkBrDN1Jqds4HTS:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: QVfcWqFLvw0cvZ4xG1sVsy8hAxaVvcG0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzAyMDEzMyBTYWx0ZWRfXxtO/G+OuW0G2 XvEVBw+BlAQS0oH86h4E3H1t46co15q+UoDjT3pXiREBjX/pCVve6loiQDorbPCjO+MeifGRQAA zTAx8uYWdFpcFCIijrOTC5n2Wp0PSyW7qrZ20fTaaxjgiiPzmPBdPe36nQ1xrHcu2+tjR1GAylG ULJ3fe6IQk2gUT8yYugomAB6Z+Q4RfmBiJI2bLxCt8yr89Lvth2/ZG1/yWqjBFZEFikILBuzhaG E78Ar0psQGIqDrjTKhbYrCzUeBiLeYyXUyT0jvRh9NmBXB7qzdIogNn7F3eM2oDjH70JmY9bBSs je+UxZNpBu0edcd5EG3Ds1oKYLgjS1Bes1hk4HD2s+S6To04KKP29pM+eBzqrvXabx88ebT8/bn XoWSx88wKlwn10fx0Rm1z4SmWYW4qGRtihCUWRA7huKrVOsOMQbt6fJg1ONtwd08wgfECoop69D TDrT7GjGSeu6u9t06Dg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-02_03,2026-03-02_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 adultscore=0 phishscore=0 spamscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603020133 From: Bartosz Golaszewski Implement the infrastructure for performing register I/O over BAM DMA, not CPU. Signed-off-by: Bartosz Golaszewski Signed-off-by: Bartosz Golaszewski --- drivers/crypto/qce/aead.c | 2 - drivers/crypto/qce/common.c | 20 ++++---- drivers/crypto/qce/core.h | 4 ++ drivers/crypto/qce/dma.c | 109 ++++++++++++++++++++++++++++++++++++++= ++++ drivers/crypto/qce/dma.h | 5 ++ drivers/crypto/qce/sha.c | 2 - drivers/crypto/qce/skcipher.c | 2 - 7 files changed, 127 insertions(+), 17 deletions(-) diff --git a/drivers/crypto/qce/aead.c b/drivers/crypto/qce/aead.c index abb438d2f8888d313d134161fda97dcc9d82d6d9..a4e8158803eb59cd0d40076674d= 0059bb94759ce 100644 --- a/drivers/crypto/qce/aead.c +++ b/drivers/crypto/qce/aead.c @@ -473,8 +473,6 @@ qce_aead_async_req_handle(struct crypto_async_request *= async_req) if (ret) goto error_unmap_src; =20 - qce_dma_issue_pending(&qce->dma); - ret =3D qce_start(async_req, tmpl->crypto_alg_type); if (ret) goto error_terminate; diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c index 04253a8d33409a2a51db527435d09ae85a7880af..b2b0e751a06517ac06e7a468599= bd18666210e0c 100644 --- a/drivers/crypto/qce/common.c +++ b/drivers/crypto/qce/common.c @@ -25,7 +25,7 @@ static inline u32 qce_read(struct qce_device *qce, u32 of= fset) =20 static inline void qce_write(struct qce_device *qce, u32 offset, u32 val) { - writel(val, qce->base + offset); + qce_write_dma(qce, offset, val); } =20 static inline void qce_write_array(struct qce_device *qce, u32 offset, @@ -82,6 +82,8 @@ static void qce_setup_config(struct qce_device *qce) { u32 config; =20 + qce_clear_bam_transaction(qce); + /* get big endianness */ config =3D qce_config_reg(qce, 0); =20 @@ -90,12 +92,14 @@ static void qce_setup_config(struct qce_device *qce) qce_write(qce, REG_CONFIG, config); } =20 -static inline void qce_crypto_go(struct qce_device *qce, bool result_dump) +static inline int qce_crypto_go(struct qce_device *qce, bool result_dump) { if (result_dump) qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT)); else qce_write(qce, REG_GOPROC, BIT(GO_SHIFT)); + + return qce_submit_cmd_desc(qce); } =20 #if defined(CONFIG_CRYPTO_DEV_QCE_SHA) || defined(CONFIG_CRYPTO_DEV_QCE_AE= AD) @@ -223,9 +227,7 @@ static int qce_setup_regs_ahash(struct crypto_async_req= uest *async_req) config =3D qce_config_reg(qce, 1); qce_write(qce, REG_CONFIG, config); =20 - qce_crypto_go(qce, true); - - return 0; + return qce_crypto_go(qce, true); } #endif =20 @@ -386,9 +388,7 @@ static int qce_setup_regs_skcipher(struct crypto_async_= request *async_req) config =3D qce_config_reg(qce, 1); qce_write(qce, REG_CONFIG, config); =20 - qce_crypto_go(qce, true); - - return 0; + return qce_crypto_go(qce, true); } #endif =20 @@ -535,9 +535,7 @@ static int qce_setup_regs_aead(struct crypto_async_requ= est *async_req) qce_write(qce, REG_CONFIG, config); =20 /* Start the process */ - qce_crypto_go(qce, !IS_CCM(flags)); - - return 0; + return qce_crypto_go(qce, !IS_CCM(flags)); } #endif =20 diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h index a80e12eac6c87e5321cce16c56a4bf5003474ef0..d238097f834e4605f3825f23d03= 16d4196439116 100644 --- a/drivers/crypto/qce/core.h +++ b/drivers/crypto/qce/core.h @@ -30,6 +30,8 @@ * @base_dma: base DMA address * @base_phys: base physical address * @dma_size: size of memory mapped for DMA + * @read_buf: Buffer for DMA to write back to + * @read_buf_dma: Mapped address of the read buffer * @async_req_enqueue: invoked by every algorithm to enqueue a request * @async_req_done: invoked by every algorithm to finish its request */ @@ -49,6 +51,8 @@ struct qce_device { dma_addr_t base_dma; phys_addr_t base_phys; size_t dma_size; + __le32 *read_buf; + dma_addr_t read_buf_dma; int (*async_req_enqueue)(struct qce_device *qce, struct crypto_async_request *req); void (*async_req_done)(struct qce_device *qce, int ret); diff --git a/drivers/crypto/qce/dma.c b/drivers/crypto/qce/dma.c index a46264735bb895b6199969e83391383ccbbacc5f..ba7a52fd4c6349d59c075c346f7= 5741defeb6034 100644 --- a/drivers/crypto/qce/dma.c +++ b/drivers/crypto/qce/dma.c @@ -4,6 +4,8 @@ */ =20 #include +#include +#include #include #include =20 @@ -11,6 +13,98 @@ #include "dma.h" =20 #define QCE_IGNORE_BUF_SZ (2 * QCE_BAM_BURST_SIZE) +#define QCE_BAM_CMD_SGL_SIZE 128 +#define QCE_BAM_CMD_ELEMENT_SIZE 128 +#define QCE_MAX_REG_READ 8 + +struct qce_desc_info { + struct dma_async_tx_descriptor *dma_desc; + enum dma_data_direction dir; +}; + +struct qce_bam_transaction { + struct bam_cmd_element bam_ce[QCE_BAM_CMD_ELEMENT_SIZE]; + struct scatterlist wr_sgl[QCE_BAM_CMD_SGL_SIZE]; + struct qce_desc_info *desc; + u32 bam_ce_idx; + u32 pre_bam_ce_idx; + u32 wr_sgl_cnt; +}; + +void qce_clear_bam_transaction(struct qce_device *qce) +{ + struct qce_bam_transaction *bam_txn =3D qce->dma.bam_txn; + + bam_txn->bam_ce_idx =3D 0; + bam_txn->wr_sgl_cnt =3D 0; + bam_txn->bam_ce_idx =3D 0; + bam_txn->pre_bam_ce_idx =3D 0; +} + +int qce_submit_cmd_desc(struct qce_device *qce) +{ + struct qce_desc_info *qce_desc =3D qce->dma.bam_txn->desc; + struct qce_bam_transaction *bam_txn =3D qce->dma.bam_txn; + struct dma_async_tx_descriptor *dma_desc; + struct dma_chan *chan =3D qce->dma.rxchan; + unsigned long attrs =3D DMA_PREP_CMD; + dma_cookie_t cookie; + unsigned int mapped; + int ret; + + mapped =3D dma_map_sg_attrs(qce->dev, bam_txn->wr_sgl, bam_txn->wr_sgl_cn= t, + DMA_TO_DEVICE, attrs); + if (!mapped) + return -ENOMEM; + + dma_desc =3D dmaengine_prep_slave_sg(chan, bam_txn->wr_sgl, bam_txn->wr_s= gl_cnt, + DMA_MEM_TO_DEV, attrs); + if (!dma_desc) { + dma_unmap_sg(qce->dev, bam_txn->wr_sgl, bam_txn->wr_sgl_cnt, DMA_TO_DEVI= CE); + return -ENOMEM; + } + + qce_desc->dma_desc =3D dma_desc; + cookie =3D dmaengine_submit(qce_desc->dma_desc); + + ret =3D dma_submit_error(cookie); + if (ret) + return ret; + + qce_dma_issue_pending(&qce->dma); + + return 0; +} + +static void qce_prep_dma_cmd_desc(struct qce_device *qce, struct qce_dma_d= ata *dma, + unsigned int addr, void *buf) +{ + struct qce_bam_transaction *bam_txn =3D dma->bam_txn; + struct bam_cmd_element *bam_ce_buf; + int bam_ce_size, cnt, idx; + + idx =3D bam_txn->bam_ce_idx; + bam_ce_buf =3D &bam_txn->bam_ce[idx]; + bam_prep_ce_le32(bam_ce_buf, addr, BAM_WRITE_COMMAND, *((__le32 *)buf)); + + bam_ce_buf =3D &bam_txn->bam_ce[bam_txn->pre_bam_ce_idx]; + bam_txn->bam_ce_idx++; + bam_ce_size =3D (bam_txn->bam_ce_idx - bam_txn->pre_bam_ce_idx) * sizeof(= *bam_ce_buf); + + cnt =3D bam_txn->wr_sgl_cnt; + + sg_set_buf(&bam_txn->wr_sgl[cnt], bam_ce_buf, bam_ce_size); + + ++bam_txn->wr_sgl_cnt; + bam_txn->pre_bam_ce_idx =3D bam_txn->bam_ce_idx; +} + +void qce_write_dma(struct qce_device *qce, unsigned int offset, u32 val) +{ + unsigned int reg_addr =3D ((unsigned int)(qce->base_phys) + offset); + + qce_prep_dma_cmd_desc(qce, &qce->dma, reg_addr, &val); +} =20 int devm_qce_dma_request(struct qce_device *qce) { @@ -31,6 +125,21 @@ int devm_qce_dma_request(struct qce_device *qce) if (!dma->result_buf) return -ENOMEM; =20 + dma->bam_txn =3D devm_kzalloc(dev, sizeof(*dma->bam_txn), GFP_KERNEL); + if (!dma->bam_txn) + return -ENOMEM; + + dma->bam_txn->desc =3D devm_kzalloc(dev, sizeof(*dma->bam_txn->desc), GFP= _KERNEL); + if (!dma->bam_txn->desc) + return -ENOMEM; + + sg_init_table(dma->bam_txn->wr_sgl, QCE_BAM_CMD_SGL_SIZE); + + qce->read_buf =3D dmam_alloc_coherent(qce->dev, QCE_MAX_REG_READ * sizeof= (*qce->read_buf), + &qce->read_buf_dma, GFP_KERNEL); + if (!qce->read_buf) + return -ENOMEM; + return 0; } =20 diff --git a/drivers/crypto/qce/dma.h b/drivers/crypto/qce/dma.h index 483789d9fa98e79d1283de8297bf2fc2a773f3a7..f05dfa9e6b25bd60e32f45079a8= bc7e6a4cf81f9 100644 --- a/drivers/crypto/qce/dma.h +++ b/drivers/crypto/qce/dma.h @@ -8,6 +8,7 @@ =20 #include =20 +struct qce_bam_transaction; struct qce_device; =20 /* maximum data transfer block size between BAM and CE */ @@ -32,6 +33,7 @@ struct qce_dma_data { struct dma_chan *txchan; struct dma_chan *rxchan; struct qce_result_dump *result_buf; + struct qce_bam_transaction *bam_txn; }; =20 int devm_qce_dma_request(struct qce_device *qce); @@ -43,5 +45,8 @@ int qce_dma_terminate_all(struct qce_dma_data *dma); struct scatterlist * qce_sgtable_add(struct sg_table *sgt, struct scatterlist *sg_add, unsigned int max_len); +void qce_write_dma(struct qce_device *qce, unsigned int offset, u32 val); +int qce_submit_cmd_desc(struct qce_device *qce); +void qce_clear_bam_transaction(struct qce_device *qce); =20 #endif /* _DMA_H_ */ diff --git a/drivers/crypto/qce/sha.c b/drivers/crypto/qce/sha.c index d7b6d042fb44f4856a6b4f9c901376dd7531454d..9552a74bf191def412fc32f3859= 356e569e5d400 100644 --- a/drivers/crypto/qce/sha.c +++ b/drivers/crypto/qce/sha.c @@ -113,8 +113,6 @@ static int qce_ahash_async_req_handle(struct crypto_asy= nc_request *async_req) if (ret) goto error_unmap_dst; =20 - qce_dma_issue_pending(&qce->dma); - ret =3D qce_start(async_req, tmpl->crypto_alg_type); if (ret) goto error_terminate; diff --git a/drivers/crypto/qce/skcipher.c b/drivers/crypto/qce/skcipher.c index 872b65318233ed21e3559853f6bbdad030a1b81f..e80452c19b03496faaee38d4ac7= 92289f560d082 100644 --- a/drivers/crypto/qce/skcipher.c +++ b/drivers/crypto/qce/skcipher.c @@ -147,8 +147,6 @@ qce_skcipher_async_req_handle(struct crypto_async_reque= st *async_req) if (ret) goto error_unmap_src; =20 - qce_dma_issue_pending(&qce->dma); - ret =3D qce_start(async_req, tmpl->crypto_alg_type); if (ret) goto error_terminate; --=20 2.47.3