From nobody Thu Apr 9 15:00:55 2026 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05BFE41B360 for ; Mon, 2 Mar 2026 15:13:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772464444; cv=none; b=eUhueEDD1h3BQH2s5EoTYMz5NEOqzeTxgQNSsqd4/UJcxaYMaNnLjARhJHe4ZjRQabQOU+BuDKmDLeirZbqFukFK8SMSPZhNRGZXOqa89awcLmaos2b5cDyQsMAAEezieFGnNRxowxu3+0ldrNogAucwbLV665fNMSEXSfj5Lfo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772464444; c=relaxed/simple; bh=oROrpMpGRFTyu9YVgnx3q3a5mnQL/8tXkXG+ZsNoOvM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VXbA9RVvFKHYQRLpuf7xTbqor7CUjZf/egTrM58YBjfGvYuQicLrda+lu/DQaV5p3NGQ0agIKwxSYAIFHcNYb6AYjlY9BluwB0hnWPcf7Hyn0rBJdq2m27w2DUxU8s49Ixi89v5MT2ivRQ/5hYwEAKB6ODhNerGwhqb+CZZcQ6s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=l+rEQAO/; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="l+rEQAO/" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-48379a42f76so37621925e9.0 for ; Mon, 02 Mar 2026 07:13:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1772464437; x=1773069237; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=1vMnihDprCpz00E0mqvOLaz+xzD900tygzUTesRDljg=; b=l+rEQAO/ZtZ5a3ll0kTsA+nD+oMAJfL2okPyrhhRV6LTCS/e/TYb4o9MTORAW0BXpw MeHb0aVXUrMwouA2f9riftkYIhrw3T/fJRqqf6WFgdRRrdcPbGwYHMKHy7sSbaKmmsPQ Yj4I5m9RGEqhQvVATuKo3ay5iNppbT3KKIls78bEu7IcCoBIZzFICVWYyEPfDs8d5U7L aW64vNu2iZyFuyE+/YgeUODWQ5qCo9cEy4/s47D9TnSkau7ccbtmChvEVw/lGz8c6WmP cMJDiFCtEqhWoe+sRa5fKd3rXM9/c5dH2w4VJMr2HY9UVS0wyKQZblPitgA8xK4cjQ1J BIRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772464437; x=1773069237; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=1vMnihDprCpz00E0mqvOLaz+xzD900tygzUTesRDljg=; b=hnRsuSDQ9AOQjy/mAXIKlUUravf27LJRwLTN9yCxYEYhNqyejLfDxQ12m3lyedenSQ RbzkeVzFmjciRHdbes0nkW7bflvcSIwJWGhuMi7flvKFoMbvIm7yiiB6DDPA8CVYjrqy KlZSvaVKmaMYMUoWkaKiJNzfD3Y8AW+FshrmRLg7BHpsjte9i1WXktifUg8qb5VQ4sWA SSFhpuutg5fb2AXbvtWwi79uZq8BiU22U5UyMiEDYVU10h2nZm9L0d0+tkThcjdSiq7U V0OltqCihuCbWaeBCZK4FdDkq4wtQ9XOdus0i53zpThffhlObwrRn4k/pgD2pc+t0lBo X/zw== X-Forwarded-Encrypted: i=1; AJvYcCVmz4lT1bDkUoeg5a1SAoWuzSRxaLzPjegKFkWC0O2JlohI2WmfOiCSAiaXUP4fpNAm0P7gF1Gol+7u9Ac=@vger.kernel.org X-Gm-Message-State: AOJu0Yy9tiSE/T7OAPjDuh0Th7EbVtF18oJfIi/PYSqneFXqam15epPT cm6H/fpVKG/XenH+MmKe9zI0qkS5Ah4xPhMCjWUN8GLi/pegzsz7DqKZ X-Gm-Gg: ATEYQzxZtq9A5h3p8fQL01Y8eNrLPaiyj01ozwUSOHFgCCMRQr3Fd0I9MZfb1FnIypE /ipirnIwUgO7QfSRkUqKBdMoDDPNCCkUxtG0KV7jbORjDKQxuFy4CJOMFjPN8zgeIHixvl1f3U6 ljLPWRlV5s9gEZ4sxYzb2w0TlPAuZdknfcDKdONfrXzz4X7hG2xBGB6o80x+5fuXFjBwbV0vJbS kwvSeJ1s7FDUgMAPoVOMrXH9+tPUHnEckIg1Ee7ca3ACRnmvHNyJhI2JO8WFfZxPAiV5rjrSQVl LYHiq9gMYeIagCxvBJYT2glS5P1k3L4BAI3S4XGTiKQEDGRRS2qq+LUVpaS996gNaQZj65Igsc/ mVhNAuq3m4hQq6Q9GjIm/UBj37NPRYsZBNTzHXmVviW+x54uY9B5uT1aXEawxOW34FM4dpKyVlB fkHFlL/1FzeKF29JmYOFtMCaDKwe32lRBM6ub/k1BikPqFJq2cGJpuMJT2pVgsbp4Xbw== X-Received: by 2002:a05:600c:c16e:b0:482:e5d4:b7ca with SMTP id 5b1f17b1804b1-483c9bbb8d3mr200785895e9.8.1772464437211; Mon, 02 Mar 2026 07:13:57 -0800 (PST) Received: from ipedrosa-thinkpadx1carbongen12.rmtes.csb ([67.218.235.131]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483bd70e692sm437240265e9.7.2026.03.02.07.13.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Mar 2026 07:13:56 -0800 (PST) From: Iker Pedrosa Date: Mon, 02 Mar 2026 16:13:26 +0100 Subject: [PATCH 05/10] mmc: sdhci-of-k1: add AIB register support for voltage switching Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260302-orangepi-sd-card-uhs-v1-5-89c219973c0c@gmail.com> References: <20260302-orangepi-sd-card-uhs-v1-0-89c219973c0c@gmail.com> In-Reply-To: <20260302-orangepi-sd-card-uhs-v1-0-89c219973c0c@gmail.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Adrian Hunter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: Michael Opdenacker , Javier Martinez Canillas , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, Iker Pedrosa X-Mailer: b4 0.14.2 Add support for SpacemiT K1 Analog Interface Block (AIB) register programming required for proper UHS voltage switching. The AIB register controls SoC-level voltage domain coordination between the SDHCI controller and I/O pins. - Add AIB register address parsing from device tree - Implement authentication sequence for secure register access - Add voltage domain switching for 3.3V/1.8V operation Signed-off-by: Iker Pedrosa --- drivers/mmc/host/sdhci-of-k1.c | 60 ++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 60 insertions(+) diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c index 2a982bca2a50ca96f43af7b4de5bc4fb4b5b195b..9425bde6a72541bd628997e91f9= 57072a6266c25 100644 --- a/drivers/mmc/host/sdhci-of-k1.c +++ b/drivers/mmc/host/sdhci-of-k1.c @@ -68,12 +68,19 @@ #define SDHC_PHY_DRIVE_SEL GENMASK(2, 0) #define SDHC_RX_BIAS_CTRL BIT(5) =20 +#define MMC1_IO_V18EN BIT(2) +#define AKEY_ASFAR 0xBABA +#define AKEY_ASSAR 0xEB10 + struct spacemit_sdhci_host { struct clk *clk_core; struct clk *clk_io; struct pinctrl *pinctrl; struct pinctrl_state *pinctrl_default; struct pinctrl_state *pinctrl_uhs; + u32 aib_mmc1_io_reg; + u32 apbc_asfar_reg; + u32 apbc_assar_reg; }; =20 /* All helper functions will update clr/set while preserve rest bits */ @@ -220,6 +227,47 @@ static void spacemit_sdhci_pre_hs400_to_hs200(struct m= mc_host *mmc) SPACEMIT_SDHC_PHY_CTRL_REG); } =20 +static void spacemit_sdhci_set_aib_mmc1_io(struct sdhci_host *host, int si= gnal_voltage) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct spacemit_sdhci_host *sdhst =3D sdhci_pltfm_priv(pltfm_host); + void __iomem *aib_reg, *asfar_reg, *assar_reg; + u32 reg_value; + + if (!sdhst->aib_mmc1_io_reg || !sdhst->apbc_asfar_reg || !sdhst->apbc_ass= ar_reg) + return; + + asfar_reg =3D ioremap(sdhst->apbc_asfar_reg, 4); + assar_reg =3D ioremap(sdhst->apbc_assar_reg, 4); + aib_reg =3D ioremap(sdhst->aib_mmc1_io_reg, 4); + + if (!asfar_reg || !assar_reg || !aib_reg) { + dev_err(mmc_dev(host->mmc), "Failed to map AIB registers\n"); + goto cleanup; + } + + writel(AKEY_ASFAR, asfar_reg); + writel(AKEY_ASSAR, assar_reg); + reg_value =3D readl(aib_reg); + + if (signal_voltage =3D=3D MMC_SIGNAL_VOLTAGE_180) + reg_value |=3D MMC1_IO_V18EN; + else + reg_value &=3D ~MMC1_IO_V18EN; + + writel(AKEY_ASFAR, asfar_reg); + writel(AKEY_ASSAR, assar_reg); + writel(reg_value, aib_reg); + +cleanup: + if (aib_reg) + iounmap(aib_reg); + if (asfar_reg) + iounmap(asfar_reg); + if (assar_reg) + iounmap(assar_reg); +} + static int spacemit_sdhci_start_signal_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) { @@ -233,6 +281,8 @@ static int spacemit_sdhci_start_signal_voltage_switch(s= truct mmc_host *mmc, if (ret) return ret; =20 + spacemit_sdhci_set_aib_mmc1_io(host, ios->signal_voltage); + /* Select appropriate pinctrl state based on signal voltage */ if (sdhst->pinctrl) { switch (ios->signal_voltage) { @@ -341,6 +391,16 @@ static int spacemit_sdhci_probe(struct platform_device= *pdev) dev_warn(dev, "Failed to get regulators: %d\n", ret); =20 sdhst =3D sdhci_pltfm_priv(pltfm_host); + + if (of_property_read_u32(dev->of_node, "spacemit,aib-mmc1-io-reg", &sdhst= ->aib_mmc1_io_reg)) + sdhst->aib_mmc1_io_reg =3D 0; + + if (of_property_read_u32(dev->of_node, "spacemit,apbc-asfar-reg", &sdhst-= >apbc_asfar_reg)) + sdhst->apbc_asfar_reg =3D 0; + + if (of_property_read_u32(dev->of_node, "spacemit,apbc-assar-reg", &sdhst-= >apbc_assar_reg)) + sdhst->apbc_assar_reg =3D 0; + sdhst->pinctrl =3D devm_pinctrl_get(dev); if (!IS_ERR(sdhst->pinctrl)) { sdhst->pinctrl_default =3D pinctrl_lookup_state(sdhst->pinctrl, "default= "); --=20 2.53.0