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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-899c7193227sm101354696d6.21.2026.03.02.00.28.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Mar 2026 00:28:41 -0800 (PST) From: Yongxing Mou Date: Mon, 02 Mar 2026 16:28:29 +0800 Subject: [PATCH v3 1/2] phy: qcom: edp: Add eDP/DP mode switch support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260302-edp_phy-v3-1-ca8888d793b0@oss.qualcomm.com> References: <20260302-edp_phy-v3-0-ca8888d793b0@oss.qualcomm.com> In-Reply-To: <20260302-edp_phy-v3-0-ca8888d793b0@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Stephen Boyd , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Yongxing Mou , stable@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772440115; l=8385; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=S2JW9nvnfu7j+y2B4VJo/pc6I2SO9Kjz/ltXVbvDAiw=; b=hYtAsZvh3OqA5KmQ2R8844BZr7OXifBB8PP0UO0YgAJ4iEtKbbA3tILbKuvfyDRmRvqrV6Stx iAUwJx1HZXYCOzzW53sLuMYf8CGbCIkOLP77CYF4FMAKf2nfcBdnkAp X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-GUID: V5LIZ9f6Fqtm5BRtPpq-z9SP7N7wMMJ7 X-Proofpoint-ORIG-GUID: V5LIZ9f6Fqtm5BRtPpq-z9SP7N7wMMJ7 X-Authority-Analysis: v=2.4 cv=Hpp72kTS c=1 sm=1 tr=0 ts=69a54a3b cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=fAMMRUVWeN1gI5VMqOgA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzAyMDA3MyBTYWx0ZWRfXzDKh1v30v7vy +tpZjV7+i7PMTDAFSND+6qcscoJYV+BUDPeiV6DgNfQ6ZS4qFjmd8GYdoixxz/bylEW5FAW2+s/ SDEKbJSZeG3rnkW9bJFtJcHazzUBf8oAqiObEPGJ0oSn4SrfVzERGS0YmRqO1kreQcVB2L1hrFf 4+upSSgOspOukeVNebg9i884YDi3UayB2PB1VQHfOBQ2VhyhT1I12zlkks/m6w6FeDZtMymAPDD aQOZr3nZFpmNrHzhh/tuc2VyqhHcXWjZFb947XRL2kvmk9LNB4z06HrU1ujOWp7DaMO7OYwRrjA JxEHjRgjqOamGcwKfMqs4pvd4SRM1mbosZK5M4XN4e1bLYcy+BRLL+rTD6vpGk+FuftYdmQFDMv G9pzWn/DQRScon+OyxA2p7aSKDhWI+Uv/iD1Pz7LHBKe07cwdFGP4scaPOznLqu6UIRAFIbUsLD 78hSfKSEu2HsD47N/dw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-02_02,2026-02-27_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 phishscore=0 priorityscore=1501 adultscore=0 bulkscore=0 malwarescore=0 clxscore=1015 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603020073 The eDP PHY supports both eDP&DP modes, each requires a different table. The current driver doesn't fully support every combo PHY mode and use either the eDP or DP table when enable the platform. In addition, some platforms mismatch between the mode and the table where DP mode uses the eDP table or eDP mode use the DP table. Clean up and correct the tables for currently supported platforms based on the HPG specification. Here lists the tables can be reused across current platforms. DP mode=EF=BC=9A -sa8775p/sc7280/sc8280xp/x1e80100 -glymur eDP mode(low vdiff): -glymur/sa8775p/sc8280xp/x1e80100 -sc7280 Cc: stable@vger.kernel.org Fixes: f199223cb490 ("phy: qcom: Introduce new eDP PHY driver") Signed-off-by: Yongxing Mou --- drivers/phy/qualcomm/phy-qcom-edp.c | 90 ++++++++++++++++++++++-----------= ---- 1 file changed, 53 insertions(+), 37 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy= -qcom-edp.c index 7372de05a0b8..36998326bae6 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -87,7 +87,8 @@ struct qcom_edp_phy_cfg { bool is_edp; const u8 *aux_cfg; const u8 *vco_div_cfg; - const struct qcom_edp_swing_pre_emph_cfg *swing_pre_emph_cfg; + const struct qcom_edp_swing_pre_emph_cfg *dp_swing_pre_emph_cfg; + const struct qcom_edp_swing_pre_emph_cfg *edp_swing_pre_emph_cfg; const struct phy_ver_ops *ver_ops; }; =20 @@ -116,17 +117,17 @@ struct qcom_edp { }; =20 static const u8 dp_swing_hbr_rbr[4][4] =3D { - { 0x08, 0x0f, 0x16, 0x1f }, + { 0x07, 0x0f, 0x16, 0x1f }, { 0x11, 0x1e, 0x1f, 0xff }, { 0x16, 0x1f, 0xff, 0xff }, { 0x1f, 0xff, 0xff, 0xff } }; =20 static const u8 dp_pre_emp_hbr_rbr[4][4] =3D { - { 0x00, 0x0d, 0x14, 0x1a }, + { 0x00, 0x0e, 0x15, 0x1a }, { 0x00, 0x0e, 0x15, 0xff }, { 0x00, 0x0e, 0xff, 0xff }, - { 0x03, 0xff, 0xff, 0xff } + { 0x04, 0xff, 0xff, 0xff } }; =20 static const u8 dp_swing_hbr2_hbr3[4][4] =3D { @@ -150,6 +151,20 @@ static const struct qcom_edp_swing_pre_emph_cfg dp_phy= _swing_pre_emph_cfg =3D { .pre_emphasis_hbr3_hbr2 =3D &dp_pre_emp_hbr2_hbr3, }; =20 +static const u8 dp_pre_emp_hbr_rbr_v8[4][4] =3D { + { 0x00, 0x0e, 0x15, 0x1a }, + { 0x00, 0x0e, 0x15, 0xff }, + { 0x00, 0x0e, 0xff, 0xff }, + { 0x00, 0xff, 0xff, 0xff } +}; + +static const struct qcom_edp_swing_pre_emph_cfg dp_phy_swing_pre_emph_cfg_= v8 =3D { + .swing_hbr_rbr =3D &dp_swing_hbr_rbr, + .swing_hbr3_hbr2 =3D &dp_swing_hbr2_hbr3, + .pre_emphasis_hbr_rbr =3D &dp_pre_emp_hbr_rbr_v8, + .pre_emphasis_hbr3_hbr2 =3D &dp_pre_emp_hbr2_hbr3, +}; + static const u8 edp_swing_hbr_rbr[4][4] =3D { { 0x07, 0x0f, 0x16, 0x1f }, { 0x0d, 0x16, 0x1e, 0xff }, @@ -158,7 +173,7 @@ static const u8 edp_swing_hbr_rbr[4][4] =3D { }; =20 static const u8 edp_pre_emp_hbr_rbr[4][4] =3D { - { 0x05, 0x12, 0x17, 0x1d }, + { 0x05, 0x11, 0x17, 0x1d }, { 0x05, 0x11, 0x18, 0xff }, { 0x06, 0x11, 0xff, 0xff }, { 0x00, 0xff, 0xff, 0xff } @@ -172,10 +187,10 @@ static const u8 edp_swing_hbr2_hbr3[4][4] =3D { }; =20 static const u8 edp_pre_emp_hbr2_hbr3[4][4] =3D { - { 0x08, 0x11, 0x17, 0x1b }, - { 0x00, 0x0c, 0x13, 0xff }, - { 0x05, 0x10, 0xff, 0xff }, - { 0x00, 0xff, 0xff, 0xff } + { 0x0c, 0x15, 0x19, 0x1e }, + { 0x0b, 0x15, 0x19, 0xff }, + { 0x0e, 0x14, 0xff, 0xff }, + { 0x0d, 0xff, 0xff, 0xff } }; =20 static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg= =3D { @@ -193,25 +208,25 @@ static const u8 edp_phy_vco_div_cfg_v4[4] =3D { 0x01, 0x01, 0x02, 0x00, }; =20 -static const u8 edp_pre_emp_hbr_rbr_v5[4][4] =3D { - { 0x05, 0x11, 0x17, 0x1d }, - { 0x05, 0x11, 0x18, 0xff }, - { 0x06, 0x11, 0xff, 0xff }, - { 0x00, 0xff, 0xff, 0xff } +static const u8 edp_swing_hbr2_hbr3_v3[4][4] =3D { + { 0x06, 0x11, 0x16, 0x1b }, + { 0x0b, 0x19, 0x1f, 0xff }, + { 0x18, 0x1f, 0xff, 0xff }, + { 0x1f, 0xff, 0xff, 0xff } }; =20 -static const u8 edp_pre_emp_hbr2_hbr3_v5[4][4] =3D { +static const u8 edp_pre_emp_hbr2_hbr3_v3[4][4] =3D { { 0x0c, 0x15, 0x19, 0x1e }, - { 0x0b, 0x15, 0x19, 0xff }, - { 0x0e, 0x14, 0xff, 0xff }, + { 0x09, 0x14, 0x19, 0xff }, + { 0x0f, 0x14, 0xff, 0xff }, { 0x0d, 0xff, 0xff, 0xff } }; =20 -static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg= _v5 =3D { +static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg= _v3 =3D { .swing_hbr_rbr =3D &edp_swing_hbr_rbr, - .swing_hbr3_hbr2 =3D &edp_swing_hbr2_hbr3, - .pre_emphasis_hbr_rbr =3D &edp_pre_emp_hbr_rbr_v5, - .pre_emphasis_hbr3_hbr2 =3D &edp_pre_emp_hbr2_hbr3_v5, + .swing_hbr3_hbr2 =3D &edp_swing_hbr2_hbr3_v3, + .pre_emphasis_hbr_rbr =3D &edp_pre_emp_hbr_rbr, + .pre_emphasis_hbr3_hbr2 =3D &edp_pre_emp_hbr2_hbr3_v3, }; =20 static const u8 edp_phy_aux_cfg_v5[DP_AUX_CFG_SIZE] =3D { @@ -262,12 +277,7 @@ static int qcom_edp_phy_init(struct phy *phy) DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, edp->edp + DP_PHY_PD_CTL); =20 - /* - * TODO: Re-work the conditions around setting the cfg8 value - * when more information becomes available about why this is - * even needed. - */ - if (edp->cfg->swing_pre_emph_cfg && !edp->is_edp) + if (!edp->is_edp) aux_cfg[8] =3D 0xb7; =20 writel(0xfc, edp->edp + DP_PHY_MODE); @@ -291,7 +301,7 @@ static int qcom_edp_phy_init(struct phy *phy) =20 static int qcom_edp_set_voltages(struct qcom_edp *edp, const struct phy_co= nfigure_opts_dp *dp_opts) { - const struct qcom_edp_swing_pre_emph_cfg *cfg =3D edp->cfg->swing_pre_emp= h_cfg; + const struct qcom_edp_swing_pre_emph_cfg *cfg; unsigned int v_level =3D 0; unsigned int p_level =3D 0; u8 ldo_config; @@ -299,11 +309,10 @@ static int qcom_edp_set_voltages(struct qcom_edp *edp= , const struct phy_configur u8 emph; int i; =20 - if (!cfg) - return 0; - if (edp->is_edp) - cfg =3D &edp_phy_swing_pre_emph_cfg; + cfg =3D edp->cfg->edp_swing_pre_emph_cfg; + else + cfg =3D edp->cfg->dp_swing_pre_emph_cfg; =20 for (i =3D 0; i < dp_opts->lanes; i++) { v_level =3D max(v_level, dp_opts->voltage[i]); @@ -564,20 +573,24 @@ static const struct qcom_edp_phy_cfg sa8775p_dp_phy_c= fg =3D { .is_edp =3D false, .aux_cfg =3D edp_phy_aux_cfg_v5, .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, - .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg_v5, + .dp_swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, + .edp_swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v4, }; =20 static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg =3D { .aux_cfg =3D edp_phy_aux_cfg_v4, .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, + .dp_swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, + .edp_swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg_v3, .ver_ops =3D &qcom_edp_phy_ops_v4, }; =20 static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg =3D { .aux_cfg =3D edp_phy_aux_cfg_v4, .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, - .swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, + .dp_swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, + .edp_swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v4, }; =20 @@ -585,7 +598,8 @@ static const struct qcom_edp_phy_cfg sc8280xp_edp_phy_c= fg =3D { .is_edp =3D true, .aux_cfg =3D edp_phy_aux_cfg_v4, .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, - .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, + .dp_swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, + .edp_swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v4, }; =20 @@ -766,7 +780,8 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v6 =3D= { static struct qcom_edp_phy_cfg x1e80100_phy_cfg =3D { .aux_cfg =3D edp_phy_aux_cfg_v4, .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, - .swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, + .dp_swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, + .edp_swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v6, }; =20 @@ -945,7 +960,8 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v8 =3D= { static struct qcom_edp_phy_cfg glymur_phy_cfg =3D { .aux_cfg =3D edp_phy_aux_cfg_v8, .vco_div_cfg =3D edp_phy_vco_div_cfg_v8, - .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg_v5, + .dp_swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg_v8, + .edp_swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v8, }; 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Introduce the com_ldo_config callback to correct LDO setting accroding to the HPG. Since SC7280 uses different LDO settings than SA8775P/SC8280XP, introduce qcom_edp_phy_ops_v3 to keep the LDO setting correct. Cc: stable@vger.kernel.org Fixes: f199223cb490 ("phy: qcom: Introduce new eDP PHY driver") Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Tested-by: Konrad Dybcio # SC8280XP X13s --- drivers/phy/qualcomm/phy-qcom-edp.c | 86 ++++++++++++++++++++++++++++++++-= ---- 1 file changed, 76 insertions(+), 10 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy= -qcom-edp.c index 36998326bae6..d29e548fce9d 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -81,6 +81,7 @@ struct phy_ver_ops { int (*com_clk_fwd_cfg)(const struct qcom_edp *edp); int (*com_configure_pll)(const struct qcom_edp *edp); int (*com_configure_ssc)(const struct qcom_edp *edp); + int (*com_ldo_config)(const struct qcom_edp *edp); }; =20 struct qcom_edp_phy_cfg { @@ -304,7 +305,7 @@ static int qcom_edp_set_voltages(struct qcom_edp *edp, = const struct phy_configur const struct qcom_edp_swing_pre_emph_cfg *cfg; unsigned int v_level =3D 0; unsigned int p_level =3D 0; - u8 ldo_config; + int ret; u8 swing; u8 emph; int i; @@ -330,13 +331,13 @@ static int qcom_edp_set_voltages(struct qcom_edp *edp= , const struct phy_configur if (swing =3D=3D 0xff || emph =3D=3D 0xff) return -EINVAL; =20 - ldo_config =3D edp->is_edp ? 0x0 : 0x1; + ret =3D edp->cfg->ver_ops->com_ldo_config(edp); + if (ret) + return ret; =20 - writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); writel(swing, edp->tx0 + TXn_TX_DRV_LVL); writel(emph, edp->tx0 + TXn_TX_EMP_POST1_LVL); =20 - writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG); writel(swing, edp->tx1 + TXn_TX_DRV_LVL); writel(emph, edp->tx1 + TXn_TX_EMP_POST1_LVL); =20 @@ -560,6 +561,52 @@ static int qcom_edp_com_configure_pll_v4(const struct = qcom_edp *edp) return 0; } =20 +static int qcom_edp_ldo_config_v3(const struct qcom_edp *edp) +{ + const struct phy_configure_opts_dp *dp_opts =3D &edp->dp_opts; + u32 ldo_config; + + if (!edp->is_edp) + ldo_config =3D 0x0; + else if (dp_opts->link_rate <=3D 2700) + ldo_config =3D 0x81; + else + ldo_config =3D 0x41; + + writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); + writel(dp_opts->lanes > 2 ? ldo_config : 0x00, edp->tx1 + TXn_LDO_CONFIG); + + return 0; +} + +static int qcom_edp_ldo_config_v4(const struct qcom_edp *edp) +{ + const struct phy_configure_opts_dp *dp_opts =3D &edp->dp_opts; + u32 ldo_config; + + if (!edp->is_edp) + ldo_config =3D 0x0; + else if (dp_opts->link_rate <=3D 2700) + ldo_config =3D 0xc1; + else + ldo_config =3D 0x81; + + writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); + writel(dp_opts->lanes > 2 ? ldo_config : 0x00, edp->tx1 + TXn_LDO_CONFIG); + + return 0; +} + +static const struct phy_ver_ops qcom_edp_phy_ops_v3 =3D { + .com_power_on =3D qcom_edp_phy_power_on_v4, + .com_resetsm_cntrl =3D qcom_edp_phy_com_resetsm_cntrl_v4, + .com_bias_en_clkbuflr =3D qcom_edp_com_bias_en_clkbuflr_v4, + .com_clk_fwd_cfg =3D qcom_edp_com_clk_fwd_cfg_v4, + .com_configure_pll =3D qcom_edp_com_configure_pll_v4, + .com_configure_ssc =3D qcom_edp_com_configure_ssc_v4, + .com_ldo_config =3D qcom_edp_ldo_config_v3, +}; + static const struct phy_ver_ops qcom_edp_phy_ops_v4 =3D { .com_power_on =3D qcom_edp_phy_power_on_v4, .com_resetsm_cntrl =3D qcom_edp_phy_com_resetsm_cntrl_v4, @@ -567,6 +614,7 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v4 =3D= { .com_clk_fwd_cfg =3D qcom_edp_com_clk_fwd_cfg_v4, .com_configure_pll =3D qcom_edp_com_configure_pll_v4, .com_configure_ssc =3D qcom_edp_com_configure_ssc_v4, + .com_ldo_config =3D qcom_edp_ldo_config_v4, }; =20 static const struct qcom_edp_phy_cfg sa8775p_dp_phy_cfg =3D { @@ -583,7 +631,7 @@ static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg = =3D { .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, .dp_swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, .edp_swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg_v3, - .ver_ops =3D &qcom_edp_phy_ops_v4, + .ver_ops =3D &qcom_edp_phy_ops_v3, }; =20 static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg =3D { @@ -768,6 +816,24 @@ static int qcom_edp_com_configure_pll_v6(const struct = qcom_edp *edp) return 0; } =20 +static int qcom_edp_ldo_config_v6(const struct qcom_edp *edp) +{ + const struct phy_configure_opts_dp *dp_opts =3D &edp->dp_opts; + u32 ldo_config; + + if (!edp->is_edp) + ldo_config =3D 0x0; + else if (dp_opts->link_rate <=3D 2700) + ldo_config =3D 0x51; + else + ldo_config =3D 0x91; + + writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); + writel(dp_opts->lanes > 2 ? ldo_config : 0x00, edp->tx1 + TXn_LDO_CONFIG); + + return 0; +} + static const struct phy_ver_ops qcom_edp_phy_ops_v6 =3D { .com_power_on =3D qcom_edp_phy_power_on_v6, .com_resetsm_cntrl =3D qcom_edp_phy_com_resetsm_cntrl_v6, @@ -775,6 +841,7 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v6 =3D= { .com_clk_fwd_cfg =3D qcom_edp_com_clk_fwd_cfg_v4, .com_configure_pll =3D qcom_edp_com_configure_pll_v6, .com_configure_ssc =3D qcom_edp_com_configure_ssc_v6, + .com_ldo_config =3D qcom_edp_ldo_config_v6, }; =20 static struct qcom_edp_phy_cfg x1e80100_phy_cfg =3D { @@ -955,6 +1022,7 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v8 = =3D { .com_clk_fwd_cfg =3D qcom_edp_com_clk_fwd_cfg_v8, .com_configure_pll =3D qcom_edp_com_configure_pll_v8, .com_configure_ssc =3D qcom_edp_com_configure_ssc_v8, + .com_ldo_config =3D qcom_edp_ldo_config_v6, }; =20 static struct qcom_edp_phy_cfg glymur_phy_cfg =3D { @@ -970,7 +1038,6 @@ static int qcom_edp_phy_power_on(struct phy *phy) const struct qcom_edp *edp =3D phy_get_drvdata(phy); u32 bias0_en, drvr0_en, bias1_en, drvr1_en; unsigned long pixel_freq; - u8 ldo_config =3D 0x0; int ret; u32 val; u8 cfg1; @@ -979,11 +1046,10 @@ static int qcom_edp_phy_power_on(struct phy *phy) if (ret) return ret; =20 - if (edp->cfg->swing_pre_emph_cfg && !edp->is_edp) - ldo_config =3D 0x1; + ret =3D edp->cfg->ver_ops->com_ldo_config(edp); + if (ret) + return ret; =20 - writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); - writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG); writel(0x00, edp->tx0 + TXn_LANE_MODE_1); writel(0x00, edp->tx1 + TXn_LANE_MODE_1); =20 --=20 2.43.0