From nobody Tue Mar 3 03:38:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94E8B2E1722; Mon, 2 Mar 2026 22:59:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772492377; cv=none; b=GURLgaxACD+0c5adG2OCTsxlLm9QJx74NZ2pgXUngRRgXrMblyFjm/JIgh72XAT+paZwh6sD2JUTsTz5kwoHVMZxph6QucmP8fVnOL/k6H6E0opzjH5ogfNcTLHj5ONfcNlP6IVfwhMnQ2oM7CyKIQfOH+y4bexYXRhobonWSn8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772492377; c=relaxed/simple; bh=Yklx4zEo9cXGREGB2xC+IAAlfxMNB8VGv2zZDAGKwno=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PKotLLtMdgWxYmOjBk4N7+YG+YWAtLvmnuGPVdwd2D01uQisOXB8l9y7Z5tQ/hyTViLbSPgUFCtOTWMKRN7bFDz26Nc9k99AeHmU8a6l2hX4eBe02DJq+JJjHsEUt+bni4Atd1B3urcwzFKApO8eEts/498q5GnqWowoP1UbZCU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GOUkhSVG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GOUkhSVG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 94264C2BC9E; Mon, 2 Mar 2026 22:59:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772492377; bh=Yklx4zEo9cXGREGB2xC+IAAlfxMNB8VGv2zZDAGKwno=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=GOUkhSVGhp7WkkZoniEyCCz5f7v8CexC5qsFUUYzjDDGEAWS7vF1ij/hsC9i1F+Y4 ezDqyL4I0m/kfyEas44iM4OGuI3vTf9d77lHsqZ221oE/mQbfhnS+If6C036C101UH HLhxo7Rv6qPrBQT5AISpAW1R4qkAlnGsjY/IKVRbgtKZ8ecKEsfjdYL75db+PVCaz6 yBLf/Wo0n2De4maZfvu/bmyMRAl0BpbI4HqfUDu5gY++7nDZMBeowFIZImBsDpbqK+ Q6wTSG3IBRUU6iMefcHsUWfsAwTYJmw0CzbT/QI6oZ3HsvreOP13ft3AMELSvSH8n7 9dJfzY7SZGlqQ== From: Mark Brown Date: Mon, 02 Mar 2026 22:53:16 +0000 Subject: [PATCH 1/8] arm64/hwcap: Generate the KERNEL_HWCAP_ definitions for the hwcaps Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260302-arm64-dpisa-2025-v1-1-0855e7f41689@kernel.org> References: <20260302-arm64-dpisa-2025-v1-0-0855e7f41689@kernel.org> In-Reply-To: <20260302-arm64-dpisa-2025-v1-0-0855e7f41689@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-38bf1 X-Developer-Signature: v=1; a=openpgp-sha256; l=9808; i=broonie@kernel.org; h=from:subject:message-id; bh=Yklx4zEo9cXGREGB2xC+IAAlfxMNB8VGv2zZDAGKwno=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBpphZPqxeGaYiC9IZG1hRWASmJi6jcQJvsfbk6S 1s1VlSeRNiJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaaYWTwAKCRAk1otyXVSH 0D+qB/9FksFK8vWAamBu1Xg0yzT23NllAD1NsQF9cS61ka8QUj0cCPNPDH8LMVq0r5rFf8J++7h phJzbDfiAT5XFJs9JhBfBqDZODX+20lJ80rUZrTGgz568RDireVWBFm73MM1853dj/IWgMmqdi6 yQItwOj0FNzD3QeDmZPblBLGLDfF5Duk71KMd+JX0pXFQwgXaoTF4cgnw4xAi2rFKBnTmGI69I/ zmCegdnIFB7h8mxllmFlyiN4iO98N7r0ib89JaGMb8uGubcRdxxclGMeLiZ1RbQI1HHWwW01JJl Y4mNoVnKm6vhbYj5JCXFBBYE3CoovKQMJsWBSQ7NQFJGdsku X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Currently for each hwcap we define both the HWCAPn_NAME definition which is exposed to userspace and a kernel internal KERNEL_HWCAP_NAME definition which we use internally. This is tedious and repetitive, instead use a script to generate the KERNEL_HWCAP_ definitions from the UAPI definitions. No functional changes intended. Signed-off-by: Mark Brown --- arch/arm64/include/asm/hwcap.h | 120 +-----------------------------= ---- arch/arm64/tools/Makefile | 8 ++- arch/arm64/tools/gen-kernel-hwcaps.sh | 23 +++++++ 3 files changed, 32 insertions(+), 119 deletions(-) diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h index 72ea4bda79f3..abe8218b2325 100644 --- a/arch/arm64/include/asm/hwcap.h +++ b/arch/arm64/include/asm/hwcap.h @@ -60,126 +60,10 @@ * of KERNEL_HWCAP_{feature}. */ #define __khwcap_feature(x) const_ilog2(HWCAP_ ## x) -#define KERNEL_HWCAP_FP __khwcap_feature(FP) -#define KERNEL_HWCAP_ASIMD __khwcap_feature(ASIMD) -#define KERNEL_HWCAP_EVTSTRM __khwcap_feature(EVTSTRM) -#define KERNEL_HWCAP_AES __khwcap_feature(AES) -#define KERNEL_HWCAP_PMULL __khwcap_feature(PMULL) -#define KERNEL_HWCAP_SHA1 __khwcap_feature(SHA1) -#define KERNEL_HWCAP_SHA2 __khwcap_feature(SHA2) -#define KERNEL_HWCAP_CRC32 __khwcap_feature(CRC32) -#define KERNEL_HWCAP_ATOMICS __khwcap_feature(ATOMICS) -#define KERNEL_HWCAP_FPHP __khwcap_feature(FPHP) -#define KERNEL_HWCAP_ASIMDHP __khwcap_feature(ASIMDHP) -#define KERNEL_HWCAP_CPUID __khwcap_feature(CPUID) -#define KERNEL_HWCAP_ASIMDRDM __khwcap_feature(ASIMDRDM) -#define KERNEL_HWCAP_JSCVT __khwcap_feature(JSCVT) -#define KERNEL_HWCAP_FCMA __khwcap_feature(FCMA) -#define KERNEL_HWCAP_LRCPC __khwcap_feature(LRCPC) -#define KERNEL_HWCAP_DCPOP __khwcap_feature(DCPOP) -#define KERNEL_HWCAP_SHA3 __khwcap_feature(SHA3) -#define KERNEL_HWCAP_SM3 __khwcap_feature(SM3) -#define KERNEL_HWCAP_SM4 __khwcap_feature(SM4) -#define KERNEL_HWCAP_ASIMDDP __khwcap_feature(ASIMDDP) -#define KERNEL_HWCAP_SHA512 __khwcap_feature(SHA512) -#define KERNEL_HWCAP_SVE __khwcap_feature(SVE) -#define KERNEL_HWCAP_ASIMDFHM __khwcap_feature(ASIMDFHM) -#define KERNEL_HWCAP_DIT __khwcap_feature(DIT) -#define KERNEL_HWCAP_USCAT __khwcap_feature(USCAT) -#define KERNEL_HWCAP_ILRCPC __khwcap_feature(ILRCPC) -#define KERNEL_HWCAP_FLAGM __khwcap_feature(FLAGM) -#define KERNEL_HWCAP_SSBS __khwcap_feature(SSBS) -#define KERNEL_HWCAP_SB __khwcap_feature(SB) -#define KERNEL_HWCAP_PACA __khwcap_feature(PACA) -#define KERNEL_HWCAP_PACG __khwcap_feature(PACG) -#define KERNEL_HWCAP_GCS __khwcap_feature(GCS) -#define KERNEL_HWCAP_CMPBR __khwcap_feature(CMPBR) -#define KERNEL_HWCAP_FPRCVT __khwcap_feature(FPRCVT) -#define KERNEL_HWCAP_F8MM8 __khwcap_feature(F8MM8) -#define KERNEL_HWCAP_F8MM4 __khwcap_feature(F8MM4) -#define KERNEL_HWCAP_SVE_F16MM __khwcap_feature(SVE_F16MM) -#define KERNEL_HWCAP_SVE_ELTPERM __khwcap_feature(SVE_ELTPERM) -#define KERNEL_HWCAP_SVE_AES2 __khwcap_feature(SVE_AES2) -#define KERNEL_HWCAP_SVE_BFSCALE __khwcap_feature(SVE_BFSCALE) -#define KERNEL_HWCAP_SVE2P2 __khwcap_feature(SVE2P2) -#define KERNEL_HWCAP_SME2P2 __khwcap_feature(SME2P2) -#define KERNEL_HWCAP_SME_SBITPERM __khwcap_feature(SME_SBITPERM) -#define KERNEL_HWCAP_SME_AES __khwcap_feature(SME_AES) -#define KERNEL_HWCAP_SME_SFEXPA __khwcap_feature(SME_SFEXPA) -#define KERNEL_HWCAP_SME_STMOP __khwcap_feature(SME_STMOP) -#define KERNEL_HWCAP_SME_SMOP4 __khwcap_feature(SME_SMOP4) - #define __khwcap2_feature(x) (const_ilog2(HWCAP2_ ## x) + 64) -#define KERNEL_HWCAP_DCPODP __khwcap2_feature(DCPODP) -#define KERNEL_HWCAP_SVE2 __khwcap2_feature(SVE2) -#define KERNEL_HWCAP_SVEAES __khwcap2_feature(SVEAES) -#define KERNEL_HWCAP_SVEPMULL __khwcap2_feature(SVEPMULL) -#define KERNEL_HWCAP_SVEBITPERM __khwcap2_feature(SVEBITPERM) -#define KERNEL_HWCAP_SVESHA3 __khwcap2_feature(SVESHA3) -#define KERNEL_HWCAP_SVESM4 __khwcap2_feature(SVESM4) -#define KERNEL_HWCAP_FLAGM2 __khwcap2_feature(FLAGM2) -#define KERNEL_HWCAP_FRINT __khwcap2_feature(FRINT) -#define KERNEL_HWCAP_SVEI8MM __khwcap2_feature(SVEI8MM) -#define KERNEL_HWCAP_SVEF32MM __khwcap2_feature(SVEF32MM) -#define KERNEL_HWCAP_SVEF64MM __khwcap2_feature(SVEF64MM) -#define KERNEL_HWCAP_SVEBF16 __khwcap2_feature(SVEBF16) -#define KERNEL_HWCAP_I8MM __khwcap2_feature(I8MM) -#define KERNEL_HWCAP_BF16 __khwcap2_feature(BF16) -#define KERNEL_HWCAP_DGH __khwcap2_feature(DGH) -#define KERNEL_HWCAP_RNG __khwcap2_feature(RNG) -#define KERNEL_HWCAP_BTI __khwcap2_feature(BTI) -#define KERNEL_HWCAP_MTE __khwcap2_feature(MTE) -#define KERNEL_HWCAP_ECV __khwcap2_feature(ECV) -#define KERNEL_HWCAP_AFP __khwcap2_feature(AFP) -#define KERNEL_HWCAP_RPRES __khwcap2_feature(RPRES) -#define KERNEL_HWCAP_MTE3 __khwcap2_feature(MTE3) -#define KERNEL_HWCAP_SME __khwcap2_feature(SME) -#define KERNEL_HWCAP_SME_I16I64 __khwcap2_feature(SME_I16I64) -#define KERNEL_HWCAP_SME_F64F64 __khwcap2_feature(SME_F64F64) -#define KERNEL_HWCAP_SME_I8I32 __khwcap2_feature(SME_I8I32) -#define KERNEL_HWCAP_SME_F16F32 __khwcap2_feature(SME_F16F32) -#define KERNEL_HWCAP_SME_B16F32 __khwcap2_feature(SME_B16F32) -#define KERNEL_HWCAP_SME_F32F32 __khwcap2_feature(SME_F32F32) -#define KERNEL_HWCAP_SME_FA64 __khwcap2_feature(SME_FA64) -#define KERNEL_HWCAP_WFXT __khwcap2_feature(WFXT) -#define KERNEL_HWCAP_EBF16 __khwcap2_feature(EBF16) -#define KERNEL_HWCAP_SVE_EBF16 __khwcap2_feature(SVE_EBF16) -#define KERNEL_HWCAP_CSSC __khwcap2_feature(CSSC) -#define KERNEL_HWCAP_RPRFM __khwcap2_feature(RPRFM) -#define KERNEL_HWCAP_SVE2P1 __khwcap2_feature(SVE2P1) -#define KERNEL_HWCAP_SME2 __khwcap2_feature(SME2) -#define KERNEL_HWCAP_SME2P1 __khwcap2_feature(SME2P1) -#define KERNEL_HWCAP_SME_I16I32 __khwcap2_feature(SME_I16I32) -#define KERNEL_HWCAP_SME_BI32I32 __khwcap2_feature(SME_BI32I32) -#define KERNEL_HWCAP_SME_B16B16 __khwcap2_feature(SME_B16B16) -#define KERNEL_HWCAP_SME_F16F16 __khwcap2_feature(SME_F16F16) -#define KERNEL_HWCAP_MOPS __khwcap2_feature(MOPS) -#define KERNEL_HWCAP_HBC __khwcap2_feature(HBC) -#define KERNEL_HWCAP_SVE_B16B16 __khwcap2_feature(SVE_B16B16) -#define KERNEL_HWCAP_LRCPC3 __khwcap2_feature(LRCPC3) -#define KERNEL_HWCAP_LSE128 __khwcap2_feature(LSE128) -#define KERNEL_HWCAP_FPMR __khwcap2_feature(FPMR) -#define KERNEL_HWCAP_LUT __khwcap2_feature(LUT) -#define KERNEL_HWCAP_FAMINMAX __khwcap2_feature(FAMINMAX) -#define KERNEL_HWCAP_F8CVT __khwcap2_feature(F8CVT) -#define KERNEL_HWCAP_F8FMA __khwcap2_feature(F8FMA) -#define KERNEL_HWCAP_F8DP4 __khwcap2_feature(F8DP4) -#define KERNEL_HWCAP_F8DP2 __khwcap2_feature(F8DP2) -#define KERNEL_HWCAP_F8E4M3 __khwcap2_feature(F8E4M3) -#define KERNEL_HWCAP_F8E5M2 __khwcap2_feature(F8E5M2) -#define KERNEL_HWCAP_SME_LUTV2 __khwcap2_feature(SME_LUTV2) -#define KERNEL_HWCAP_SME_F8F16 __khwcap2_feature(SME_F8F16) -#define KERNEL_HWCAP_SME_F8F32 __khwcap2_feature(SME_F8F32) -#define KERNEL_HWCAP_SME_SF8FMA __khwcap2_feature(SME_SF8FMA) -#define KERNEL_HWCAP_SME_SF8DP4 __khwcap2_feature(SME_SF8DP4) -#define KERNEL_HWCAP_SME_SF8DP2 __khwcap2_feature(SME_SF8DP2) -#define KERNEL_HWCAP_POE __khwcap2_feature(POE) - #define __khwcap3_feature(x) (const_ilog2(HWCAP3_ ## x) + 128) -#define KERNEL_HWCAP_MTE_FAR __khwcap3_feature(MTE_FAR) -#define KERNEL_HWCAP_MTE_STORE_ONLY __khwcap3_feature(MTE_STORE_ONLY) -#define KERNEL_HWCAP_LSFE __khwcap3_feature(LSFE) -#define KERNEL_HWCAP_LS64 __khwcap3_feature(LS64) + +#include "asm/kernel-hwcap.h" =20 /* * This yields a mask that user programs can use to figure out what diff --git a/arch/arm64/tools/Makefile b/arch/arm64/tools/Makefile index c2b34e761006..a94b3d9caad6 100644 --- a/arch/arm64/tools/Makefile +++ b/arch/arm64/tools/Makefile @@ -3,7 +3,7 @@ gen :=3D arch/$(ARCH)/include/generated kapi :=3D $(gen)/asm =20 -kapisyshdr-y :=3D cpucap-defs.h sysreg-defs.h +kapisyshdr-y :=3D cpucap-defs.h kernel-hwcap.h sysreg-defs.h =20 kapi-hdrs-y :=3D $(addprefix $(kapi)/, $(kapisyshdr-y)) =20 @@ -18,11 +18,17 @@ kapi: $(kapi-hdrs-y) quiet_cmd_gen_cpucaps =3D GEN $@ cmd_gen_cpucaps =3D mkdir -p $(dir $@); $(AWK) -f $(real-prereqs) > = $@ =20 +quiet_cmd_gen_kernel_hwcap =3D GEN $@ + cmd_gen_kernel_hwcap =3D mkdir -p $(dir $@); /bin/sh -e $(real-prere= qs) > $@ + quiet_cmd_gen_sysreg =3D GEN $@ cmd_gen_sysreg =3D mkdir -p $(dir $@); $(AWK) -f $(real-prereqs) > $@ =20 $(kapi)/cpucap-defs.h: $(src)/gen-cpucaps.awk $(src)/cpucaps FORCE $(call if_changed,gen_cpucaps) =20 +$(kapi)/kernel-hwcap.h: $(src)/gen-kernel-hwcaps.sh $(srctree)/arch/arm64/= include/uapi/asm/hwcap.h FORCE + $(call if_changed,gen_kernel_hwcap) + $(kapi)/sysreg-defs.h: $(src)/gen-sysreg.awk $(src)/sysreg FORCE $(call if_changed,gen_sysreg) diff --git a/arch/arm64/tools/gen-kernel-hwcaps.sh b/arch/arm64/tools/gen-k= ernel-hwcaps.sh new file mode 100644 index 000000000000..e7cdcf428d91 --- /dev/null +++ b/arch/arm64/tools/gen-kernel-hwcaps.sh @@ -0,0 +1,23 @@ +#!/bin/sh -e +# SPDX-License-Identifier: GPL-2.0 +# +# gen-kernel-hwcap.sh - Generate kernel internal hwcap.h definitions +# +# Copyright 2026 Arm, Ltd. + +if [ "$1" =3D "" ]; then + echo "$0: no filename specified" + exit 1 +fi + +echo "#ifndef __ASM_KERNEL_HWCAPS_H" +echo "#define __ASM_KERNEL_HWCAPS_H" +echo "" +echo "/* Generated file - do not edit */" +echo "" + +grep -E '^#define HWCAP[0-9]*_[A-Z0-9_]+' $1 | \ + sed 's/.*HWCAP\([0-9]*\)_\([A-Z0-9_]\+\).*/#define KERNEL_HWCAP_\2\t__khw= cap\1_feature(\2)/' + +echo "" +echo "#endif /* __ASM_KERNEL_HWCAPS_H */" --=20 2.47.3 From nobody Tue Mar 3 03:38:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A08F531F9B8; Mon, 2 Mar 2026 22:59:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772492379; cv=none; b=tDfNnhtMhyEnDhOuEeN7YHn7C/iKnXwK/fUoLHxApH01za3ohXWclB5i/vXby6E8RNRK7yZ+W5VoYdIhHJGEJg02TjEwBx9tIC95FmPJizvf/8ASN/vol+t+4kZsEvrLDX4BQP4ffixWMlPYt8EqwoufqWVuXpbFj0E0HViSDAo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772492379; c=relaxed/simple; bh=1Y2Bq9RZnh/y+WhW+nbmbBevrPdJ+64IRYiYABDxDkQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=K31EujeH1r2rvnMOmmFWbAVMN9ZSUEoQJd/tTHnUkBrCRw8jFc/OGWRAReYJqlYX67FKEVmTeoWbDH4ScdD7iJjXNol91i2wUIxnuoWezSiqkWHTGwnLQPbQLwk1n7M3jExKoC9IrD0KcH3BHq5TKBZaFiLimUidtn7VfTMO+Vo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BJU2ylMc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BJU2ylMc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A13B3C2BCB0; Mon, 2 Mar 2026 22:59:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772492379; bh=1Y2Bq9RZnh/y+WhW+nbmbBevrPdJ+64IRYiYABDxDkQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=BJU2ylMchmveFvOo8jidxLebv0z5YW5nBMKZwbc84IXP2HjyMqSRM1qV11WktDpKb ZMmElVmX79x8NOSoLHk6HVxw+1yNzrMFa0Xwl2yG112Af3/6Gz91pfaRUomkbGR66u XBrGTG3O2jncVZzwxfH3P+e2bkQLAKhheH5NmaSAQGPPLk1RfanQv+4v/T4Yri605S pEB+bKLAaQhHz15RbLev+eoPP5m1q2L9k0xP7uG4w12vkR65/neEc2Mb73zAXKuRFv YOI3GDSp6ENDA7efTPmwJRTHZmUNR7peITj5N0S5H15Nf+OhZWBT3jfTKkuCUon8Dc hjALaGoHIso8Q== From: Mark Brown Date: Mon, 02 Mar 2026 22:53:17 +0000 Subject: [PATCH 2/8] arm64/sysreg: Update ID_AA64ISAR0_EL1 description to DDI0601 2025-12 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260302-arm64-dpisa-2025-v1-2-0855e7f41689@kernel.org> References: <20260302-arm64-dpisa-2025-v1-0-0855e7f41689@kernel.org> In-Reply-To: <20260302-arm64-dpisa-2025-v1-0-0855e7f41689@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-38bf1 X-Developer-Signature: v=1; a=openpgp-sha256; l=534; i=broonie@kernel.org; h=from:subject:message-id; bh=1Y2Bq9RZnh/y+WhW+nbmbBevrPdJ+64IRYiYABDxDkQ=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBpphZPOQKIFjhY6njCjprG3IPtIaVhniJ04UQA7 BeR9yCsQxKJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaaYWTwAKCRAk1otyXVSH 0DsuB/9AS2b1JoJ/2zrQoyeNO9LuorbifIHkLRQ2CtvP6CY6n1UtqkdpEdO6icM7sR/oLmQjrjh 4QtLiE95mL6G0AMHSgQjVFLpnBFsarwkjeOcGK9ieU5rQ2/K28Yf84xCcMuoWt66HGoJWJFpObY M4Q/9rSx11OFXHnEdIXBBZo9SY3nqQGnOkFNCKrgVKmUl2dlJCPOM8gWaUnhUOoJ5HUbhQqybNJ xDpiebYqf1mXIyvMfI6gXsmCyBxq6VG83JVYAmO7X2JQB1iGh6XyULJe9PeuOCVfeU2pXMZVC7E CoTtFMxg3P2zf9VPiYNyZkS/BAcqoH2HfXfU1xG5qZCpoZKR X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB The 2025 extensions add FEAT_F16F32DOT and FEAT_F16F32MM. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 9d1c21108057..623577b7554b 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1835,6 +1835,8 @@ EndEnum UnsignedEnum 51:48 FHM 0b0000 NI 0b0001 IMP + 0b0010 F16F32DOT + 0b0011 F16F32MM EndEnum UnsignedEnum 47:44 DP 0b0000 NI --=20 2.47.3 From nobody Tue Mar 3 03:38:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A39F7317169; Mon, 2 Mar 2026 22:59:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772492381; cv=none; b=WHKV58Vc2QmKaaZ2yK9khZyI4DNDCl2G76LQ7qGjtOHOXQa/rblp9MGAq4YXZ1nOWBL97UEsflyaVWmfnZKZGEbXeVH9iTpbvp9KowsObNThhwVFX2303AHrqriMzOyNPyZrlunnVaew5otdYDlnto8VtP3vGN8oaXguwuL/7Rs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772492381; c=relaxed/simple; bh=PtfcxF9KcORftVGAXfd58IX/BO8+KKdxndL+8xF0gOA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cNIo6JLqrOcbBMKaSGCqoFMHeqAcUA05NpwJwhwoz8SKUHM1n2peM4MJ91mj9RJcR9IqyomjFfZiygKHNiliwFj/jXLWpMhmCnG/m04PWyLHp2Yuk2k3IFSbgxfUqsVJ1bya/h0kjfiUqOqdV+/xzxF6dEsROliPwHVwsgZ8+BM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hl6tUKXu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hl6tUKXu" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AB595C2BCB1; Mon, 2 Mar 2026 22:59:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772492381; bh=PtfcxF9KcORftVGAXfd58IX/BO8+KKdxndL+8xF0gOA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=hl6tUKXuEcavV2hhYUPDket+05sdUf2MhbUytP05hdDz6P7xZs0rD71Me4SzVQhhH 4muRY8RcKlt6mEhDhg6fkzt5mT1i38h8of/z3xKRXnC2m5ftrO+xErvEcfOsjwmH6i 8S+aEocKm9061lGipdo8/HeHVEg972m4/ttsDwmVChehM42wUGZPgZ0VhKRhfc16Vz fWHSLIyOfYCyz2D7PvdDyn89HEw/oV7y+iU7OoiAouDcHmV1Vxx0u3njnr9s97YznR WU8dWDnYfSq1AzAROpwJNxewZ8YRP1a/ObM3XOseTuDWHCvU1b9voKvj0q1XkUqMfY uwJWD5+yIHfbQ== From: Mark Brown Date: Mon, 02 Mar 2026 22:53:18 +0000 Subject: [PATCH 3/8] arm64/sysreg: Update ID_AA64ISAR2_EL1 description to DDI0601 2025-12 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260302-arm64-dpisa-2025-v1-3-0855e7f41689@kernel.org> References: <20260302-arm64-dpisa-2025-v1-0-0855e7f41689@kernel.org> In-Reply-To: <20260302-arm64-dpisa-2025-v1-0-0855e7f41689@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-38bf1 X-Developer-Signature: v=1; a=openpgp-sha256; l=587; i=broonie@kernel.org; h=from:subject:message-id; bh=PtfcxF9KcORftVGAXfd58IX/BO8+KKdxndL+8xF0gOA=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBpphZQ04+K+tILLsIzCBUDqzM9L+KkjnT1cuQZQ H2WgqdvzPOJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaaYWUAAKCRAk1otyXVSH 0Il1B/0RHFHUr5JF6GIdPVGFVcg5NP+JUu0mxrimmH0RAAFPOYfxGGumlYmBMevEC1etYw3ns+B kKH9dpQ/UI9QFZl6cv1zup+yoifdfmz8G8cJ7q2tRZXzkbszMXCsGwou/fl6cyHsRsWdxPl9w5k SX5Kfw2v90ukZwKcxx9mOSDgGMMEfsEAG7C+iOk67wjh+Ri+3N533derldmdhXJv5Qk5o+aUUhN P7eAfE6/JNE5CtuC3HQAjCY2aD5/rVPM96fLFvrbBns0w0zcA7u2XJA7oMGMJG/vugeHylOA1ue EdXRn2Cx+yhumRaFO90EEkOjiSfbU3/s8pxdaxo0DS2cATQo X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB The 2025 extensions update the LUT field for new instructions added by SVE and SME 2.3, there is no separate FEAT_ feature for these. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 623577b7554b..0d619c173c87 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1978,6 +1978,7 @@ EndEnum UnsignedEnum 59:56 LUT 0b0000 NI 0b0001 IMP + 0b0010 LUT6 EndEnum UnsignedEnum 55:52 CSSC 0b0000 NI --=20 2.47.3 From nobody Tue Mar 3 03:38:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A95C1AF0BB; Mon, 2 Mar 2026 22:59:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772492383; cv=none; b=UJztjlYfsKAgbtAeeHdx3XhpC2qgbtYXgX4ahI7HqqIiRLQ7FEii2NKSzhp57ljCXRkplhQ/9pHn/YlU2N1Za27EsiilbpRuLBd2XyBqUFfr38PXwJg3sCrIWVyHz2gMCBAx5sMkwL41af4IHFzYq6Go2Jdm+lm8SVGcIkImyG8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772492383; c=relaxed/simple; bh=3cDEmPbM/ZrYkcKE8GG467rShtzE9T3OP7Nd6C9sgls=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EFUCBy1oJU7dnxchfwZQDrgC332RG7pYaVoATmki/JcZWm2HobHqjV5aLdL2d/nX1OZ+3/hmInHm+q8qsA8qzORR8e6Jx6bM0l21RdDfMaj+usWwWg46ZR17LR9eHPuXH423IN0yEMSXKGRw3kibfVSCqJiVJ5sTTnZN7yjv3EE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NGIk0XOf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NGIk0XOf" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B5149C2BCB0; Mon, 2 Mar 2026 22:59:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772492383; bh=3cDEmPbM/ZrYkcKE8GG467rShtzE9T3OP7Nd6C9sgls=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=NGIk0XOfImvJ63+ydhkZUIWm95xFTrUYfrTRezcqS5Zu1U7j0YfoWNW9hIrsSJNDR UUx7vpuhIbMOhniyftthpM4ccHZq1XQK638LFy8RSrbKDqpUZoHxphngrSjdrWp10s cMwFW/VvDhZMSr8UlCg9uoBhk00XEXIPH3lpM1MWZp13JXWsWx1yHMJQpUt6kWA0Cp i6/xrPfy30vxjT1hiXu2M65ZrV8uFmxuWuzF2dd/SbwLVsf01N8LsJkiZVVyKyTH2N muSZkE22I5nT7tjDM6iJ4wx+J14xttw1kjwzTFA7dR8YsxaLX3Hfg67MNx6hbrw/6f tqwEXeJexxv2Q== From: Mark Brown Date: Mon, 02 Mar 2026 22:53:19 +0000 Subject: [PATCH 4/8] arm64/sysreg: Update ID_AA64FPFR0_EL1 description to DDI0601 2025-12 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260302-arm64-dpisa-2025-v1-4-0855e7f41689@kernel.org> References: <20260302-arm64-dpisa-2025-v1-0-0855e7f41689@kernel.org> In-Reply-To: <20260302-arm64-dpisa-2025-v1-0-0855e7f41689@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-38bf1 X-Developer-Signature: v=1; a=openpgp-sha256; l=680; i=broonie@kernel.org; h=from:subject:message-id; bh=3cDEmPbM/ZrYkcKE8GG467rShtzE9T3OP7Nd6C9sgls=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBpphZRWfQt6vizNrWnnVqMTnzPDEZkuz/frnUdr UY98RUo1+KJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaaYWUQAKCRAk1otyXVSH 0Gp7B/wJu4xpUwsMSjlE4mku4Dmg5Mpyc/Zuh4NBayp2zw79vd9mqLm1M5HWOtELGEifFm5YFD7 CE9JGeuiqf9M7W2T6Yo0W2Tz263tQ+CbeVFX10tmzVF1TMQ0F0vOAv5aKkyaqNPWgzdYUZeqCsm 3d1qmGqBcTcWESKDSf3gqgim9XtqmPFz+An7dA6Gx1Ayf4xcAJZVN4c+rfn6UCRpzSmbgQekrAH wRicgSMJcrBf7vYLZFKyHTNy7B2k2spJwCfUEqZElc/PP57gnp5FlaXMXHIScM6tXt8/pYqQscM wAKOwSQZysQSjukS6tkL1YjJGfPnDHLpQR4kUrp2/tWJQFcs X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB The 2025 extensions add FEAT_F16MM and adjust some of the RES0 bits to be RAZ instead as a placeholder for future extensions. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 0d619c173c87..451ad312dc78 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1654,7 +1654,13 @@ UnsignedEnum 26 F8MM4 0b0 NI 0b1 IMP EndEnum -Res0 25:2 +Res0 25:16 +UnsignedEnum 15 F16MM2 + 0b0 NI + 0b1 IMP +EndEnum +Res0 14:8 +Raz 7:2 UnsignedEnum 1 F8E4M3 0b0 NI 0b1 IMP --=20 2.47.3 From nobody Tue Mar 3 03:38:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC67B30C602; Mon, 2 Mar 2026 22:59:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772492385; cv=none; b=OULB5ya91DMs/tTRV1GohCvHvzeWHN/wJGHj49sFh/Rz8DLgObSR8gvUlj+QnfvScTVQLUUmKHlHws2oWv/c+1xKbXxkGAgEj8erLGO759WKPRIBWP45jJnlmfJ/XhB8xxmHWBhU5ytu1AIrMPMmPaX0Q3tln+NEhuyHOiqQzRA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772492385; c=relaxed/simple; bh=gOV19KPEmG6qQjPLN5UxzzlwQ7VoUg11/tTDEq/4rOs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qKGklD0V1arZzCwXCVqYsHthtre6QjnVfufAT6NS6nxiyWD8GfUG1jEuTGUYnRsaKd0flC0WzQAHxwG81mELx+07lRZTdbmtB/hLOCC1pG7Jveddaq7KjSxBL/xgltEyYTErg9uxSvDAJCSMZZtIPzvtcvSJZBj7gVnlmmK7moU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XKSdAYZ6; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XKSdAYZ6" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C4B89C19423; Mon, 2 Mar 2026 22:59:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772492385; bh=gOV19KPEmG6qQjPLN5UxzzlwQ7VoUg11/tTDEq/4rOs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=XKSdAYZ6nP2hHf6ghUqepYMXUEKxLNCG8XH2xFzmt6MEVgrOb122213v2kZKfY+DH sWDf/ChUsjMgcKifFS1bLIQalKB4cXe/4THWbOvo1c48qncpbiTpL3q8BmVssU+yty BahPs/KkxMOKRuw04wZS7WY2wYZ665Rxsjg8twnK5zapPl/aOILFVJxyVC1FL9X+OP qCS1MByaE8C7wmDVcsWOGPryAhfBsw4g4VP5T7I6/cQBkRLqTEhOVbIjNkVZYPib7o x7QDjsAaPvoagn05jyRLDmGDQL5A7Wk02sxrsqXLx9k3FExL8FmILYxL6Zhg3366yK JYoDYy4CXrlYA== From: Mark Brown Date: Mon, 02 Mar 2026 22:53:20 +0000 Subject: [PATCH 5/8] arm64/sysreg: Update ID_AA64ZFR0_EL1 description to DDI0601 2025-12 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260302-arm64-dpisa-2025-v1-5-0855e7f41689@kernel.org> References: <20260302-arm64-dpisa-2025-v1-0-0855e7f41689@kernel.org> In-Reply-To: <20260302-arm64-dpisa-2025-v1-0-0855e7f41689@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-38bf1 X-Developer-Signature: v=1; a=openpgp-sha256; l=660; i=broonie@kernel.org; h=from:subject:message-id; bh=gOV19KPEmG6qQjPLN5UxzzlwQ7VoUg11/tTDEq/4rOs=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBpphZSiXUQ68jk0LvIbAWxVLEe80A/d0CuDUHsp uAP2Qs1K8qJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaaYWUgAKCRAk1otyXVSH 0HFSB/4qJmd27YIhHKwPZXYNA6Gld6nKMyla+tcVWxPLysOcB/tfjs5YE5mjQj6o2Yh1nQ1zBgZ Ht7To8zg4LDFn1X+BeL5YdZsoL65oiytQlvmEAdbr2VX6PLxhnCwINEoDObEajjRgwbatWDidFe W2JlwyAnhQKoT9H/VTODSL5VDk+YPNu18969M8rWllEyCicB9YUSAQHQ4wVaF48ZjcUZOvoTLj0 qY4HHfNnhwJ/cUU/ZOdHofM059BnI7at+TZCNw2jANNixlH5AxDsYtMiyi6vtkDOgezFjk4VrbZ hX+xsxEJLOGIMIfEnf7RtJ5VLkb1PFYuCFv4Al5TUmX92pTa X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB The 2025 extensions add FEAT_SVE2P3 and FEAT_SVE_B16MM. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 451ad312dc78..75b8644c4753 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1496,6 +1496,7 @@ UnsignedEnum 27:24 B16B16 0b0000 NI 0b0001 IMP 0b0010 BFSCALE + 0b0011 B16MM EndEnum UnsignedEnum 23:20 BF16 0b0000 NI @@ -1522,6 +1523,7 @@ UnsignedEnum 3:0 SVEver 0b0001 SVE2 0b0010 SVE2p1 0b0011 SVE2p2 + 0b0100 SVE2p3 EndEnum EndSysreg =20 --=20 2.47.3 From nobody Tue Mar 3 03:38:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 470873469FA; Mon, 2 Mar 2026 22:59:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772492388; cv=none; b=tsIP4/4kfyTlSeHEHOHWTESxt+57GG/HHXbYUpY4F9f4OTtm9TsD45vrLdB7ThNdNNkJOGutG6FHw3HRlj5ep8dGt/2QcBmGAoWf65CWMrmXjaA2A4W9GGSeoWKrk32iy/XTt0OEfOABwFxVtX+W0hA1s7nzd4ha/nJ94PRZb1Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772492388; c=relaxed/simple; bh=/lJ/fehI44WibZOvYodNtIelbVYTdzXsSQx64Pg7wIg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rr8y6Dg2MHccwfcuE/kD2Z7/BPL2kgEPHC1uNbPmG8QZfvKiwqPXUh8oWfpGY0yom6GSYuqvjUoyGCIZJZuNWI0sOIG3TMGZUpdWY9uLkm+9jXuEnebGvFZPke36gV98ZMzwy0WT3e6/8FQz4Leqct9xC6zPs41XXvEKPoUu8cM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bitJPtW3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bitJPtW3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D3DC2C2BCAF; Mon, 2 Mar 2026 22:59:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772492387; bh=/lJ/fehI44WibZOvYodNtIelbVYTdzXsSQx64Pg7wIg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=bitJPtW3XaXkfxh8HzFIJ+9wFYUPYCzc0GxlPNl5UJnXeIkyZm7QZR1CLId+5QWuC uh1T9uELA5K2i4rlfmJCjNJyVZp4bw7FuYQXiXYBTd7vedEc8pjv+iNQS8S+WuedBz EPX+SpA3P03WwmplXCsFAblyJXXdD0eoyy7srOCGr7MJhK7ZSKB9beTUFmI6D0Jczd m4LhtpKz6u24w7imvgitsKJ/7G64SYIzUiRTRFbJPryjd01v9hG6UAJdGaXFf8z7Yc h56gkBpSKXh9k8XqspUzBv2tkPomXwGVACakgOlxbRdr64LwszVZnr6lGBsOxLMP/t Ovk95MkqJa6ow== From: Mark Brown Date: Mon, 02 Mar 2026 22:53:21 +0000 Subject: [PATCH 6/8] arm64/sysreg: Update ID_AA64SMFR0_EL1 description to DDI0601 2025-12 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260302-arm64-dpisa-2025-v1-6-0855e7f41689@kernel.org> References: <20260302-arm64-dpisa-2025-v1-0-0855e7f41689@kernel.org> In-Reply-To: <20260302-arm64-dpisa-2025-v1-0-0855e7f41689@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-38bf1 X-Developer-Signature: v=1; a=openpgp-sha256; l=744; i=broonie@kernel.org; h=from:subject:message-id; bh=/lJ/fehI44WibZOvYodNtIelbVYTdzXsSQx64Pg7wIg=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBpphZS/+s06dtawLD+8AABMWAE3HxCNXtMFOPnG tVJRpBgfdGJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaaYWUgAKCRAk1otyXVSH 0A59B/0fe7ZQnlgvilKPjZLS9zvMj/v6kbyBjzEMHarYcE3Yrw+CBp9dAHRQ2egdswvoORI9F+9 kLdFofxVIdMrMyfmAXoGlRKnqsBJILOCf+9dwIuI1l3LjbGuA+/yHJ+k6KT1DIsgCigAA8UxnX2 UbfLrxztfNIHaBTMYF62v5IhOW4nRXi3kkbXeqBL1LXHYHsQnsckHQA7aLhQq0y+nItdDx3m3i4 421mE3exI6N1MP5q9qVk3lv6XeH2obZaUMBFuvXSrPXVmSOn3acS0qiS+9EEp2anER7TTDG2uCN Ppb3G9wiHzlhbjQrTG9ThHFYM73EYU7KcbJMAjeaOMyGHviU X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB The 2025 extensions add FEAT_SME2P3, including LUT6. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 75b8644c4753..eded0bee6ce4 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1532,7 +1532,11 @@ UnsignedEnum 63 FA64 0b0 NI 0b1 IMP EndEnum -Res0 62:61 +Res0 62 +UnsignedEnum 61 LUT6 + 0b0 NI + 0b1 IMP +EndEnum UnsignedEnum 60 LUTv2 0b0 NI 0b1 IMP @@ -1542,6 +1546,7 @@ UnsignedEnum 59:56 SMEver 0b0001 SME2 0b0010 SME2p1 0b0011 SME2p2 + 0b0100 SME2p3 EndEnum UnsignedEnum 55:52 I16I64 0b0000 NI --=20 2.47.3 From nobody Tue Mar 3 03:38:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3254346AD3; Mon, 2 Mar 2026 22:59:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772492389; cv=none; b=UnsxSDYXTx/w5g6Vn4NughX5c4bUsdmpcTvyDjFHrBJe2Jw84kMvPStxzeyf+57xC/djE3KsrrEr9poUjVoXbaMNCuzAFsA2agEjuf2EjAr90W2mduzpuCSzBqHy2CZCtWWneQqgDWe7QliCB6A3ASVtHdamTtlyd250Ys9U8Sk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772492389; c=relaxed/simple; bh=bNGXa11VnH1NvzRGc4Tl07oCGUSosAZoawn/QPFfidU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JgaltHw0CrIm/nxkLVC+DGQ0uipSHrf8P88wcTdvY2Z1HUVP5cq6Gx7hxLPu7GreXmTgjMkEFf5bfT/+QNftDV0GKFCq2B5D99yqw/HjPkdQFzcHKqh2gKMWa+3Rakug8z4NJW9ux/srh8OWSsOkM67IPa+sOl89tqwULB5putg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dYNn2v/X; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dYNn2v/X" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E0880C19425; Mon, 2 Mar 2026 22:59:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772492389; bh=bNGXa11VnH1NvzRGc4Tl07oCGUSosAZoawn/QPFfidU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=dYNn2v/X/movuo2GInv/rlYhzJ7YyUo6VCNmNDc2j353VBWhVXqd/vA23dfQiAv3p zOsfZAFNmULMKDxzaDvG35r1xmRf/P/nEV1AYg/PtfBelIpWn5hbu3lfIsl0tO9xRj ayx6WONPeFfFe/EImzv4YSRuaN0tt3FO4IGpFCdjidfxHSMLuG1CzjbftMJXycyeBc /mYThkpA1qj4QSpft7Etw8y0XT1b25QCENLT8FHXPKyRooJXPPbBO29vDeI2v6FVNd GWs0R2Xt4CiVsCkd3Yf0nkVjSb1o04al6z5UY2Grv/N3MTnHabp84D4uO5yF9VG3DT gsRQ1Uodr4gJQ== From: Mark Brown Date: Mon, 02 Mar 2026 22:53:22 +0000 Subject: [PATCH 7/8] arm64/cpufeature: Define hwcaps for 2025 dpISA features Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260302-arm64-dpisa-2025-v1-7-0855e7f41689@kernel.org> References: <20260302-arm64-dpisa-2025-v1-0-0855e7f41689@kernel.org> In-Reply-To: <20260302-arm64-dpisa-2025-v1-0-0855e7f41689@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-38bf1 X-Developer-Signature: v=1; a=openpgp-sha256; l=8779; i=broonie@kernel.org; h=from:subject:message-id; bh=bNGXa11VnH1NvzRGc4Tl07oCGUSosAZoawn/QPFfidU=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBpphZT6BGuSdPWhShOCQfApymkYPVM9/1nMpvOI /voBV79D5uJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaaYWUwAKCRAk1otyXVSH 0HAWB/4sTjyyXZAiy/f3AfdhASKKHnoyTEFUklFbLZqj3WKyBKUvkXX8EDhwpCC6KSzIwgipy5I K9AKuQ/pC12Ozgf93CPRkYHfEr+Z7Q/QQrUO8ZuYz9hUHEGjkPvUyHtLIF2hPQDZpKSQ0ffDs9z d+A5oNXvqdEFJnIErPSg/a8pH9jGm1u79wnxnewJW92/mlzlYnorOKR9kVNSMU4Ex4s7udRNNdi 4sGYhsZAovJOXi9UKq28QhTbb2R+mpIOVcEIk3LQ33lWIbcUMEcnWK3vlHuGjSiLJXaJpwm68mT 9wWUsXp+CmItSbkGrXkzm5fT6eoSaRGvHpuK8J9j02wT4Bw3 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB The features added by the 2025 dpISA are all straightforward instruction only features so there is no state to manage, we can just expose hwcaps to let userspace know they are available. F16MM is slightly odd in that the feature is FEAT_F16MM but it is discovered via ID_AA64FPFR0_EL1.F16MM2. We follow the feature name. Signed-off-by: Mark Brown --- Documentation/arch/arm64/elf_hwcaps.rst | 24 ++++++++++++++++++++++++ arch/arm64/include/uapi/asm/hwcap.h | 8 ++++++++ arch/arm64/kernel/cpufeature.c | 11 +++++++++++ arch/arm64/kernel/cpuinfo.c | 8 ++++++++ 4 files changed, 51 insertions(+) diff --git a/Documentation/arch/arm64/elf_hwcaps.rst b/Documentation/arch/a= rm64/elf_hwcaps.rst index 97315ae6c0da..ea9215d65481 100644 --- a/Documentation/arch/arm64/elf_hwcaps.rst +++ b/Documentation/arch/arm64/elf_hwcaps.rst @@ -451,6 +451,30 @@ HWCAP3_LS64 of CPU. User should only use ld64b/st64b on supported target (device) memory location, otherwise fallback to the non-atomic alternatives. =20 +HWCAP3_SVE_B16MM + Functionality implied by ID_AA64ZFR0_EL1.B16B16 =3D=3D 0b0011 + +HWCAP3_SVE2P3 + Functionality implied by ID_AA64ZFR0_EL1.SVEver =3D=3D 0b0100 + +HWCAP3_SME_LUT6 + Functionality implied by ID_AA64SMFR0_EL1.LUT6 =3D=3D 0b1 + +HWCAP3_SME2P3 + Functionality implied by ID_AA64SMFR0_EL1.SMEver =3D=3D 0b0100 + +HWCAP3_F16MM + Functionality implied by ID_AA64FPFR0_EL1.F16MM2 =3D=3D 0b1 + +HWCAP3_F16F32DOT + Functionality implied by ID_AA64ISAR0_EL1.FHM =3D=3D 0b0010 + +HWCAP3_F16F32MM + Functionality implied by ID_AA64ISAR0_EL1.FHM =3D=3D 0b0011 + +HWCAP3_LUT6 + Functionality implied by ID_AA64ISAR2_EL1.LUT =3D=3D 0b0010 + =20 4. Unused AT_HWCAP bits ----------------------- diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/= asm/hwcap.h index 06f83ca8de56..a48aee07a54a 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -147,5 +147,13 @@ #define HWCAP3_MTE_STORE_ONLY (1UL << 1) #define HWCAP3_LSFE (1UL << 2) #define HWCAP3_LS64 (1UL << 3) +#define HWCAP3_SVE_B16MM (1UL << 4) +#define HWCAP3_SVE2P3 (1UL << 5) +#define HWCAP3_SME_LUT6 (1UL << 6) +#define HWCAP3_SME2P3 (1UL << 7) +#define HWCAP3_F16MM (1UL << 8) +#define HWCAP3_F16F32DOT (1UL << 9) +#define HWCAP3_F16F32MM (1UL << 10) +#define HWCAP3_LUT6 (1UL << 11) =20 #endif /* _UAPI__ASM_HWCAP_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index c31f8e17732a..a26cef210b08 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -361,6 +361,8 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = =3D { static const struct arm64_ftr_bits ftr_id_aa64smfr0[] =3D { ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUT6_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), @@ -415,6 +417,7 @@ static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = =3D { ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2= _SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM8= _SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM4= _SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F16MM= 2_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M= 3_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M= 2_SHIFT, 1, 0), ARM64_FTR_END, @@ -3265,6 +3268,8 @@ static const struct arm64_cpu_capabilities arm64_elf_= hwcaps[] =3D { HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4), HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), + HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, F16F32DOT, CAP_HWCAP, KERNEL_HWCAP_F16F3= 2DOT), + HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, F16F32MM, CAP_HWCAP, KERNEL_HWCAP_F16F32= MM), HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM), HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG), @@ -3290,11 +3295,13 @@ static const struct arm64_cpu_capabilities arm64_el= f_hwcaps[] =3D { HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), HWCAP_CAP(ID_AA64ISAR1_EL1, LS64, LS64, CAP_HWCAP, KERNEL_HWCAP_LS64), HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT), + HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, LUT6, CAP_HWCAP, KERNEL_HWCAP_LUT6), HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINM= AX), HWCAP_CAP(ID_AA64ISAR3_EL1, LSFE, IMP, CAP_HWCAP, KERNEL_HWCAP_LSFE), HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), #ifdef CONFIG_ARM64_SVE HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), + HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p3, CAP_= HWCAP, KERNEL_HWCAP_SVE2P3), HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p2, CAP_= HWCAP, KERNEL_HWCAP_SVE2P2), HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_= HWCAP, KERNEL_HWCAP_SVE2P1), HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HW= CAP, KERNEL_HWCAP_SVE2), @@ -3304,6 +3311,7 @@ static const struct arm64_cpu_capabilities arm64_elf_= hwcaps[] =3D { HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HW= CAP, KERNEL_HWCAP_SVEBITPERM), HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWC= AP, KERNEL_HWCAP_SVE_B16B16), HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, BFSCALE, CAP= _HWCAP, KERNEL_HWCAP_SVE_BFSCALE), + HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, B16MM, CAP_H= WCAP, KERNEL_HWCAP_SVE_B16MM), HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP= , KERNEL_HWCAP_SVEBF16), HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWC= AP, KERNEL_HWCAP_SVE_EBF16), HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP= , KERNEL_HWCAP_SVESHA3), @@ -3343,7 +3351,9 @@ static const struct arm64_cpu_capabilities arm64_elf_= hwcaps[] =3D { #ifdef CONFIG_ARM64_SME HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCA= P, KERNEL_HWCAP_SME_FA64), + HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, LUT6, IMP, CAP_HWCA= P, KERNEL_HWCAP_SME_LUT6), HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWC= AP, KERNEL_HWCAP_SME_LUTV2), + HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p3, CAP= _HWCAP, KERNEL_HWCAP_SME2P3), HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p2, CAP= _HWCAP, KERNEL_HWCAP_SME2P2), HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP= _HWCAP, KERNEL_HWCAP_SME2P1), HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2, CAP_H= WCAP, KERNEL_HWCAP_SME2), @@ -3374,6 +3384,7 @@ static const struct arm64_cpu_capabilities arm64_elf_= hwcaps[] =3D { HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2), HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM8, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM8), HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM4), + HWCAP_CAP(ID_AA64FPFR0_EL1, F16MM2, IMP, CAP_HWCAP, KERNEL_HWCAP_F16MM), HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3), HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2), #ifdef CONFIG_ARM64_POE diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 6149bc91251d..1967ef4e25c8 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -164,6 +164,14 @@ static const char *const hwcap_str[] =3D { [KERNEL_HWCAP_MTE_FAR] =3D "mtefar", [KERNEL_HWCAP_MTE_STORE_ONLY] =3D "mtestoreonly", [KERNEL_HWCAP_LSFE] =3D "lsfe", + [KERNEL_HWCAP_SVE_B16MM] =3D "sveb16mm", + [KERNEL_HWCAP_SVE2P3] =3D "sve2p3", + [KERNEL_HWCAP_SME_LUT6] =3D "smelut6", + [KERNEL_HWCAP_SME2P3] =3D "sme2p3", + [KERNEL_HWCAP_F16MM] =3D "f16mm", + [KERNEL_HWCAP_F16F32DOT] =3D "f16f32dot", + [KERNEL_HWCAP_F16F32MM] =3D "f16f32mm", + [KERNEL_HWCAP_LUT6] =3D "lut6", }; =20 #ifdef CONFIG_COMPAT --=20 2.47.3 From nobody Tue Mar 3 03:38:10 2026 Received: from smtp.kernel.org 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Q/fZwpswTbuHKvcuqZLHYo5lbXvlRfGUKwlPHSqq4RD0SIa66zB0BpQQ7uNZR/p1T/ ndnENqy/uj4M5uAPvdh20y84YoD1vVB2Jj5/GDMepR7SYWguKEEe8YqlMdngjacOwY e/FMKY5lKyC2g== From: Mark Brown Date: Mon, 02 Mar 2026 22:53:23 +0000 Subject: [PATCH 8/8] kselftest/arm64: Add 2025 dpISA coverage to hwcaps Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260302-arm64-dpisa-2025-v1-8-0855e7f41689@kernel.org> References: <20260302-arm64-dpisa-2025-v1-0-0855e7f41689@kernel.org> In-Reply-To: <20260302-arm64-dpisa-2025-v1-0-0855e7f41689@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-38bf1 X-Developer-Signature: v=1; a=openpgp-sha256; l=5080; i=broonie@kernel.org; h=from:subject:message-id; bh=k28xlv3oqLuHGwNR19fusA0RoHT8v5EmRNzuxn2QGlU=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBpphZU7oC8QDO2MV5R+ciPpTV9RuVrZ00VY0ySE QFZ8dwzDumJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaaYWVAAKCRAk1otyXVSH 0AgWB/0W2H9qyDm1/Hh2fBseSJgT62ZDZcnq6WbxOSLC7jcizLb+9K9rZI/Um4UFrt2YsI0dK+S TqKgp71KDtpFYqoRkPQuyBMKrXLZdPnsD5zhfDHCz2ny9clsi3hpPW2tkNYsyCCtUCtwA7LVqUL wF+CXVMWMgtEU2A50W5gJva8K+tVsWvc+rpDxdLaE/VOkZnFPPiBC9QRICMidRjbAdPPXVK0DUE EMorjxB9OAmwtbs2SB/hSRI0qs+j8mVj3XkbHHN9KpsYUGjpKrvouEaY6m1vsqZ0TDZihFKQY4l SMkDSHu7vbU2Urzwr0JWcHSKrYdU6ENdBP+/k/9iESMVyMJk X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Add coverage of the new hwcaps to the test program, encodings cross checked against LLVM 22. Signed-off-by: Mark Brown --- tools/testing/selftests/arm64/abi/hwcap.c | 116 ++++++++++++++++++++++++++= ++++ 1 file changed, 116 insertions(+) diff --git a/tools/testing/selftests/arm64/abi/hwcap.c b/tools/testing/self= tests/arm64/abi/hwcap.c index 9d2df1f3e6bb..fbb5563ac7ac 100644 --- a/tools/testing/selftests/arm64/abi/hwcap.c +++ b/tools/testing/selftests/arm64/abi/hwcap.c @@ -107,6 +107,24 @@ static void f8mm8_sigill(void) asm volatile(".inst 0x6e80ec00"); } =20 +static void f16f32dot_sigill(void) +{ + /* FDOT V0.2S, V0.4H, V0.2H[0] */ + asm volatile(".inst 0xf409000"); +} + +static void f16f32mm_sigill(void) +{ + /* FMMLA V0.4S, V0.8H, V0.8H */ + asm volatile(".inst 0x4e40ec00"); +} + +static void f16mm_sigill(void) +{ + /* FMMLA V0.8H, V0.8H, V0.8H */ + asm volatile(".inst 0x4ec0ec00"); +} + static void faminmax_sigill(void) { /* FAMIN V0.4H, V0.4H, V0.4H */ @@ -190,6 +208,12 @@ static void lut_sigill(void) asm volatile(".inst 0x4e801000"); } =20 +static void lut6_sigill(void) +{ + /* LUTI6 Z0.H, { Z0.H, Z1.H }, Z0[0] */ + asm volatile(".inst 0x4560ac00"); +} + static void mops_sigill(void) { char dst[1], src[1]; @@ -281,6 +305,18 @@ static void sme2p2_sigill(void) asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); } =20 +static void sme2p3_sigill(void) +{ + /* SMSTART SM */ + asm volatile("msr S0_3_C4_C3_3, xzr" : : : ); + + /* ADDQP Z0.B, Z0.B, Z0.B */ + asm volatile(".inst 0x4207800" : : : "z0"); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + static void sme_aes_sigill(void) { /* SMSTART SM */ @@ -377,6 +413,18 @@ static void smef8f32_sigill(void) asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); } =20 +static void smelut6_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* LUTI6 { Z0.B-Z3.B }, ZT0, { Z0-Z2 } */ + asm volatile(".inst 0xc08a0000" : : : ); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + static void smelutv2_sigill(void) { /* SMSTART */ @@ -485,6 +533,12 @@ static void sve2p2_sigill(void) asm volatile(".inst 0x4cea000" : : : "z0"); } =20 +static void sve2p3_sigill(void) +{ + /* ADDQP Z0.B, Z0.B, Z0.B */ + asm volatile(".inst 0x4207800" : : : "z0"); +} + static void sveaes_sigill(void) { /* AESD z0.b, z0.b, z0.b */ @@ -503,6 +557,12 @@ static void sveb16b16_sigill(void) asm volatile(".inst 0x65000000" : : : ); } =20 +static void sveb16mm_sigill(void) +{ + /* BFMMLA Z0.H, Z0.H, Z0.H */ + asm volatile(".inst 0x64e0e000" : : : ); +} + static void svebfscale_sigill(void) { /* BFSCALE Z0.H, P0/M, Z0.H, Z0.H */ @@ -728,6 +788,27 @@ static const struct hwcap_data { .cpuinfo =3D "f8mm4", .sigill_fn =3D f8mm4_sigill, }, + { + .name =3D "F16MM", + .at_hwcap =3D AT_HWCAP3, + .hwcap_bit =3D HWCAP3_F16MM, + .cpuinfo =3D "f16mm", + .sigill_fn =3D f16mm_sigill, + }, + { + .name =3D "F16F32DOT", + .at_hwcap =3D AT_HWCAP3, + .hwcap_bit =3D HWCAP3_F16F32DOT, + .cpuinfo =3D "f16f32dot", + .sigill_fn =3D f16f32dot_sigill, + }, + { + .name =3D "F16F32MM", + .at_hwcap =3D AT_HWCAP3, + .hwcap_bit =3D HWCAP3_F16F32MM, + .cpuinfo =3D "f16f32mm", + .sigill_fn =3D f16f32mm_sigill, + }, { .name =3D "FAMINMAX", .at_hwcap =3D AT_HWCAP2, @@ -830,6 +911,13 @@ static const struct hwcap_data { .cpuinfo =3D "lut", .sigill_fn =3D lut_sigill, }, + { + .name =3D "LUT6", + .at_hwcap =3D AT_HWCAP3, + .hwcap_bit =3D HWCAP3_LUT6, + .cpuinfo =3D "lut6", + .sigill_fn =3D lut6_sigill, + }, { .name =3D "MOPS", .at_hwcap =3D AT_HWCAP2, @@ -917,6 +1005,13 @@ static const struct hwcap_data { .cpuinfo =3D "sme2p2", .sigill_fn =3D sme2p2_sigill, }, + { + .name =3D "SME 2.3", + .at_hwcap =3D AT_HWCAP3, + .hwcap_bit =3D HWCAP3_SME2P3, + .cpuinfo =3D "sme2p3", + .sigill_fn =3D sme2p3_sigill, + }, { .name =3D "SME AES", .at_hwcap =3D AT_HWCAP, @@ -966,6 +1061,13 @@ static const struct hwcap_data { .cpuinfo =3D "smef8f32", .sigill_fn =3D smef8f32_sigill, }, + { + .name =3D "SME LUT6", + .at_hwcap =3D AT_HWCAP3, + .hwcap_bit =3D HWCAP3_SME_LUT6, + .cpuinfo =3D "smelut6", + .sigill_fn =3D smelut6_sigill, + }, { .name =3D "SME LUTV2", .at_hwcap =3D AT_HWCAP2, @@ -1051,6 +1153,13 @@ static const struct hwcap_data { .cpuinfo =3D "sve2p2", .sigill_fn =3D sve2p2_sigill, }, + { + .name =3D "SVE 2.3", + .at_hwcap =3D AT_HWCAP3, + .hwcap_bit =3D HWCAP3_SVE2P3, + .cpuinfo =3D "sve2p3", + .sigill_fn =3D sve2p3_sigill, + }, { .name =3D "SVE AES", .at_hwcap =3D AT_HWCAP2, @@ -1065,6 +1174,13 @@ static const struct hwcap_data { .cpuinfo =3D "sveaes2", .sigill_fn =3D sveaes2_sigill, }, + { + .name =3D "SVE B16MM", + .at_hwcap =3D AT_HWCAP3, + .hwcap_bit =3D HWCAP3_SVE_B16MM, + .cpuinfo =3D "sveb16mm", + .sigill_fn =3D sveb16mm_sigill, + }, { .name =3D "SVE BFSCALE", .at_hwcap =3D AT_HWCAP, --=20 2.47.3