From nobody Thu Apr 16 08:34:48 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012063.outbound.protection.outlook.com [52.101.43.63]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E95730F7E2; Sun, 1 Mar 2026 14:04:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.43.63 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772373853; cv=fail; b=LekG6E8Zd0fngsZS+NyAauHHdtIHA9rPRC9xhgz83jzJZbJQNal5QR5hAA9r/Gwn5cLGcfEs7jrFiV3ZdDCWQuNSbbBjiFAt1+U35AveyITJ/X74AyQ+zh0iQoQ0TdZa+yyBgQAt1oWLR57QR3mmvT3u8QhK0aYIWGcrJ+n3TDk= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772373853; c=relaxed/simple; bh=ZRTD88jIp7srX0mvY31nU+UJAtiS4XSyrE3oe8psdZI=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=KHAY0I2W+9fmVV8qhI80yE+cXQvbF7exKCH0v7e2+hx9sHWUR30EYr76ho4L6ncXtv7hpdLAzdb4cjNBchvjpPe+69WYCjroSSWHK5rhGiKaOsJ89t2QylDrK2HUuGI7/MYt/zXcvoZog1MzLgJlvM8a84G1F2gthpKEdJk+UOA= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=h8FJWwRV; arc=fail smtp.client-ip=52.101.43.63 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="h8FJWwRV" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=puzINy0SFmUbzlhgzwLxrHDu+3GV6rGRJde3/mtEXWnayLabBbBObiKJE02sub2WBOTSjx3trDaZ4TNghCXVAzGvG3im/iNRbg22RPbX2RHZnH16VBCuYDVaP9sCmo33HbYefyGgY71XIftooCRrnolAIXeEldIBkpDvdMUm9B8daszaM4fyCMfUWwKiJ9orT5aygQd8BVMhh1Ww1DQotsDO/+AkASaM/6pUdJaraTKofMbNzfvYOEtY6Bj6cFQFUc0p1JdmC5kJXaCsAHDY96gwNrxSYqOPwGzP5xRzNukdrUhyFqJWYm8OPLOytAlBaohZ6TxVv9wiqkK8CXMmnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=k0BBaOGVayVHPRxD95cED7HkcT8xlGsqKNcdDfJDDPs=; b=gonHpKlOVmGyHoyK4O8eNEfjObX24XaS1s2NiyzmRcjmceQDe4emlTyWy6+5aIG+zXuCSfRwOAtY6GiYD07Kj3hBA0g4oGGgo9rOugyrDZQuXUzEq+zASu0UtFSD8olPNQsCc7NTDaJLc7KsiXXmjhWaDMDlYPmMt9ka+2SA9Zebwb0y1bB09JP8YNnYdB+dmY4NS/pbRfVTo6N4OyiwA93uP9a8yQQx4k7I376cczvO4N/aXGvnnjljYp63x2EEsRlPTnVHpJQ8i/ZTyr5KN3jxA+f3Okps9gnIL9FcH255PEDSIi8M5nogJcd+t/Pchfcy+XXz5yDqFkYBM//CzA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=k0BBaOGVayVHPRxD95cED7HkcT8xlGsqKNcdDfJDDPs=; b=h8FJWwRVQDJqlRjqpshOa1MgI5pTgVC+I6wR172zyhw82qYKswiyRV9qtrAfUG6Jt0cF2QTy9gGLc3ZTjJDwcv8pLJOTCgUVMYVhKe6tYWNUz8qAUQEKJ0tC9WgyYktf6up4cEWzrm8dt7j+R5uYOKK1bjlS/nwEyy3DJTfHFRPp//PWoiKH1X8SV/FCLhOluzSYOcgCg2irjSESr4P38x1Bf5VVv5LifZOAaW7rX4BV4bssBcee4GyHgpMsdZb8A+JJVVWn4vTUIf/NrnUXQrQOTP/yRy2CaMslG5NrsfX0KTldSwp1uSUO1BAWLvvMXi4AskHlUFq4bcO4KN4wlw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) by DS0PR12MB6632.namprd12.prod.outlook.com (2603:10b6:8:d0::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.19; Sun, 1 Mar 2026 14:04:03 +0000 Received: from CH2PR12MB3990.namprd12.prod.outlook.com ([fe80::7de1:4fe5:8ead:5989]) by CH2PR12MB3990.namprd12.prod.outlook.com ([fe80::7de1:4fe5:8ead:5989%6]) with mapi id 15.20.9654.020; Sun, 1 Mar 2026 14:04:03 +0000 From: Alexandre Courbot Date: Sun, 01 Mar 2026 23:03:44 +0900 Subject: [PATCH v10 01/10] gpu: nova-core: create falcon firmware DMA objects lazily Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260301-turing_prep-v10-1-dde5ee437c60@nvidia.com> References: <20260301-turing_prep-v10-0-dde5ee437c60@nvidia.com> In-Reply-To: <20260301-turing_prep-v10-0-dde5ee437c60@nvidia.com> To: Danilo Krummrich , Alexandre Courbot , Alice Ryhl , David Airlie , Simona Vetter Cc: John Hubbard , Alistair Popple , Joel Fernandes , Timur Tabi , Edwin Peer , Eliot Courtney , nouveau@lists.freedesktop.org, rust-for-linux@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-ClientProxiedBy: TYCP286CA0005.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:26c::9) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|DS0PR12MB6632:EE_ X-MS-Office365-Filtering-Correlation-Id: 91b9d19f-23f2-48ef-5bc1-08de779b64d9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|366016|10070799003; X-Microsoft-Antispam-Message-Info: zlKLgxjdJwmddbb1LGh+40w4XdNsMAN3Z0l9oMFsiRK2fsotK1mxKky0O9z690n14MEpS7K0Y/XzY4if58+j4VB42exBqtAIuY0jLsfsn3MYza28P6VxXs5ZTn2AahkFJIC/L9W4pouHrGBBzsPUdY3QkTf8e0zoetqBXaZ2Z/pNdC+ROoGq9NN6Xt61m45P8KFAOqs7CbG8cv2s4xGpm/9kO8prCS83qKp8VUVDBzRpVVea7jaLIox/Q31+YfSU5bmd3fgcEnp/PeIPx1YxUa+DXch55CuoXieHVWKNvMnuvWW/Ubqi07qFcvPv158MC0J02tZt9lraHD+PYlQ8eiV1bdpPOuFQwoXX0V4nfUEuON/PVhIL+uN0yjDeeaAhvw2/sJ1hFHibdMBtYST09rH/kcv+nkRcqhYmmSWOh18ydrcEIuQfVLtj26L9ER4Au1XcXw43ZaFHZ7p8Fhle4r+RgYdwwFNxEHaHw6iVJ7+8Z/iipGZF0K0awd9rRE/hZ8whiwo+JuBvo+fVbADdFFbHcEGKJ3JtIx28KcNNoqKfmQZVMmcuUF1FWeqCGEfcOQ1lsLCYSYHHmt7PqHcNXvJ8ivPTtqF7E6D1bamvBcL/U7NQQu/U/0utD57o6VReQ4iQTb+/2WBQAPg+kRU8dXgUD3F/vhCloY19p1mARzBSCHm+qsO/iSlKIfUgF5tz8imSLuvIv/jFzlp3Y2oDM8VvguNJUHPQRqR5qITIq14= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CH2PR12MB3990.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(366016)(10070799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 2 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?WUNYaW9ZL01ZMThCN1ZzT3cwRDJrQXNzVjVLZE42N25YVVZRTnZsWnpBTGVW?= =?utf-8?B?NWJ5SGhvTEZNUDJWVHR6VGdsWWQxVkVvTkpHbm1JY0hya1hQemlKNzE4U0tl?= =?utf-8?B?UzhqdWx4NFBTeGw0d2QxNzlFQ0hESUMxUW8yQlpFd040YXY2cTkvWUFQVmpy?= =?utf-8?B?WUlUakRlNy9wWXdjZENvbFN6YmlFOXpHVWovV1BjaVdkZlZrQVFFNlhLYVdp?= =?utf-8?B?WjJpcS9Ddlp0SEhJSFdlM0t3Zm4zRENoS2h5NG9adUxBM1hBdm4ybEZDVEdN?= =?utf-8?B?bVNLbXErUSttUkxJK2lWYVZwVmhoUm1BbWFwWkpzYThsTDJPcXUvanU2UnB2?= =?utf-8?B?QmhDdE44dmR6MzQ1c2dTTFVUcFNqOEh4ZVZaV3pwdTJqZXFZTXhtQmdXQU9X?= =?utf-8?B?RVRHdTdGMmhnTllDTmcwMUI2cGI2bk84bExFRzd0ZmpCMG54bGpZbjBhdzdo?= =?utf-8?B?bTFCNlJha1RqcThXSnAvb0Z5QzBveTZqMUk2K0lRekl5UzJPMnhtSmh2cE1Z?= =?utf-8?B?R1htY1BRZE40SnVPMS95azdnbm9JcE5Ramg2eXd5MUJKMk5scExCZkg1TXVz?= =?utf-8?B?dStqb1Z1bTIrSFFyS29KOHRVV0tBYUtJZTRDWHphcDNlanEvMFRFSHplZnZ2?= =?utf-8?B?M2RiWjMwZnErNEpWZDRmMEl6UHVoUkdjNGNkZm1nenV4NFVLS2pPQlUxT0Zv?= =?utf-8?B?RXFwL25qMG5pd0FMWEZQZmJ6VW1pZGVENFd2WUI1SXFjc3VTQi83Qkt2Q0M1?= =?utf-8?B?VHhKbUVPQTBhdVdTazltRGRNQzNreWcvM1MwTGVldWVKc25ZUnNyd1dxM3hm?= =?utf-8?B?M0Jyakg0eUVKc0hKTkM5U0hBNWd2MGl1MlJDUDlHYUo3N05pWCtURjVTYWFG?= =?utf-8?B?cDlSbGVQc0p5Vm5obFpRWFFra3QxZ01LT1g2MEI4WThiYWNJUVpyTlpRWVpt?= =?utf-8?B?L2N5Rm9WZ2xKbTVFc05PNTNWUUI4SGdESlBxRnBGQVNUd09GNmZvM2FWVm44?= =?utf-8?B?QWcvelAyWUwxYmo1Rm52MEFWbVB4K2xaMWI2U0xQRlE5RFdRRmNhbFdCbExV?= =?utf-8?B?enMwaC9SZlM4b0kvU3JzYTBybWUvdndrSkZyYzNRMC9pVlpaUFBiSTRCWGR2?= =?utf-8?B?R0ZWN2pQNzRNL09NanZSWlhtNnlGR25pN00zdUNyMXEzYUJqYXNmVk9HelYv?= =?utf-8?B?RUNaMVlUU2NVeGs4T0RSdGxBY09iUmEvcHpFNTVmanR4U05vU2h2aHZndENX?= =?utf-8?B?MnV4RmxCNHNVSVU3ejg3dGs0WWJNeHY5TFF5UmQvZ1R5eHZZVmxXS0ExZnpn?= =?utf-8?B?V2NoZUpZV3ZPVWpNbVAxaG5EWDZ5YURIWEJ0U29EcHpNQXA3Wmx6VDkydXJU?= =?utf-8?B?cDEvb1E5KzlFaDZRb09CUFQrbCtWSUMzbVN3eTlweEp5cm1tN09ya3dtZ1Nk?= =?utf-8?B?cFRaMUt1WDQwMmhLaWhoTGY5YVZ0dUpHcVBiVmw3VVgzZ093VC9kS1N0Zk9n?= =?utf-8?B?ZGJ2bzZSVlg3dmFnL1VYZ1Q5Yy9OcWJoQ3lleDR3TVRrTFl4UUQ3OWZaWDM4?= =?utf-8?B?YzlSRENXT0VFQ3E1SDBGTlllbWhKT1F1TU5WOVNydjBPT1N0dnFNdi9RR0du?= =?utf-8?B?ZE5Wb3BIVkhjcEZ0Z0pnVDNZWHUxamF3ditUSHFXZHhWZm1FY2t1N3RtMFBQ?= =?utf-8?B?ODVWeHUwS2pTTXdhZXhGdzBZZ3REWTNGZWYrNVBzYkJRWVlUV3diM1JWclNl?= =?utf-8?B?SVZDb0FIM0k3emgydDRDNmZjcUhKcXduZXpNSXMwZ2NoOXZtTGZPRzNBMGxF?= =?utf-8?B?Zy9SQTF6V1FXVXV2NkxEdlRnWUdZVXJFbXlSMWZCUlQ2dzhzQlZCbCtJOGVZ?= =?utf-8?B?T2J4RjBYa1hDZUlWUkFzWUpQdEh0OVdtWFdueDk5TVI4RmcrVW90TkZuSDZt?= =?utf-8?B?UVJReXRzcVRWQmZZWGxnZkRDUFMwZnA1NmpGZmdiem52blF3cEk2UFdQcEQ4?= =?utf-8?B?QTJ6bUxkQlQxRjEzMUNGUkhQU3RFaENKZU94SWcrK1NDeENNczc0c3ZrSFZl?= =?utf-8?B?VjZ0eWU4MVhGS2pVT2M3V2RLL2NkNGVTaXAxU0FrTStFQXZvSzI5ZVFrOTNn?= =?utf-8?B?Y2NUOHNDQlJUSkovdzUxYUdqL2JMcXFWSXJ5WXBjNmxKN1ZOUG9IVUZKUHU1?= =?utf-8?B?TFBMWUpwd05EK2Q3TmNSbzVORXpLUEhVbGpQcTMydmlzdW5jczlxL1U0WVVT?= =?utf-8?B?Qm1UQUx0L3RsaHVwUCt2cEJXK2JzanVNTGNYdEloeXBTU0NPak9iNTFxUzgx?= =?utf-8?B?U0MyZjJtdGpGL1BnMmoxdDczVW5YZWowZ0dkVHFNTkhwbTVJSjZ5dmZtVk1P?= =?utf-8?Q?Esyzi9g/60wKqyOtE+n8y+QVVfOmyXU1ngHi3vHVU9Wry?= X-MS-Exchange-AntiSpam-MessageData-1: mxtBP5StKzovsA== X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 91b9d19f-23f2-48ef-5bc1-08de779b64d9 X-MS-Exchange-CrossTenant-AuthSource: CH2PR12MB3990.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2026 14:04:03.0471 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 3FDua+MK9OoP5zGKOyR9W++b2lZP/YSkrU60qmr6pgwl/1bcLHMPBFCnIE7A6EAbK6UVnRYDK+JGfeJ8x7KgNw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6632 When DMA was the only loading option for falcon firmwares, we decided to store them in DMA objects as soon as they were loaded from disk and patch them in-place to avoid having to do an extra copy. This decision complicates the PIO loading patch considerably, and actually does not even stand on its own when put into perspective with the fact that it requires 8 unsafe statements in the code that wouldn't exist if we stored the firmware into a `KVVec` and copied it into a DMA object at the last minute. The cost of the copy is, as can be expected, imperceptible at runtime. Thus, switch to a lazy DMA object creation model and simplify our code a bit. This will also have the nice side-effect of being more fit for PIO loading. Signed-off-by: Alexandre Courbot Acked-by: Danilo Krummrich Reviewed-by: Eliot Courtney --- drivers/gpu/nova-core/falcon.rs | 57 ++++++++++++------- drivers/gpu/nova-core/firmware.rs | 38 ++++++------- drivers/gpu/nova-core/firmware/booter.rs | 33 +++++------ drivers/gpu/nova-core/firmware/fwsec.rs | 96 ++++++++++------------------= ---- drivers/gpu/nova-core/gsp/boot.rs | 2 +- 5 files changed, 99 insertions(+), 127 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index 37bfee1d0949..8d444cf9d55c 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -2,12 +2,13 @@ =20 //! Falcon microprocessor base support =20 -use core::ops::Deref; - use hal::FalconHal; =20 use kernel::{ - device, + device::{ + self, + Device, // + }, dma::{ DmaAddress, DmaMask, // @@ -15,9 +16,7 @@ io::poll::read_poll_timeout, prelude::*, sync::aref::ARef, - time::{ - Delta, // - }, + time::Delta, }; =20 use crate::{ @@ -351,6 +350,9 @@ pub(crate) struct FalconBromParams { =20 /// Trait for providing load parameters of falcon firmwares. pub(crate) trait FalconLoadParams { + /// Returns the firmware data as a slice of bytes. + fn as_slice(&self) -> &[u8]; + /// Returns the load parameters for Secure `IMEM`. fn imem_sec_load_params(&self) -> FalconLoadTarget; =20 @@ -370,9 +372,8 @@ pub(crate) trait FalconLoadParams { =20 /// Trait for a falcon firmware. /// -/// A falcon firmware can be loaded on a given engine, and is presented in= the form of a DMA -/// object. -pub(crate) trait FalconFirmware: FalconLoadParams + Deref { +/// A falcon firmware can be loaded on a given engine. +pub(crate) trait FalconFirmware: FalconLoadParams { /// Engine on which this firmware is to be loaded. type Target: FalconEngine; } @@ -415,10 +416,10 @@ pub(crate) fn reset(&self, bar: &Bar0) -> Result { /// `target_mem`. /// /// `sec` is set if the loaded firmware is expected to run in secure m= ode. - fn dma_wr>( + fn dma_wr( &self, bar: &Bar0, - fw: &F, + dma_obj: &DmaObject, target_mem: FalconMem, load_offsets: FalconLoadTarget, ) -> Result { @@ -430,11 +431,11 @@ fn dma_wr>( // For DMEM we can fold the start offset into the DMA handle. let (src_start, dma_start) =3D match target_mem { FalconMem::ImemSecure | FalconMem::ImemNonSecure =3D> { - (load_offsets.src_start, fw.dma_handle()) + (load_offsets.src_start, dma_obj.dma_handle()) } FalconMem::Dmem =3D> ( 0, - fw.dma_handle_with_offset(load_offsets.src_start.into_safe= _cast())?, + dma_obj.dma_handle_with_offset(load_offsets.src_start.into= _safe_cast())?, ), }; if dma_start % DmaAddress::from(DMA_LEN) > 0 { @@ -466,7 +467,7 @@ fn dma_wr>( dev_err!(self.dev, "DMA transfer length overflow\n"); return Err(EOVERFLOW); } - Some(upper_bound) if usize::from_safe_cast(upper_bound) > fw.s= ize() =3D> { + Some(upper_bound) if usize::from_safe_cast(upper_bound) > dma_= obj.size() =3D> { dev_err!(self.dev, "DMA transfer goes beyond range of DMA = object\n"); return Err(EINVAL); } @@ -515,7 +516,12 @@ fn dma_wr>( } =20 /// Perform a DMA load into `IMEM` and `DMEM` of `fw`, and prepare the= falcon to run it. - fn dma_load>(&self, bar: &Bar0, fw: &F= ) -> Result { + fn dma_load>( + &self, + dev: &Device, + bar: &Bar0, + fw: &F, + ) -> Result { // The Non-Secure section only exists on firmware used by Turing a= nd GA100, and // those platforms do not use DMA. if fw.imem_ns_load_params().is_some() { @@ -523,14 +529,22 @@ fn dma_load>(&self, b= ar: &Bar0, fw: &F) -> Result return Err(EINVAL); } =20 + // Create DMA object with firmware content as the source of the DM= A engine. + let dma_obj =3D DmaObject::from_data(dev, fw.as_slice())?; + self.dma_reset(bar); regs::NV_PFALCON_FBIF_TRANSCFG::update(bar, &E::ID, 0, |v| { v.set_target(FalconFbifTarget::CoherentSysmem) .set_mem_type(FalconFbifMemType::Physical) }); =20 - self.dma_wr(bar, fw, FalconMem::ImemSecure, fw.imem_sec_load_param= s())?; - self.dma_wr(bar, fw, FalconMem::Dmem, fw.dmem_load_params())?; + self.dma_wr( + bar, + &dma_obj, + FalconMem::ImemSecure, + fw.imem_sec_load_params(), + )?; + self.dma_wr(bar, &dma_obj, FalconMem::Dmem, fw.dmem_load_params())= ?; =20 self.hal.program_brom(self, bar, &fw.brom_params())?; =20 @@ -641,9 +655,14 @@ pub(crate) fn is_riscv_active(&self, bar: &Bar0) -> bo= ol { } =20 // Load a firmware image into Falcon memory - pub(crate) fn load>(&self, bar: &Bar0,= fw: &F) -> Result { + pub(crate) fn load>( + &self, + dev: &Device, + bar: &Bar0, + fw: &F, + ) -> Result { match self.hal.load_method() { - LoadMethod::Dma =3D> self.dma_load(bar, fw), + LoadMethod::Dma =3D> self.dma_load(dev, bar, fw), LoadMethod::Pio =3D> Err(ENOTSUPP), } } diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index 815e8000bf81..09b12ad546c2 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -15,7 +15,6 @@ }; =20 use crate::{ - dma::DmaObject, falcon::{ FalconFirmware, FalconLoadTarget, // @@ -292,7 +291,7 @@ impl SignedState for Unsigned {} struct Signed; impl SignedState for Signed {} =20 -/// A [`DmaObject`] containing a specific microcode ready to be loaded int= o a falcon. +/// Microcode to be loaded into a specific falcon. /// /// This is module-local and meant for sub-modules to use internally. /// @@ -300,34 +299,33 @@ impl SignedState for Signed {} /// before it can be loaded (with an exception for development hardware). = The /// [`Self::patch_signature`] and [`Self::no_patch_signature`] methods are= used to transition the /// firmware to its [`Signed`] state. -struct FirmwareDmaObject(DmaObject, Pha= ntomData<(F, S)>); +struct FirmwareObject(KVVec, Phanto= mData<(F, S)>); =20 /// Trait for signatures to be patched directly into a given firmware. /// /// This is module-local and meant for sub-modules to use internally. trait FirmwareSignature: AsRef<[u8]> {} =20 -impl FirmwareDmaObject { - /// Patches the firmware at offset `sig_base_img` with `signature`. +impl FirmwareObject { + /// Patches the firmware at offset `signature_start` with `signature`. fn patch_signature>( mut self, signature: &S, - sig_base_img: usize, - ) -> Result> { + signature_start: usize, + ) -> Result> { let signature_bytes =3D signature.as_ref(); - if sig_base_img + signature_bytes.len() > self.0.size() { - return Err(EINVAL); - } + let signature_end =3D signature_start + .checked_add(signature_bytes.len()) + .ok_or(EOVERFLOW)?; + let dst =3D self + .0 + .get_mut(signature_start..signature_end) + .ok_or(EINVAL)?; =20 - // SAFETY: We are the only user of this object, so there cannot be= any race. - let dst =3D unsafe { self.0.start_ptr_mut().add(sig_base_img) }; + // PANIC: `dst` and `signature_bytes` have the same length. + dst.copy_from_slice(signature_bytes); =20 - // SAFETY: `signature` and `dst` are valid, properly aligned, and = do not overlap. - unsafe { - core::ptr::copy_nonoverlapping(signature_bytes.as_ptr(), dst, = signature_bytes.len()) - }; - - Ok(FirmwareDmaObject(self.0, PhantomData)) + Ok(FirmwareObject(self.0, PhantomData)) } =20 /// Mark the firmware as signed without patching it. @@ -335,8 +333,8 @@ fn patch_signature>( /// This method is used to explicitly confirm that we do not need to s= ign the firmware, while /// allowing us to continue as if it was. This is typically only neede= d for development /// hardware. - fn no_patch_signature(self) -> FirmwareDmaObject { - FirmwareDmaObject(self.0, PhantomData) + fn no_patch_signature(self) -> FirmwareObject { + FirmwareObject(self.0, PhantomData) } } =20 diff --git a/drivers/gpu/nova-core/firmware/booter.rs b/drivers/gpu/nova-co= re/firmware/booter.rs index ab374026b1f4..2b7166eaf283 100644 --- a/drivers/gpu/nova-core/firmware/booter.rs +++ b/drivers/gpu/nova-core/firmware/booter.rs @@ -4,10 +4,7 @@ //! running on [`Sec2`], that is used on Turing/Ampere to load the GSP fir= mware into the GSP falcon //! (and optionally unload it through a separate firmware image). =20 -use core::{ - marker::PhantomData, - ops::Deref, // -}; +use core::marker::PhantomData; =20 use kernel::{ device, @@ -16,7 +13,6 @@ }; =20 use crate::{ - dma::DmaObject, driver::Bar0, falcon::{ sec2::Sec2, @@ -28,7 +24,7 @@ }, firmware::{ BinFirmware, - FirmwareDmaObject, + FirmwareObject, FirmwareSignature, Signed, Unsigned, // @@ -269,12 +265,15 @@ pub(crate) struct BooterFirmware { // BROM falcon parameters. brom_params: FalconBromParams, // Device-mapped firmware image. - ucode: FirmwareDmaObject, + ucode: FirmwareObject, } =20 -impl FirmwareDmaObject { - fn new_booter(dev: &device::Device, data: &[u8]) -> Res= ult { - DmaObject::from_data(dev, data).map(|ucode| Self(ucode, PhantomDat= a)) +impl FirmwareObject { + fn new_booter(data: &[u8]) -> Result { + let mut ucode =3D KVVec::new(); + ucode.extend_from_slice(data, GFP_KERNEL)?; + + Ok(Self(ucode, PhantomData)) } } =20 @@ -328,7 +327,7 @@ pub(crate) fn new( let ucode =3D bin_fw .data() .ok_or(EINVAL) - .and_then(|data| FirmwareDmaObject::::new_booter(dev,= data))?; + .and_then(FirmwareObject::::new_booter)?; =20 let ucode_signed =3D { let mut signatures =3D hs_fw.signatures_iter()?.peekable(); @@ -400,6 +399,10 @@ pub(crate) fn new( } =20 impl FalconLoadParams for BooterFirmware { + fn as_slice(&self) -> &[u8] { + self.ucode.0.as_slice() + } + fn imem_sec_load_params(&self) -> FalconLoadTarget { self.imem_sec_load_target.clone() } @@ -425,14 +428,6 @@ fn boot_addr(&self) -> u32 { } } =20 -impl Deref for BooterFirmware { - type Target =3D DmaObject; - - fn deref(&self) -> &Self::Target { - &self.ucode.0 - } -} - impl FalconFirmware for BooterFirmware { type Target =3D Sec2; } diff --git a/drivers/gpu/nova-core/firmware/fwsec.rs b/drivers/gpu/nova-cor= e/firmware/fwsec.rs index df3d8de14ca1..9349c715a5a4 100644 --- a/drivers/gpu/nova-core/firmware/fwsec.rs +++ b/drivers/gpu/nova-core/firmware/fwsec.rs @@ -10,10 +10,7 @@ //! - The command to be run, as this firmware can perform several tasks ; //! - The ucode signature, so the GSP falcon can run FWSEC in HS mode. =20 -use core::{ - marker::PhantomData, - ops::Deref, // -}; +use core::marker::PhantomData; =20 use kernel::{ device::{ @@ -28,7 +25,6 @@ }; =20 use crate::{ - dma::DmaObject, driver::Bar0, falcon::{ gsp::Gsp, @@ -40,7 +36,7 @@ }, firmware::{ FalconUCodeDesc, - FirmwareDmaObject, + FirmwareObject, FirmwareSignature, Signed, Unsigned, // @@ -174,52 +170,21 @@ fn as_ref(&self) -> &[u8] { =20 impl FirmwareSignature for Bcrt30Rsa3kSignature {} =20 -/// Reinterpret the area starting from `offset` in `fw` as an instance of = `T` (which must implement -/// [`FromBytes`]) and return a reference to it. -/// -/// # Safety -/// -/// * Callers must ensure that the device does not read/write to/from memo= ry while the returned -/// reference is live. -/// * Callers must ensure that this call does not race with a write to the= same region while -/// the returned reference is live. -unsafe fn transmute(fw: &DmaObject, offset: usize) -= > Result<&T> { - // SAFETY: The safety requirements of the function guarantee the devic= e won't read - // or write to memory while the reference is alive and that this call = won't race - // with writes to the same memory region. - T::from_bytes(unsafe { fw.as_slice(offset, size_of::())? }).ok_or(E= INVAL) -} - -/// Reinterpret the area starting from `offset` in `fw` as a mutable insta= nce of `T` (which must -/// implement [`FromBytes`]) and return a reference to it. -/// -/// # Safety -/// -/// * Callers must ensure that the device does not read/write to/from memo= ry while the returned -/// slice is live. -/// * Callers must ensure that this call does not race with a read or writ= e to the same region -/// while the returned slice is live. -unsafe fn transmute_mut( - fw: &mut DmaObject, - offset: usize, -) -> Result<&mut T> { - // SAFETY: The safety requirements of the function guarantee the devic= e won't read - // or write to memory while the reference is alive and that this call = won't race - // with writes or reads to the same memory region. - T::from_bytes_mut(unsafe { fw.as_slice_mut(offset, size_of::())? })= .ok_or(EINVAL) -} - /// The FWSEC microcode, extracted from the BIOS and to be run on the GSP = falcon. /// /// It is responsible for e.g. carving out the WPR2 region as the first st= ep of the GSP bootflow. pub(crate) struct FwsecFirmware { /// Descriptor of the firmware. desc: FalconUCodeDesc, - /// GPU-accessible DMA object containing the firmware. - ucode: FirmwareDmaObject, + /// Object containing the firmware binary. + ucode: FirmwareObject, } =20 impl FalconLoadParams for FwsecFirmware { + fn as_slice(&self) -> &[u8] { + self.ucode.0.as_slice() + } + fn imem_sec_load_params(&self) -> FalconLoadTarget { self.desc.imem_sec_load_params() } @@ -245,23 +210,15 @@ fn boot_addr(&self) -> u32 { } } =20 -impl Deref for FwsecFirmware { - type Target =3D DmaObject; - - fn deref(&self) -> &Self::Target { - &self.ucode.0 - } -} - impl FalconFirmware for FwsecFirmware { type Target =3D Gsp; } =20 -impl FirmwareDmaObject { - fn new_fwsec(dev: &Device, bios: &Vbios, cmd: FwsecComm= and) -> Result { +impl FirmwareObject { + fn new_fwsec(bios: &Vbios, cmd: FwsecCommand) -> Result { let desc =3D bios.fwsec_image().header()?; - let ucode =3D bios.fwsec_image().ucode(&desc)?; - let mut dma_object =3D DmaObject::from_data(dev, ucode)?; + let mut ucode =3D KVVec::new(); + ucode.extend_from_slice(bios.fwsec_image().ucode(&desc)?, GFP_KERN= EL)?; =20 let hdr_offset =3D desc .imem_load_size() @@ -269,8 +226,9 @@ fn new_fwsec(dev: &Device, bios: &Vbios,= cmd: FwsecCommand) -> Re .map(usize::from_safe_cast) .ok_or(EINVAL)?; =20 - // SAFETY: we have exclusive access to `dma_object`. - let hdr: &FalconAppifHdrV1 =3D unsafe { transmute(&dma_object, hdr= _offset) }?; + let hdr =3D FalconAppifHdrV1::from_bytes_prefix(&ucode[hdr_offset.= .]) + .ok_or(EINVAL)? + .0; =20 if hdr.version !=3D 1 { return Err(EINVAL); @@ -284,8 +242,9 @@ fn new_fwsec(dev: &Device, bios: &Vbios,= cmd: FwsecCommand) -> Re .and_then(|o| o.checked_add(i.checked_mul(usize::from(hdr.= entry_size))?)) .ok_or(EINVAL)?; =20 - // SAFETY: we have exclusive access to `dma_object`. - let app: &FalconAppifV1 =3D unsafe { transmute(&dma_object, en= try_offset) }?; + let app =3D FalconAppifV1::from_bytes_prefix(&ucode[entry_offs= et..]) + .ok_or(EINVAL)? + .0; =20 if app.id !=3D NVFW_FALCON_APPIF_ID_DMEMMAPPER { continue; @@ -298,9 +257,10 @@ fn new_fwsec(dev: &Device, bios: &Vbios= , cmd: FwsecCommand) -> Re .map(usize::from_safe_cast) .ok_or(EINVAL)?; =20 - let dmem_mapper: &mut FalconAppifDmemmapperV3 =3D - // SAFETY: we have exclusive access to `dma_object`. - unsafe { transmute_mut(&mut dma_object, dmem_mapper_offset= ) }?; + let dmem_mapper =3D + FalconAppifDmemmapperV3::from_bytes_mut_prefix(&mut ucode[= dmem_mapper_offset..]) + .ok_or(EINVAL)? + .0; =20 dmem_mapper.init_cmd =3D match cmd { FwsecCommand::Frts { .. } =3D> NVFW_FALCON_APPIF_DMEMMAPPE= R_CMD_FRTS, @@ -314,9 +274,9 @@ fn new_fwsec(dev: &Device, bios: &Vbios,= cmd: FwsecCommand) -> Re .map(usize::from_safe_cast) .ok_or(EINVAL)?; =20 - let frts_cmd: &mut FrtsCmd =3D - // SAFETY: we have exclusive access to `dma_object`. - unsafe { transmute_mut(&mut dma_object, frts_cmd_offset) }= ?; + let frts_cmd =3D FrtsCmd::from_bytes_mut_prefix(&mut ucode[frt= s_cmd_offset..]) + .ok_or(EINVAL)? + .0; =20 frts_cmd.read_vbios =3D ReadVbios { ver: 1, @@ -340,7 +300,7 @@ fn new_fwsec(dev: &Device, bios: &Vbios,= cmd: FwsecCommand) -> Re } =20 // Return early as we found and patched the DMEMMAPPER region. - return Ok(Self(dma_object, PhantomData)); + return Ok(Self(ucode, PhantomData)); } =20 Err(ENOTSUPP) @@ -357,7 +317,7 @@ pub(crate) fn new( bios: &Vbios, cmd: FwsecCommand, ) -> Result { - let ucode_dma =3D FirmwareDmaObject::::new_fwsec(dev, bio= s, cmd)?; + let ucode_dma =3D FirmwareObject::::new_fwsec(bios, cmd)?; =20 // Patch signature if needed. let desc =3D bios.fwsec_image().header()?; @@ -429,7 +389,7 @@ pub(crate) fn run( .reset(bar) .inspect_err(|e| dev_err!(dev, "Failed to reset GSP falcon: {:= ?}\n", e))?; falcon - .load(bar, self) + .load(dev, bar, self) .inspect_err(|e| dev_err!(dev, "Failed to load FWSEC firmware:= {:?}\n", e))?; let (mbox0, _) =3D falcon .boot(bar, Some(0), None) diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/= boot.rs index c56029f444cb..78957ed8814f 100644 --- a/drivers/gpu/nova-core/gsp/boot.rs +++ b/drivers/gpu/nova-core/gsp/boot.rs @@ -178,7 +178,7 @@ pub(crate) fn boot( ); =20 sec2_falcon.reset(bar)?; - sec2_falcon.load(bar, &booter_loader)?; + sec2_falcon.load(dev, bar, &booter_loader)?; let wpr_handle =3D wpr_meta.dma_handle(); let (mbox0, mbox1) =3D sec2_falcon.boot( bar, --=20 2.53.0 From nobody Thu Apr 16 08:34:48 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012063.outbound.protection.outlook.com [52.101.43.63]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F94F317141; Sun, 1 Mar 2026 14:04:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.43.63 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772373851; cv=fail; b=n/J+syyxLHEocNu0YnWurE37mNGh2oL4/VfGsUUTxjD9TZzm5B6zwUI/KD/EHWoH4XecGUV/3BEoJVT6R3P5EwaI1QIK/CaO8aLngJgrCTF8VoivEV1hN/qw8mtqEk5cJPglNfl4fwVeDp5M4O6v9QoLdTNHnpU2A2rKEF/2SHA= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772373851; c=relaxed/simple; bh=vSWiRbnws4wYxbCjQbAWJRBM1uasSW409ny1V9x6mQQ=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=Xcvu3FM+8SPx8Bu9/mCfBelDnSgx/EiwZKmLdA6sdXWXytNuC4TZW7s/Tzra2MZ4ktzSF9WC1jl0tJ24ly0GxHAB5eQP8Uw3Or96ybsmCqzypit77a0WBE77W1ensB+Sm3Z0HYq3c4yarOAJw9IsZ/3AlGVHvzKSZI1gxpwoyKQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=gnJMDHWk; arc=fail smtp.client-ip=52.101.43.63 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="gnJMDHWk" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=sZ+JRIgMrRTW2iUy2rHAqEWZ9kjCjSlK2PNGMIKUgt1WhXrUaTufqU/lFsPZjuL+oBEAnW2FuO3QZ6Oh7A38+hFYi4GZ/Ud43fYadt2/F8TmwIwK4IKtILtLwiy5XL1PG/cY6JwY23n5Vx4BnXURoa+MqMOZp8m2MSyJ19H836N0Qyze104y+8AGScWzZ/QAYMdtVXQc4AarqUA64md8/qYm3yrLtBO6vaDCvn7iseRyo7sU5H5COKDLEeI1OA3sBK4qC+3IIs95I07mqSaz7HUrRmAoGhNMfJhBQSkIlKZmld4fzxSYweGhvhRErSFw31wJQyIA8BM9k7DA9MGeoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=aud2TLeEKC72QNU2PMJEYofNwuHgLyuaoRuIsCU0Gmo=; b=tjGrnBVBFpMIZ/xX3sGpB5H8nrYX6mcRohMIi2TQvh/1zeR6ebf0lwVvkYMQq+B7TNwp9/QRl61JVG5IQpyyT89eyZmiOs6AkjTM38txX/a6MTHyrHEqNshdVk2LuT/MkGeMWRDBjQOFs5Xmxx6Ce0ZlxIBUs+GtF86S3jjjB5n/IeI61YqTEZRX2lzWPnCEWIvtyKx/CkKWuhBZnmjb8h8H/hXgTmNCa455Z8bWzZQ8qtsAa5CA//I/utB/6zGRhHWlu5UuvO7m3uutNlNshFy1D6XwKQ7caCnV9befpf2eAT4Bk6dHiBwiMFkmehWNeMyYUFH6+Fr6zQAYYlGU6w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=aud2TLeEKC72QNU2PMJEYofNwuHgLyuaoRuIsCU0Gmo=; b=gnJMDHWktT8tm+T6Sip60iADl1poynaeC1euXhMgLrzxs8UoQNeV8ExStIxGwFioVVv3Z3hhH1TzS+QSWDaBkKYj2nkvBTaw8a8R79t5RE3/LKeaQ642QpQ5faHIkZ8gq/Xe3b9yDrSC2MwUjgeb4CJNher8KY3Gu2fm53bYoT77AYFho1Cw2ru5tdF46DaTzEXMAFbCdRmnLI5k+JGcquwaoMhBLm+GUtLokACOttO1tirRaNAgD0JpmgjPXSMwuCGLuuDgoxWsjrvbXCAtWzmm0U/HI+HLYM4JhS0IeXGTr0KXS26D4359+iVcZ0TeGkZcqKsWbgUTWjn3NMtsgQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) by DS0PR12MB6632.namprd12.prod.outlook.com (2603:10b6:8:d0::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.19; Sun, 1 Mar 2026 14:04:06 +0000 Received: from CH2PR12MB3990.namprd12.prod.outlook.com ([fe80::7de1:4fe5:8ead:5989]) by CH2PR12MB3990.namprd12.prod.outlook.com ([fe80::7de1:4fe5:8ead:5989%6]) with mapi id 15.20.9654.020; Sun, 1 Mar 2026 14:04:06 +0000 From: Alexandre Courbot Date: Sun, 01 Mar 2026 23:03:45 +0900 Subject: [PATCH v10 02/10] gpu: nova-core: falcon: add constant for memory block alignment Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260301-turing_prep-v10-2-dde5ee437c60@nvidia.com> References: <20260301-turing_prep-v10-0-dde5ee437c60@nvidia.com> In-Reply-To: <20260301-turing_prep-v10-0-dde5ee437c60@nvidia.com> To: Danilo Krummrich , Alexandre Courbot , Alice Ryhl , David Airlie , Simona Vetter Cc: John Hubbard , Alistair Popple , Joel Fernandes , Timur Tabi , Edwin Peer , Eliot Courtney , nouveau@lists.freedesktop.org, rust-for-linux@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-ClientProxiedBy: TYCP301CA0034.JPNP301.PROD.OUTLOOK.COM (2603:1096:400:380::14) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|DS0PR12MB6632:EE_ X-MS-Office365-Filtering-Correlation-Id: f4901671-4721-4457-ff53-08de779b66f5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|366016|10070799003; X-Microsoft-Antispam-Message-Info: xZanZuxjiJP7IW7OVwA7Fid0e9UKa4V+EDV7sdrUY54mVHVn4+MLO4htUTTBLbReNULqQlkEh9nftQPgzLinTcG9jYQr2nQCOnO91XsynKFM9YV8XuoHIAEd6omWyKpp1HihpEJzJu6CoNlD0QskWMvEtLq/zmed9RLZOPNkHlvVlYJm4kq+btNbOpL3sbmklQPZ8U0FY3NR8ILDhjdt6GV2pLozFqDGllKDqhYAZjqk5hw8niMMTJO3c257ciQ6XvHa/0ZMYuVkGJo5GR7RXj+KjdJxySLR0r1sf+pjsoYbfL54mZT1xBleqO7vhmsjKtEoOC4FT9Wd8Jqvqz4v6wR9tVGk3sRf1bPUSmJbRp6zLElplrpt5dVYTDbkueGrCJCzixatfKENhtBvpARgnqUI7BADUTDmEwShardEoNZ1r483zPCtZY1v3/Dm8Zf5UDgQOqra9ZlyV67VK2npqqVNBRZOT4E/VKbZThalTroil6Dwtc1NtjgHH0UdhWAf3P++/x1OCsP40FZ+Sv50jRHWgGP7wD8CA64HFK6xR6urF3Bx2Z46zHAEieSVjiQFwMO9mkrMr/3B3dQRSo/vw+n1C4icmT+TqRsDIxuPZJJVoZjHFGiksKpzjHQUS3N5A/G9e6nUKSbqFoITfQ03/YvIWC2Hv5/lv95w7RO/9w9rCsmaKAS67sU5N24s0PPJEZK7xxGSiw/ZfNE0sSs5wED2QkL5SZ3UX2SBsPvhzpQ= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CH2PR12MB3990.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(366016)(10070799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 2 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?WTBrMzBNOXYydjN0YjZ6dm9iSUYxemJCRklzblRLYWRoWHdpLy9QT29CeTda?= =?utf-8?B?TnF6K1NJSjVhTFJ0YzYvenhvdDJkcC9rdXR6OEVwUCtSc1krVGdBRWI5YlNp?= =?utf-8?B?dFZWQ0tEMi9RMzJIc05wZHhtWkoySkdQdWliMllFaTVCZGlYb3M2cVhIa3p4?= =?utf-8?B?SHlUb3NOd2ErYVhFRVU0Y2RCRFZ4MCt4L3UwSjMwb2prZytGOVNuMFBhM2RH?= =?utf-8?B?ZGhucUVhZ1NPdlVDZ3R4eE40dW1NazFaT0JBQjNVZlhyWVlUZmN1bUVJTFc4?= =?utf-8?B?V3ZkdXFOTmlrUWl6QVRBdGpzMkZYMkVPd2dac0RVbG4wbmtlYWppMHovSzBj?= =?utf-8?B?ajhXSnZLUWNZaWNzbFZ4NXpxLzgwYXptdU9MSnMxaGtTOXB0VnRYcU5jeWlI?= =?utf-8?B?QzIrcjk1MTZBdTZ5Z3FkQXZnS3M4a2lkME9uSVg5RXBvSW5LTVd0YzZ2c3A3?= =?utf-8?B?K3VuRGkyR0p1Y2IxQWlSQTNuTDUrY0NYdUQxdExyM3hQMDRERUxnYWxUbWJF?= =?utf-8?B?NFJYVUFXM2VOcm9EUlFQN0EyYWErNFNjaUdqQ3phdTRuWHF1TEFNdURBRk85?= =?utf-8?B?WEQwNXhRV3UwRit0cnB3RmMyekVSRmRoeTBIeGVuSlZybklPSWtXZHRxajZC?= =?utf-8?B?M1Y3MS9wSjRCelFPN1BBOTBkdytxTEJlejhCTFdmUWZ6a3BnbG1LRFFMekRD?= =?utf-8?B?TXVqak1ueTJOaG84N1NBT1Jqd3paSDF0OGdDSjgyb1BrRlNwTXAreUpqaDFN?= =?utf-8?B?Z0lMRmFPUllZYlhqS1Q0WXc3OUdYSGZ2NitMRkRvK2lPSy8wZEJTRm9oRnZG?= =?utf-8?B?dHd0SS8zODNGR0pPcUFvbUVEcWxoUGsvVkp5SDk3dUFMTENzVHJjdnpIQUp5?= =?utf-8?B?eERsOFdqdzRwdHpwSWlyUTlyNXJTanIvTzUzMUtuS2dUQnBweUs4WEJIT3di?= =?utf-8?B?b0poZlNiYk55MlNtNXFZVDBlanNvdTZ6MDN1RzkyM1JoNGUvRGx6T0VPUmxm?= =?utf-8?B?eFpxMlIrMGdHTWRaVzBCbC9xUFV4b01Zb3N5UGlSWjVucDhSMW4vMkIydjhC?= =?utf-8?B?WTdYakRqdnZzZUJwV0huNmNGaS8ya2RCRS9LOFJ4eERPUko2eUkvV1Rsd0hF?= =?utf-8?B?YURHcFhBNDdLK2dlaGlYSVIzdFZYRXZJcHBYUkxoWnA1Sm9IK1VsZkxtZGVM?= =?utf-8?B?SVk5NVdaRGJVT0hYZmpkdFFTYzB5cnFiTSs3SGh5Nkd1enFzVHRPNTExeE5I?= =?utf-8?B?WndsZkI3RVFsR0JUNXRlTkozc2ZXNFBBM3lvQTZoMGtVaFZnN0t4eVl1cW9F?= =?utf-8?B?SmZodTdCd3J2QkVvRFdveVI1aElQSEpsV3JKUHJTTkVrQ1dTSW9xSzQySU94?= =?utf-8?B?RFFrMWhiVks2TENDWGRWSXV2RllldjF1TFV6V2w3eG5BZExmbjY3L1JvRkU1?= =?utf-8?B?Q2dDMmovc0p5Snl2SGFITEljYWlqOWZxWTZjc2pEV3RnZmQrU2xTb2NlbGJO?= =?utf-8?B?TUpXU2VVeU5JQ1JjekM3dGkza3ZKMERBUUozczZkV1hMbk9IZVFFd0Rocjdw?= =?utf-8?B?clVXV0p5UGtkMU5Nek5tY0dBQlA0c3JCWlljcUJnV20rSURiT3B6RHNLME9a?= =?utf-8?B?aGZGV0tiOWg1emwvTWdpR3FjOHh6MUl6U1YzQ1grckhxVEpzckptYWE0ZmV5?= =?utf-8?B?WStFNlhaYk5Gb29GM0krMjF3NGtvNjZtTWRhVjZXQVFtUVFFYU91RTJNMml1?= =?utf-8?B?MVc2ZC90enZXK0d6elJ4TGxXNktIVUExeHFad1dmOUVGWWl5NjZnZVlCbGVj?= =?utf-8?B?TWJieWM4OTNoK1FkSlJvbGdWeTMwdjNRVTlpOUpQQlFTVWYzeTBNdjFFZUQy?= =?utf-8?B?UjBXbFdJMlBMVnZ1VncvcTFWV1JXM3hyRDhBTGo5aEVHL1hpS1E5K3Q1dmEv?= =?utf-8?B?R2dVb1NTV1ZuTVJLa0xEb1kxbkpkNU5rUUFOOVlGWWZFeGM5RGFWRGZqWkNj?= =?utf-8?B?Y3FTWlFpck00Ti8vMFpjQklqaExoWUJCNGVTYW5rMGVFOVozUW56ZDU4V1NG?= =?utf-8?B?c0FGalN6QzJIWkJnYUpJN0IwdjZaWWxnMEdmSVRIdG1PRXJCalJTNzI3QSt3?= =?utf-8?B?bUM2MCtZTitiR3RrMzlKeGZaZjdPbHptRVdiVEczck1RN00vMHRlZko0azdT?= =?utf-8?B?ZWdaeUZELzV5SExHU25rUmQwN1VXM2xoQk5MQUJobGdnRjA3dVIvS0MweXRS?= =?utf-8?B?WXhLQzdBaEhOMytEM2RJOHpMeVVCeENYS2duVnM1cmdUamo0all5Z3NZUHNy?= =?utf-8?B?TkovbzF6YzMxY1RzRGZJMnV6RzVocE1nMmR6MVp5UE9BdU14aW9ManFoc2hC?= =?utf-8?Q?iJn+7+D9jKfiqosXcDLFNeJrO34V/frRcGlyocZl6nGWZ?= X-MS-Exchange-AntiSpam-MessageData-1: LTlZ+FRPKKI8EA== X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: f4901671-4721-4457-ff53-08de779b66f5 X-MS-Exchange-CrossTenant-AuthSource: CH2PR12MB3990.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2026 14:04:06.5415 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Ok7HBlBRHdenbtROKuWR14V6yNYnlsskpFK83BLwOO3h7nygn8/kqc3zrwpeucyUTobyBDm6488/07+VK3gEqQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6632 Falcon memory blocks are 256 bytes in size. This is a hard constant on all models. This value was hardcoded, so turn it into a documented constant. It will also become useful with the PIO loading code. Signed-off-by: Alexandre Courbot Acked-by: Danilo Krummrich Reviewed-by: Eliot Courtney --- drivers/gpu/nova-core/falcon.rs | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index 8d444cf9d55c..31217cd3a795 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -25,6 +25,7 @@ falcon::hal::LoadMethod, gpu::Chipset, num::{ + self, FromSafeCast, IntoSafeCast, // }, @@ -36,6 +37,9 @@ mod hal; pub(crate) mod sec2; =20 +/// Alignment (in bytes) of falcon memory blocks. +pub(crate) const MEM_BLOCK_ALIGNMENT: usize =3D 256; + // TODO[FPRI]: Replace with `ToPrimitive`. macro_rules! impl_from_enum_to_u8 { ($enum_type:ty) =3D> { @@ -423,7 +427,7 @@ fn dma_wr( target_mem: FalconMem, load_offsets: FalconLoadTarget, ) -> Result { - const DMA_LEN: u32 =3D 256; + const DMA_LEN: u32 =3D num::usize_into_u32::<{ MEM_BLOCK_ALIGNMENT= }>(); =20 // For IMEM, we want to use the start offset as a virtual address = tag for each page, since // code addresses in the firmware (and the boot vector) are virtua= l. --=20 2.53.0 From nobody Thu Apr 16 08:34:48 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012063.outbound.protection.outlook.com [52.101.43.63]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6CBF2C028C; Sun, 1 Mar 2026 14:04:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.43.63 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772373855; cv=fail; b=eQcIF4ikD17XT2Q5PKq7dDgUXZzRsXOBF3sEA50VRXaHyeCESYE02Q0SsIWJxNRilkmoHzs4ypMbxfNBHC1zFBD2hd2ocm2TkKo1c/pVSxNlh09neFzBxDJ4M4ikFlB7MNx9dqTK9Dxo6O8iaYut4qxxwld+D+o51J5sqdpxHk8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772373855; c=relaxed/simple; bh=O7Kuee3duj8OKoigZ+UscSMK8Jn/HzWUTdBLV303XDQ=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=M0UT60GY1pReYpxqJx668TTlt56bEN/KKUcg0S9xcFmsii2DfIn8xOdzOGPEDQ0VoVgZxpeBBes9xi1C/4FL6ixGWu57SbDNCAkkVRMYfzatihhdfXIjyzHHsGVJH5B+5mk45obq/7G9NKDr5k2ZnZVyWJ0URtecLd1nxLr0oWc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=VXLlVLJK; arc=fail smtp.client-ip=52.101.43.63 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="VXLlVLJK" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Vbl098fM0v1+PZ6bz+zsgjcaWt+SKsVvezJ2zEtwO5wsVXiBB+GSIEoSNWL4dpraRs4hMSj1h/X0/qKH4YF8mFGorySGtGigmByNh5gMknGqjbHT7Xrb7BgSFmDtQNKxNxiZ39xXf7GGPET2B1nzgB758rnz51NYz+eXmvqgm5VwI4WPdBIQqPF7Fld/Uul7TXYyB5ABzv0lA4R+HAqvnBrojiPrlEQJHxPS1+KXnlvpZ0BLPBjc+v1WRTBHTsPTD9fkVU2aUqnT0wNKN1/+0HqFDXuzm0+bxctr1BlG/2C0h9SnSrdcEPEfxsoLTYXUzRYnYnuJ3uROUKYw06fZEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=uYuunDNfKDzpQu1lHJv0PNN3py0bop0d5/vlzm00ic8=; b=DvRQcEUOkzgdB+6xSmADCYbIzC5uX2xTfoLQgplH/z8OfjIEDAKlU0z64NSeixfnXzXyq/Kr2+EBJcNEMdxDRi234AyYYWSsH+SFtwjWzQkdcfkrcqWpwJbcKuvyLD4woezxmAARkmUlG1tHvd7fYh9wpq5eGGd3Jti8Ni4DcpJ3DWOlq+sLpGpcghcAcBph0hPhUsiXK4IdccTG/LnQYg6IS/Tt2GU/htTAie4BUxMRcFeYAzgmhjRbKatPAmYW5H4jSAZSHrYU72BubM6nHMN7u+tRILI4f9VYT8qKbL4IqU54MSBAtdPfxL6Eh1XBKca6ylkhkWJJakZdXEkujA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=uYuunDNfKDzpQu1lHJv0PNN3py0bop0d5/vlzm00ic8=; b=VXLlVLJKYecIgVM66NrcDPCbVW4zxqmnLZHTA3ss4D+yy3ZSTJxI68tFEP7F7L044L1CLcu/+pfiWfAFL016uK4aFBzan+JJZtlmywu/8ZqScpdPO2Jvldxw5Z+e9FWE76DzqoO7uRI6U57RS2mr3GyQAM/oFl76adg8RKGetCuFgimurix5cyXRn85AgRDxN1cWKpVQ8XkeZ8Q1CLTMJU3zy+ddGHpuDwY51UbVizKzO3csMWmTCpYm2p+9wqoka5/z5Cz/E6l4X/PxdXWV1wWiVvWZ+nA4WY5iFFWKrSpnsxp/FvmI0jSbJLgYZVBR8BePnkLGZGy7MSQKlRf+Pw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) by DS0PR12MB6632.namprd12.prod.outlook.com (2603:10b6:8:d0::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.19; Sun, 1 Mar 2026 14:04:10 +0000 Received: from CH2PR12MB3990.namprd12.prod.outlook.com ([fe80::7de1:4fe5:8ead:5989]) by CH2PR12MB3990.namprd12.prod.outlook.com ([fe80::7de1:4fe5:8ead:5989%6]) with mapi id 15.20.9654.020; Sun, 1 Mar 2026 14:04:10 +0000 From: Alexandre Courbot Date: Sun, 01 Mar 2026 23:03:46 +0900 Subject: [PATCH v10 03/10] gpu: nova-core: falcon: rename load parameters to reflect DMA dependency Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260301-turing_prep-v10-3-dde5ee437c60@nvidia.com> References: <20260301-turing_prep-v10-0-dde5ee437c60@nvidia.com> In-Reply-To: <20260301-turing_prep-v10-0-dde5ee437c60@nvidia.com> To: Danilo Krummrich , Alexandre Courbot , Alice Ryhl , David Airlie , Simona Vetter Cc: John Hubbard , Alistair Popple , Joel Fernandes , Timur Tabi , Edwin Peer , Eliot Courtney , nouveau@lists.freedesktop.org, rust-for-linux@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-ClientProxiedBy: TYCP286CA0050.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:2b5::8) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|DS0PR12MB6632:EE_ X-MS-Office365-Filtering-Correlation-Id: ca79bbbe-1196-46f5-3a26-08de779b6945 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|366016|10070799003; X-Microsoft-Antispam-Message-Info: sIzIRUcpoD3UDwltZcMX26HYbQeLHprxbTH8MKkd0oOpsH144KiqAH0ffF3OkPDPa/6DTfpgClNOQFjayJ35e8vv5NIPlbqUh24L6KnP1XxDezc6D/HaycXz8/9gnzRzJczQ7aJs3pjWfKTcWEg/ROHgC2ER1V8GRxxcyFtgRLqG01bfzym4lDRO0Ho7FMPUR8xDWddbhx8tMpKSe5eHMzTnjLvn5hTreWPrYdJ0sMy//QJRx+199YGVrRJhxsSpamxxzdf8sco9sRqFwftdAKpkKXM6RYHPGMlkjslRFlo/Op3/AXdgFNoeO7Aq/A5h8bL4FIR0eVm45oN4s8qXyUuA2DS2C/hl62zDmhmuwxYEAheOi73HhXsBQC3fdM0JzFsPwXD6xpIMZNWzf+O2XtFJCfE6ip0Tk+AzkavGpscfyvHg6io+umrXjNcqKFHCS5hvF/MRsWeEalM5DcldsZzSbQ+Vtpjwdt9/9TABgzH1yD3DgU0QMgLJXFV9MuF33Nx2kTQ1OGDaEDfdA7Z43Il3ERO7j4WZ13YgO2E0U767hxfR87pv+pLySNgkygJyrqb2adcpxIbjkoLt90H54StVaAdVbLFytjJlGY6VOrR+B9By8qB+0qHNoG0Z/JRXDQroGi+lLPCG6YNKCFvEGeZ7d8hM3Al/RSt5XMS9wfimh0TmUh3nkpQixKO1e2dBibNeHICOl0oH4uPHVR7GCagDEL4zGfD2RPWKoXnSNWk= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CH2PR12MB3990.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(366016)(10070799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 2 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?cmdrQzBqL0dRYnRwUHJDTjdqN1YyQTdSWWZNQVlJY3pKV2xBa3Z0WGliVkM3?= =?utf-8?B?cHRkclJqaWRIeEU3RFRQdmhwVEU5dDZEMGNGTVJYRWNMdXpzYVlsL1BGbkxs?= =?utf-8?B?b01SNWc2TGtyN2NVTHpIdXdaa0taODJ0OGNUc01teFRqbGlJQVFPTE5qM3Z5?= =?utf-8?B?S1ZYQ3Q4NmM0TUV1V1NaaXpMNnRINFZMNXpsUWlsTHFuVEt2VW1zTHZ2cG41?= =?utf-8?B?aStsRXcvN1QwdklKUFM5RnNlcmtEZzBRRGdwdG9qTHR6QzBqUmlUQlRYTnNy?= =?utf-8?B?ODJJOGFKMlprS2NtakRDMW1xbEtyYVJwSmF1ME8ybUxHUWh6M25VWjZaNENG?= =?utf-8?B?dXNqYmVROXRCSlZEcmZHUjlZSXVqOFNOd2NjNlllcCsxVXFJUWVid3FiOFc1?= =?utf-8?B?c3NGVlJST2kxWUVMZEdDcDZyRGU0VVU2RTZvZ3U5ZFNJQlRYK2JVYkpZWENR?= =?utf-8?B?R0ZUUzNxVXZFYWFYWTBhNlVra0Y4ZUVJWnVheHl1SmoxS3lZMFdFcVNhUGd6?= =?utf-8?B?a0hUTjZEdlRLSUpBWThjTVNJKys3amhqOUlvcGI4Nm5NQW9TWU9yeEJ1bUxk?= =?utf-8?B?MXVoNHYzSDR2TTh4blR6Z3h3UGpYRzVkbTRqNG9NUE9JWDFBZTUzeXoyelFo?= =?utf-8?B?bXZ3MjMvK2xsS09VYmJSTU9TTlhBL3ZxZHhIWnhNVFBXWkxLTlo1QUc0WXk0?= =?utf-8?B?ZzVmMVJPK1QrZGlkTno5WVhocTNOZlpjU1l1czdXRCtBSm1ReWszY3hFQk1P?= =?utf-8?B?L0ZqczNSc0tyV2FhbTJaVlpCUEdDb1llQVlKOWI0UkV4NGFrNko3dzR4dExC?= =?utf-8?B?U0FsSmFIMlhrcHRqdW9ob28xQ3RsY1RrTzJQeCsyVEF6TmhsbVZhZTg5TExJ?= =?utf-8?B?aHBWSm5DRTAxWVFhclN6N09tVmFsTnkxdmRtYlZhRFpvUXRscDlrMkw5NCtN?= =?utf-8?B?MjZZcE1lNkZoR2M3amkweC9wcHh4TnY0d2hXMFhMaHJVRVJsMGMwOEJnbml0?= =?utf-8?B?bVh3aTk1UWhJaXZZcU9KMnp0d3BISXIwRThiVTN4d0o0U0JmN2hYRGs4aWJW?= =?utf-8?B?RC9KbE16VlpaUWdVVVFlVFFoUkROS1RkSURwNys4NUJEY004R2ZTamQ4L3ZQ?= =?utf-8?B?dlVjYm1hT2pNYnZTRTVTU3oybjZ3Zmdpa0tkMThDUW9LMkp3cDQ2Y3h5WEwr?= =?utf-8?B?WE4xci82YlB2c1ZsL3NYcDFxZmRRTEZ5U2RRNk55QS92VEtVOXZzL0FQVk01?= =?utf-8?B?WFdJbXg0RklpOWs0Nm5FTjYybHdPR3NwOGF3elRNTFlONVVGMHFSVHhiZ1B2?= =?utf-8?B?TTdreVEvWU5ZaGJib2ZJaGpOeTI2WHkvTnJVdHlrOUhLQWRWYWRSQlBJdXQy?= =?utf-8?B?MWp4bnRVNmg3dGhpTXJzQmwvM1c5djVwdFB4c0RTNjNGeG1UMWNKcSs1TVZ0?= =?utf-8?B?QWljczBscy9LWUE3c0RVOXg3cmd5blpJM2FOTUF1QjBCWG9ZQU1PVWNINnFB?= =?utf-8?B?R21OME1zRG1aRlMranJPZ01OalhxdlpEUHk0VFlodmdrUnAycWR2Z01GaHMx?= =?utf-8?B?Q2swN2dUbGw4c29FVG5KTGpqN2JFZFRCZUx2akVaUjN6N2t4eWZ2eU4yUnJR?= =?utf-8?B?bGtjNlRuWmxmaXFVMUpuQ3VsZVVrMDJEM0lmOGhDc0dUWU13bEljbWN6ZTlv?= =?utf-8?B?L1JCWFpweFd5a3ZKM0FWbVN4ZlhMRWgzcDJIY2tZMTB3dUhOL29FUklFUFYv?= =?utf-8?B?OE5xTUhJNXNYL3JEeXR2cG5STUw4V0dtSTc1Njl2eUR4S25PdURrQ1QvVFBB?= =?utf-8?B?U3ZFSnlkYzFiS1JkQjNHLys0Z0U4bDh2Y2tDZVU4UUFpWEtwM2xadERhN28z?= =?utf-8?B?YlRCSEltbHY1ZmF3TUNnS0sxT2JHRDR0aFpkbGFwR21TUG9qK1djcHRjbHRo?= =?utf-8?B?ckpCanN5Z3FHd2E4Umticy9od2ZwZjRtWWxtZVVTSllHN2tDVGZQZmZhaEpS?= =?utf-8?B?T1BNUHhmVHM3U1p2aDVlOWRUSkdBVnFZN1F0ZllUV3JWRSt3VTAyZERDUWQ5?= =?utf-8?B?RHpJZGRlb2svUXBMQ3I1VU1yUWY2VDhkVUJEVVhtb2RBZVdzcWMrLzk1VTBR?= =?utf-8?B?azBHZ2I0Vml1N1JJSWFuYXpONEpBNXhvdUR2SkpRODVSUTQzc0ZHR0tFV3Zn?= =?utf-8?B?b2xjQXJ6Wm41WUZQWk1zeXdnUndGMHZGUGFFcmo5WW9sMXhTbEx0aUhoTEpn?= =?utf-8?B?a2RybDU1Kzd1c2tmYU5yYnY1RW1XOTBCZTZRSEp6enhwNStHMEtsNEJPdGdM?= =?utf-8?B?aUtsVTVzV3BBZUhESlcyR25Xc1F2YkwvcHFnRDhac2xLaUVTd1BJR2R5cWxP?= =?utf-8?Q?4cKJzDiUP01s3gtzWYU7fbQlD5EfvUMvNAYrog+stMmpG?= X-MS-Exchange-AntiSpam-MessageData-1: IkU6kr9v+mfbMg== X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: ca79bbbe-1196-46f5-3a26-08de779b6945 X-MS-Exchange-CrossTenant-AuthSource: CH2PR12MB3990.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2026 14:04:10.6325 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: FllgaYLdfDmCMifaIhpfo1FIKGms2Ak62cdIbu0S2AjA7clbHwW8s5YqImYrVY7yKeqoQUxMw8z2Toq7uem2AA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6632 The current `FalconLoadParams` and `FalconLoadTarget` types are fit for DMA loading, but not so much for PIO loading which will require its own types. Start by renaming them to something that indicates that they are indeed DMA-related. Signed-off-by: Alexandre Courbot Acked-by: Danilo Krummrich --- drivers/gpu/nova-core/falcon.rs | 19 ++++++++++--------- drivers/gpu/nova-core/firmware.rs | 30 +++++++++++++++-------------= -- drivers/gpu/nova-core/firmware/booter.rs | 24 ++++++++++++------------ drivers/gpu/nova-core/firmware/fwsec.rs | 12 ++++++------ 4 files changed, 43 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index 31217cd3a795..9eb827477e5e 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -330,9 +330,10 @@ pub(crate) trait FalconEngine: const ID: Self; } =20 -/// Represents a portion of the firmware to be loaded into a particular me= mory (e.g. IMEM or DMEM). +/// Represents a portion of the firmware to be loaded into a particular me= mory (e.g. IMEM or DMEM) +/// using DMA. #[derive(Debug, Clone)] -pub(crate) struct FalconLoadTarget { +pub(crate) struct FalconDmaLoadTarget { /// Offset from the start of the source object to copy from. pub(crate) src_start: u32, /// Offset from the start of the destination memory to copy into. @@ -352,20 +353,20 @@ pub(crate) struct FalconBromParams { pub(crate) ucode_id: u8, } =20 -/// Trait for providing load parameters of falcon firmwares. -pub(crate) trait FalconLoadParams { +/// Trait implemented by falcon firmwares that can be loaded using DMA. +pub(crate) trait FalconDmaLoadable { /// Returns the firmware data as a slice of bytes. fn as_slice(&self) -> &[u8]; =20 /// Returns the load parameters for Secure `IMEM`. - fn imem_sec_load_params(&self) -> FalconLoadTarget; + fn imem_sec_load_params(&self) -> FalconDmaLoadTarget; =20 /// Returns the load parameters for Non-Secure `IMEM`, /// used only on Turing and GA100. - fn imem_ns_load_params(&self) -> Option; + fn imem_ns_load_params(&self) -> Option; =20 /// Returns the load parameters for `DMEM`. - fn dmem_load_params(&self) -> FalconLoadTarget; + fn dmem_load_params(&self) -> FalconDmaLoadTarget; =20 /// Returns the parameters to write into the BROM registers. fn brom_params(&self) -> FalconBromParams; @@ -377,7 +378,7 @@ pub(crate) trait FalconLoadParams { /// Trait for a falcon firmware. /// /// A falcon firmware can be loaded on a given engine. -pub(crate) trait FalconFirmware: FalconLoadParams { +pub(crate) trait FalconFirmware: FalconDmaLoadable { /// Engine on which this firmware is to be loaded. type Target: FalconEngine; } @@ -425,7 +426,7 @@ fn dma_wr( bar: &Bar0, dma_obj: &DmaObject, target_mem: FalconMem, - load_offsets: FalconLoadTarget, + load_offsets: FalconDmaLoadTarget, ) -> Result { const DMA_LEN: u32 =3D num::usize_into_u32::<{ MEM_BLOCK_ALIGNMENT= }>(); =20 diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index 09b12ad546c2..6d47a6364c79 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -17,7 +17,7 @@ use crate::{ falcon::{ FalconFirmware, - FalconLoadTarget, // + FalconDmaLoadTarget, // }, gpu, num::{ @@ -170,9 +170,9 @@ fn size(&self) -> usize { ((hdr & HDR_SIZE_MASK) >> HDR_SIZE_SHIFT).into_safe_cast() } =20 - fn imem_sec_load_params(&self) -> FalconLoadTarget; - fn imem_ns_load_params(&self) -> Option; - fn dmem_load_params(&self) -> FalconLoadTarget; + fn imem_sec_load_params(&self) -> FalconDmaLoadTarget; + fn imem_ns_load_params(&self) -> Option; + fn dmem_load_params(&self) -> FalconDmaLoadTarget; } =20 impl FalconUCodeDescriptor for FalconUCodeDescV2 { @@ -204,24 +204,24 @@ fn signature_versions(&self) -> u16 { 0 } =20 - fn imem_sec_load_params(&self) -> FalconLoadTarget { - FalconLoadTarget { + fn imem_sec_load_params(&self) -> FalconDmaLoadTarget { + FalconDmaLoadTarget { src_start: 0, dst_start: self.imem_sec_base, len: self.imem_sec_size, } } =20 - fn imem_ns_load_params(&self) -> Option { - Some(FalconLoadTarget { + fn imem_ns_load_params(&self) -> Option { + Some(FalconDmaLoadTarget { src_start: 0, dst_start: self.imem_phys_base, len: self.imem_load_size.checked_sub(self.imem_sec_size)?, }) } =20 - fn dmem_load_params(&self) -> FalconLoadTarget { - FalconLoadTarget { + fn dmem_load_params(&self) -> FalconDmaLoadTarget { + FalconDmaLoadTarget { src_start: self.dmem_offset, dst_start: self.dmem_phys_base, len: self.dmem_load_size, @@ -258,21 +258,21 @@ fn signature_versions(&self) -> u16 { self.signature_versions } =20 - fn imem_sec_load_params(&self) -> FalconLoadTarget { - FalconLoadTarget { + fn imem_sec_load_params(&self) -> FalconDmaLoadTarget { + FalconDmaLoadTarget { src_start: 0, dst_start: self.imem_phys_base, len: self.imem_load_size, } } =20 - fn imem_ns_load_params(&self) -> Option { + fn imem_ns_load_params(&self) -> Option { // Not used on V3 platforms None } =20 - fn dmem_load_params(&self) -> FalconLoadTarget { - FalconLoadTarget { + fn dmem_load_params(&self) -> FalconDmaLoadTarget { + FalconDmaLoadTarget { src_start: self.imem_load_size, dst_start: self.dmem_phys_base, len: self.dmem_load_size, diff --git a/drivers/gpu/nova-core/firmware/booter.rs b/drivers/gpu/nova-co= re/firmware/booter.rs index 2b7166eaf283..d569151982d1 100644 --- a/drivers/gpu/nova-core/firmware/booter.rs +++ b/drivers/gpu/nova-core/firmware/booter.rs @@ -19,8 +19,8 @@ Falcon, FalconBromParams, FalconFirmware, - FalconLoadParams, - FalconLoadTarget, // + FalconDmaLoadable, + FalconDmaLoadTarget, // }, firmware::{ BinFirmware, @@ -256,12 +256,12 @@ impl<'a> FirmwareSignature for Booter= Signature<'a> {} /// The `Booter` loader firmware, responsible for loading the GSP. pub(crate) struct BooterFirmware { // Load parameters for Secure `IMEM` falcon memory. - imem_sec_load_target: FalconLoadTarget, + imem_sec_load_target: FalconDmaLoadTarget, // Load parameters for Non-Secure `IMEM` falcon memory, // used only on Turing and GA100 - imem_ns_load_target: Option, + imem_ns_load_target: Option, // Load parameters for `DMEM` falcon memory. - dmem_load_target: FalconLoadTarget, + dmem_load_target: FalconDmaLoadTarget, // BROM falcon parameters. brom_params: FalconBromParams, // Device-mapped firmware image. @@ -370,7 +370,7 @@ pub(crate) fn new( let (imem_sec_dst_start, imem_ns_load_target) =3D if chipset <=3D = Chipset::GA100 { ( app0.offset, - Some(FalconLoadTarget { + Some(FalconDmaLoadTarget { src_start: 0, dst_start: load_hdr.os_code_offset, len: load_hdr.os_code_size, @@ -381,13 +381,13 @@ pub(crate) fn new( }; =20 Ok(Self { - imem_sec_load_target: FalconLoadTarget { + imem_sec_load_target: FalconDmaLoadTarget { src_start: app0.offset, dst_start: imem_sec_dst_start, len: app0.len, }, imem_ns_load_target, - dmem_load_target: FalconLoadTarget { + dmem_load_target: FalconDmaLoadTarget { src_start: load_hdr.os_data_offset, dst_start: 0, len: load_hdr.os_data_size, @@ -398,20 +398,20 @@ pub(crate) fn new( } } =20 -impl FalconLoadParams for BooterFirmware { +impl FalconDmaLoadable for BooterFirmware { fn as_slice(&self) -> &[u8] { self.ucode.0.as_slice() } =20 - fn imem_sec_load_params(&self) -> FalconLoadTarget { + fn imem_sec_load_params(&self) -> FalconDmaLoadTarget { self.imem_sec_load_target.clone() } =20 - fn imem_ns_load_params(&self) -> Option { + fn imem_ns_load_params(&self) -> Option { self.imem_ns_load_target.clone() } =20 - fn dmem_load_params(&self) -> FalconLoadTarget { + fn dmem_load_params(&self) -> FalconDmaLoadTarget { self.dmem_load_target.clone() } =20 diff --git a/drivers/gpu/nova-core/firmware/fwsec.rs b/drivers/gpu/nova-cor= e/firmware/fwsec.rs index 9349c715a5a4..2ba70e0c5a30 100644 --- a/drivers/gpu/nova-core/firmware/fwsec.rs +++ b/drivers/gpu/nova-core/firmware/fwsec.rs @@ -31,8 +31,8 @@ Falcon, FalconBromParams, FalconFirmware, - FalconLoadParams, - FalconLoadTarget, // + FalconDmaLoadable, + FalconDmaLoadTarget, // }, firmware::{ FalconUCodeDesc, @@ -180,20 +180,20 @@ pub(crate) struct FwsecFirmware { ucode: FirmwareObject, } =20 -impl FalconLoadParams for FwsecFirmware { +impl FalconDmaLoadable for FwsecFirmware { fn as_slice(&self) -> &[u8] { self.ucode.0.as_slice() } =20 - fn imem_sec_load_params(&self) -> FalconLoadTarget { + fn imem_sec_load_params(&self) -> FalconDmaLoadTarget { self.desc.imem_sec_load_params() } =20 - fn imem_ns_load_params(&self) -> Option { + fn imem_ns_load_params(&self) -> Option { self.desc.imem_ns_load_params() } =20 - fn dmem_load_params(&self) -> FalconLoadTarget { + fn dmem_load_params(&self) -> FalconDmaLoadTarget { self.desc.dmem_load_params() } =20 --=20 2.53.0 From nobody Thu Apr 16 08:34:48 2026 Received: from MW6PR02CU001.outbound.protection.outlook.com (mail-westus2azon11012042.outbound.protection.outlook.com [52.101.48.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4E6721772A; Sun, 1 Mar 2026 14:04:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.48.42 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772373858; cv=fail; b=p027SR3XKcToMh6YzA52xoTBZbvnD2nF0VNPhBpJ5ihTB9+34xh9niq5Ycvpdtcx12QW70Zhjakd94Wnt2YdX9RdjL/QOW5d9gYTpmEIvEeQ1OU9UZUnX7vRdGC+tpCtdb9My5XofPBplxwe564pj/39X7EpKSr75yrbqFQGVmo= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772373858; c=relaxed/simple; bh=qwOBTqAainalTSOjInAkDZRMTa6x8PrizTuwYAFaNTM=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=JLANbVMVnM386cgXjBZnZeKEpMq8XcGMRFF7BKW1qxjZNMjo93PgHd0yfDVH6vAuRQ0sueclgx6iVwBR6eT9t/jZIjtNI6apu/B92bEBmLdrYoCfnZ/1VT2Zq3d4QfkFg29zCiE6iPi2gt1sCTKoA31eCifb8kLFriS4fWQih7E= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=fzmUZmxa; arc=fail smtp.client-ip=52.101.48.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="fzmUZmxa" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=FLYIHat0Ya4Z/4NVT9ntSbwSzqgbGhsyT2LPtgFmnIDLN/3X7RsKnL4GURZwK45vy0hGl/CnnRFSbYxbUj9PuR+B5hAm0gUOApvvOMOOAHo5bruwnrzTnnhntSPcUQbtY9rPmIq6+WYGz7GsKYf2cfBVx12Cp/gNQpqpw1LsBw6mAOy9WGHMQTGMvQYwu7Tetgf+p3oscjgcXX79OAkRErMsxVb7D7OHPyMgfFDcaT2Wp4Iijl8E98vwskRGj2A9QBovmjjzbtMoeB70ZbPTz79Jo7YO7YkLZI35it8GSc5I4KbVgo1gAZzG/PDdwubW0hwZ+EYJLqvroTf/kt8ehw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=X8fTxnCJW32zkvMORNZsJWwmK7aIi+K0a2CEi3QfKGQ=; b=g6aDRU/VgsFCmq/revesMCwDaAR8+ug40sMmAc9m9wgfoZkiJCb+sdf3fizDTk6j+F9t0TGQ3KdJX7KPvX0LTM0Ik5giEJD7Y+wALNpYFG2UwqEvaiq/TZMWjHpZ2lAj0AvYi7WF+M2hdRxfTUFPAqZJF2/V69O6KqVNAKbeqeZaoyMmyUVaxf6YsWSFkLUIVo6vlO8lbw6giVfl56tktyZT2LGjuaOj89UrSYS5QO9e375S30q0OCLihC3uqZ9qr/PIRsZNwZ5GhjHVfUldTn4kVOuakjKaBIBGjN2RgsDtG+CBotEkyWvteNwqxsa9KJFISaR3cmpeSMrrsJ6dyQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=X8fTxnCJW32zkvMORNZsJWwmK7aIi+K0a2CEi3QfKGQ=; b=fzmUZmxaVjZ2/8NCv3NGswPqVYmvSCcdmWVN928bruklp+thTE4rNXCAnrIpKLFJXWZjzZPonAmaj+pazysPTg+F3tg0IQeotYtD8N+kRL6GoxNYlSQwQrkxeZrRiPBd3EIuOFptlWc4ipiXekqKwnbZ1b6hyByOJIg2fRkC37mZWEviAnh7yuvWHE5lOpJJSX5/vdI5HnRLgI1pWmToHZeO+R3R7jK5yosejgNlWyGGhgEqcLvL1Rj1U0ujwyPlwA7K9VNELHz3oby7le1RPbgTBUHdmRS6HnXCrUHRYbZ70hEjDUPpX2QHQpVQJ7YqQ1JFHoBt1qMD2wTv7A3WUA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) by DS0PR12MB6632.namprd12.prod.outlook.com (2603:10b6:8:d0::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.19; Sun, 1 Mar 2026 14:04:14 +0000 Received: from CH2PR12MB3990.namprd12.prod.outlook.com ([fe80::7de1:4fe5:8ead:5989]) by CH2PR12MB3990.namprd12.prod.outlook.com ([fe80::7de1:4fe5:8ead:5989%6]) with mapi id 15.20.9654.020; Sun, 1 Mar 2026 14:04:14 +0000 From: Alexandre Courbot Date: Sun, 01 Mar 2026 23:03:47 +0900 Subject: [PATCH v10 04/10] gpu: nova-core: falcon: remove FalconFirmware's dependency on FalconDmaLoadable Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260301-turing_prep-v10-4-dde5ee437c60@nvidia.com> References: <20260301-turing_prep-v10-0-dde5ee437c60@nvidia.com> In-Reply-To: <20260301-turing_prep-v10-0-dde5ee437c60@nvidia.com> To: Danilo Krummrich , Alexandre Courbot , Alice Ryhl , David Airlie , Simona Vetter Cc: John Hubbard , Alistair Popple , Joel Fernandes , Timur Tabi , Edwin Peer , Eliot Courtney , nouveau@lists.freedesktop.org, rust-for-linux@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-ClientProxiedBy: TY4P301CA0116.JPNP301.PROD.OUTLOOK.COM (2603:1096:405:37e::19) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|DS0PR12MB6632:EE_ X-MS-Office365-Filtering-Correlation-Id: 85ab404d-5b03-404b-5dc7-08de779b6bae X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|366016|10070799003; X-Microsoft-Antispam-Message-Info: LqttnEfljTENto2so/xIcpMpmgxijwg7+oQXm5Jr42pxCZ1pLAr53K1WuAdCoJP5LbgV7CvkSs0gh7/8q4wXJ7gwLTdjS+UJk29KzG9me8kIAIjdtuHyn3IoCWBWHMoT41e5a+gztg+FhipCbiPowgUdjcY4EThafR/1nehUrPjfWSyP9Y4Hgu4KNZbCeurYSc7ISweto9iQdrwP8gJ7EHTksYoJUQMmfIH0gNizRrX03l2OPZa+ELn6s+vP5NXg+d7Rf724qfeorMXjyHiHDv0ZtpQr1z3l5sEw0rgP4JULeSTXpIOFEi18l/jsojxsEf05AfpBoM45BgVjbRPhddxif5KhYan9GW6w0WWHybIQqP+/x0jp89AUXE5tyzrxB8D5FODPc5b7HUr5BsSLdVeY1hzJ2uV0pbOn8NEo4OCvtq+yiRhVKRfUN4tDb/VcRqc4Hn6tc1Z8d+msuyc7/Xf5y+5DDhAuEAyfSN/cizhstjMyt8SQLuScZi5AoXw7DszCnhHSITFUiGGtGLP7TadBO0gVb2gSCimq1m2kwqYBtsKzO/SWm35j2p8i1kwvVa0PHsuB2AvZtkqeiw7EFEO9jwBp7K9KfjqtN/aI2TaPfeeUlbq/s8xj2bnzkc4K5MJIAQcPYCYXmX4F+plR+xO7lRknCDMvNEmCSg8+da87iblFIce5CriJ22CxTujYxXi2jTYmbJRlUWNt2Fu4avQxUq6OhMV1xtd4CiL6tWc= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CH2PR12MB3990.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(366016)(10070799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 2 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?Y3JwMzZoOEhJMXo0a0hUblFYbVdsRHltWGN6bnU1ODdDbHBjbTNFSDIxOXRw?= =?utf-8?B?Y3Z3MUNHblNqZUZIUVdCU3crNUdCREdlK2hsMkNKa0pNYWxyZ1p0bjNrYXpo?= =?utf-8?B?L1dUZWdJdFNGRm44WlBRSnBQYWFVbzVPYWpFZGZObHA2MThsbGl2ZDVqN09m?= =?utf-8?B?KzJNTTlPOW9yQ2c0UTg1MGY0anQ0bjhRckpadDdYTlp3aWR4WWlDK2pqMEp1?= =?utf-8?B?OW5USWdQRGl4bWVubXVtS0I4c3orR1JLS2dBekNlVDVBWGJFeklmUUhCUWY3?= =?utf-8?B?S1I0Y2NOQU9Vd2x6MmlNdExMUGYxU0Y4aWM3TEVTdElZWjdYWitkaWNsT3Ju?= =?utf-8?B?Wnd2R29BQkJUK0l3M1plV01ZUGVCcmxJNjgxSEwyS2hGRlZld2tkVGVGdHVB?= =?utf-8?B?NWNYam5BRzJmeE5aVitrSUFMSG10QVMwbWI0RTRtODBwcmxyUVNLYzhKdjVr?= =?utf-8?B?Y0NWRzVBM20xT01lQlkvTTBwTnl6dGk5QmlGVHNFY2tNcmNraEtST1lyL2tV?= =?utf-8?B?RWtuMUt3aXhjY2c4YUMrVmgwR2xoaCs2aFJzUmtCQU96WUVXS1FtNXJDMmhY?= =?utf-8?B?VlQ3MWhuNHI5RTdDVlN5emhwTnpiL3lpbklkOW9mODNNTy96K3dOSERtMWlu?= =?utf-8?B?ek5XNndXZWVRc3MwbFFZQWxsc0djM295UTRYWnBhZFhnZHJZakFiWFVYTWpp?= =?utf-8?B?N25ib2IwckgzL3pleFpZbEpiUXA0Z2Y5T2FGVVYyU09HOWgwOVZpNHJGVXc3?= =?utf-8?B?NzJtYmJORWNkTDBjU2xxVHAwR0crcXU0Q0Nqa1JuOUFxcUJCWXh1bm1HS0tL?= =?utf-8?B?R3ZOb3ExRm1sM0wvU1FIVFZkejVmT2JtUkdwRW9mZGFETHRQSUc5c3JoRVZy?= =?utf-8?B?R0dDd2hzQXRKdk1XbzRNb05ZN3I3Y3J1WWx4MmlnZVdrcWxYUERUY21LS2d2?= =?utf-8?B?VllNcytXM1RBcDVUUC92UzZZc0ova1N3dmJpYkwxQllJb2FKczZBRVdGUklQ?= =?utf-8?B?ZFJKYy85TlJzZ2NqeTV5K2FsODlYYnlKZUpwcWlvcXRiOGxocThJRWlHYW1L?= =?utf-8?B?dUozTSs2dlFjY0w5dy9tVW01RjRsaHhKK0NEQUJHSnlmeWpKWTk5S2F0eEg5?= =?utf-8?B?dW0rL3llWjZXV1ZrcmVTWmRVYWtaUmU1eFVENU9pUTVIeGV6Q0xLMHFjUjh4?= =?utf-8?B?Q1lCQkE5TlZzRzNMUlNZZlgzL0RSVUZEdXJOQ0VXSHRpWERGeTlicUpBVmxa?= =?utf-8?B?OVJ0WlhEOEo1MVUyQndvRGZSbXh6cFNGMVoyL0Fyam5SSlR2V3ducldXZHdP?= =?utf-8?B?clFmeDExcnplZ0ltQmtBY25HT3NVRC9ielZ5SXhnYkJOdks0d1pBVGpzVnZE?= =?utf-8?B?U241V3I0dUlrRDFxWmxBcm93NjZicVhkU1kwZk9wNWNkaDNEMGdML3FaV2VB?= =?utf-8?B?KzB4MTN0dHkrbXlSaDVRSDFHLy9BUE9hM01MYmVNeHdZNWppQ3YyWVlTUGJE?= =?utf-8?B?YS9hR1N6Y1ZiWHNzQk1hWmZXcXhFVVNwMmhuOFlxMVRwQ1ZlR0s5NmRyWHVv?= =?utf-8?B?N1NzLzlCeThtUkxUOUFGUHJibjdHaUVqenFmUFduc1dVYkVlMVdvY1ZDN2Jv?= =?utf-8?B?MmdvQ3Q4QWRVQk13MTY4ZjcrejZiTHJXUVArYWxlanVZSzM0S3hkMHFVYlJk?= =?utf-8?B?OXp4dHVLeWhwbEhUeU9xQlg0ZUFZSjBMR3lFT2t2ZnYycFJ2VXl1SmxTbHEy?= =?utf-8?B?UHRQZ3hYOGZCSG01aXNZS0pNQnE3endmVzRJcmhwNHNrcEs4cHROMUtDT3ZB?= =?utf-8?B?c0lDakwwczRmeGY0VnNxYzREVldKT1RaSDlCeFBkOFlncm1FV1FJSmxOdnpB?= =?utf-8?B?c2hySW9vSytRbXBhd0IxT2JGZWJrNzkxZnlvNk9IdUdOOERWNnJrTFlkMjhz?= =?utf-8?B?Z3B6OUs4Sm4zb1dIR1FsdmZjcG1UV0tJY1VqRkxGMnZlTjY3YS9LdU5mOWlW?= =?utf-8?B?Vk1ENTB4eFZVZmFNaGNaUktWLzV5SEp6ZElyV0k4QTdJOHlIM016WjFXY1Nv?= =?utf-8?B?YUFaNXliMU1YbTd0MWE0YU03cTM4OGlRb2hOa3dFOTFIYXVwZ1o3Y2RLNXZD?= =?utf-8?B?UDBRR0VoRURDK1ZPMFY5OXJIcUdGQlIvK092Q2cwL1JKYnVBMVFkSlJkWkw0?= =?utf-8?B?UDJkSlpPblh2YWtxSVFURmR2K09XakhtaC9KS3BxQmdTNzBOZkRsTzMrdC81?= =?utf-8?B?THdDd01oM291K0RUY1E4YUtnYXBSNnROM3BqQUIwZ1c3NEEzNTE0ODYxL0pW?= =?utf-8?B?ajJEaVhnQ01kdTFZenY4NFd5OXRaZ1Vab1VSbmtwU1J0Vkp2N1VRQVlnVm5W?= =?utf-8?Q?wdtEO4OHtwdGgVh4rF0UehYXERSCfAJUHTomB1hf8JGX1?= X-MS-Exchange-AntiSpam-MessageData-1: cKieQKDyixw+7w== X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 85ab404d-5b03-404b-5dc7-08de779b6bae X-MS-Exchange-CrossTenant-AuthSource: CH2PR12MB3990.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2026 14:04:14.5767 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: OXNVo1A1Y3JEOpeehrijoRO/ps8guhW+p0XsChVo9nu3fL2V3an19cUVELxd9THKT/41jMI7tjJavO33vUMmqg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6632 Not all firmware is necessarily loaded by DMA. Remove the requirement for `FalconFirmware` to implement `FalconDmaLoadable`, and adapt `Falcon`'s methods constraints accordingly. Signed-off-by: Alexandre Courbot Acked-by: Danilo Krummrich Reviewed-by: Eliot Courtney --- drivers/gpu/nova-core/falcon.rs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index 9eb827477e5e..450431804e1c 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -378,7 +378,7 @@ pub(crate) trait FalconDmaLoadable { /// Trait for a falcon firmware. /// /// A falcon firmware can be loaded on a given engine. -pub(crate) trait FalconFirmware: FalconDmaLoadable { +pub(crate) trait FalconFirmware { /// Engine on which this firmware is to be loaded. type Target: FalconEngine; } @@ -521,7 +521,7 @@ fn dma_wr( } =20 /// Perform a DMA load into `IMEM` and `DMEM` of `fw`, and prepare the= falcon to run it. - fn dma_load>( + fn dma_load + FalconDmaLoadable>( &self, dev: &Device, bar: &Bar0, @@ -660,7 +660,7 @@ pub(crate) fn is_riscv_active(&self, bar: &Bar0) -> boo= l { } =20 // Load a firmware image into Falcon memory - pub(crate) fn load>( + pub(crate) fn load + FalconDmaLoadable= >( &self, dev: &Device, bar: &Bar0, --=20 2.53.0 From nobody Thu Apr 16 08:34:48 2026 Received: from SN4PR0501CU005.outbound.protection.outlook.com (mail-southcentralusazon11011042.outbound.protection.outlook.com [40.93.194.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F84C326952; Sun, 1 Mar 2026 14:04:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.194.42 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772373863; cv=fail; b=NB4QS1AdH+FTobUbnJwjTPF/yV3A4IhyhCrgWEYg1hFzaJokyTcZ7wXFQ+t4XcNTSRTnGoYm3nR2MWyfmYedI/C1xOESjG/IfMKqlPZ6/6Jq5cMm1P1aTIWWPYssyyRIfuTolqy4k0IoEcV32f/WodUvR5Nb8iRMfptte0koMe0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772373863; c=relaxed/simple; bh=pCSpKj5qBZGyRQWq6WPT7+fDeT7/gmP2uBznyz4HYtU=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=kk/mAEFeR4Qqwix+6PdSjRPHoXXLjYjQdVK4Ce8hwM64BXQfjZ/8qbwibk73Qpt7iDZfw/1FAkXZacLEdYXfMLtEa8rrGb8LnjYpgUjapa7NtSZS18xhp0pOslp11Ao4xaQLiqUxnQsOlt2R5AyhqmwPo90FNoZrMsR1thqleEo= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=r98JKGV1; arc=fail smtp.client-ip=40.93.194.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="r98JKGV1" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Os8v9PXTrBxrqL7hhtLiGlD9NtSajhgZtAA1r4Dwo//Y+IBdbD8hHigcl74s16Ne+NUhPmvO6wnDgFvqFY6TUiIo6FB++xwxlr5uHGPYaZD/exJJaJlieKBHmkmskGkSlgTp7du1X+S6usJ1KtQlxAEufElRK4NkSzVGMIfIujNe8tQ94aE6+uaCzqphQGYFcMRz9WMjPeSnLoci0tUYrND6UJqP7syz6BpRuy5M7+muYVEtwA9Lvtd2FibSz+FEH7bwq38qtshk2FFTKhX45xtCzZ4GbUEazq1mJGqKjE03FqGLFLqSxjG/SF35xqwc6AUKCUTBnOOmxsUbJyZLCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=DqHgG/IphMPhH8T5g9qPaerrFfdXnk662HUzwWUs2ow=; b=WppFPEtDSNMHsxX8w4HybMKqpiRZNpezYrV410D6Xp5yrtQ7AbfDErx7u6Jy4f/As/OcWaby2AMX0tEI9rA/il8AkTmiaT7kjSCMjaIdTCHWcM7vuXykiNpdF0+ivsnd3ohdZl7MnKih0Qug7PtDDS8hH2YrMYDXYVmAj1Ywx2lJc5wl6YjMXoqNMh5f4+LcWM2445DlwG7tQPhnUv3W79zIZjSOmTv3ZAg0MdEu4TXH5+CHaLdi1HhxQQR7Wti6nZg6AQM0XUiA9IX71Zyj9C/BqDGJ49IvCTTOdnhzGKxN6Yd96+B7qo0hbQGyQ/2IWWQdFiMJp1BJmxHZUwOAUg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=DqHgG/IphMPhH8T5g9qPaerrFfdXnk662HUzwWUs2ow=; b=r98JKGV1k3O/lFo9Lfs0cV2xddiaNzlMf471qzQaPGBOTj2rwLLuqiNqyvtSQ7xZ0W9dEtXeQQeGdPVmDqAwab4+2KXCMByk58nE8BF3Y3uHYbvgIKh2R3w1VIgMiuZgytzSAox0lvXlmaRulGfcK/997sDj2Y2E4xS6/y1E4E76XWQjJRsrzl5s7uEsChBY2lQmTP54QPga0zFiQgcLbcsxEe0TMKLl3ZIhzMIXFheFusyBVjoYekuYY5LyU60TTScKAX7EX4Fz+ywiS3o+wvryBUawiaG4LpZ4CkOfhLFKllHtUG8fbQxwVMV6mjUHTkM8+TVcrJ/iglXpBNh7ng== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) by DS0PR12MB6632.namprd12.prod.outlook.com (2603:10b6:8:d0::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.19; Sun, 1 Mar 2026 14:04:18 +0000 Received: from CH2PR12MB3990.namprd12.prod.outlook.com ([fe80::7de1:4fe5:8ead:5989]) by CH2PR12MB3990.namprd12.prod.outlook.com ([fe80::7de1:4fe5:8ead:5989%6]) with mapi id 15.20.9654.020; Sun, 1 Mar 2026 14:04:18 +0000 From: Alexandre Courbot Date: Sun, 01 Mar 2026 23:03:48 +0900 Subject: [PATCH v10 05/10] gpu: nova-core: falcon: remove unwarranted safety check in dma_load Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260301-turing_prep-v10-5-dde5ee437c60@nvidia.com> References: <20260301-turing_prep-v10-0-dde5ee437c60@nvidia.com> In-Reply-To: <20260301-turing_prep-v10-0-dde5ee437c60@nvidia.com> To: Danilo Krummrich , Alexandre Courbot , Alice Ryhl , David Airlie , Simona Vetter Cc: John Hubbard , Alistair Popple , Joel Fernandes , Timur Tabi , Edwin Peer , Eliot Courtney , nouveau@lists.freedesktop.org, rust-for-linux@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-ClientProxiedBy: TY4P301CA0114.JPNP301.PROD.OUTLOOK.COM (2603:1096:405:37e::12) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|DS0PR12MB6632:EE_ X-MS-Office365-Filtering-Correlation-Id: b5ca7dd7-5ace-428c-7ecb-08de779b6e22 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|366016|10070799003; X-Microsoft-Antispam-Message-Info: H/1EZHdyVfiNsk0jr2VXi6gIzr+0Z1viXPwSgtsm1190tKyhNJwGnVB9UaybzQ3+2OV+A9gaudRti7SNYZkA/gam43NKFqif8+z/tVoGD9fLBfs3ZImMdE1EkpGMeJvnVxXbqCI43ebarp6rphbmYjPm572kAivUj58/z4nhaQkd2ivgKWUtIq1H+BXKpSJnQ8/iP7/vL4bx/KuItamikhC+HlvJaDHNZUWXFnuyl7YBcfUgdZsMsIGP2fZniCE0pn+5oFcKQm04wtMcQokIlkQ7fPVxwZ6bjHGLUs03Hp/+481CqyonR0bC30YPthRGEuBF0Ng3caKAxZNx+Dr7jRO6G6QJR0H40MG7eKZQdYpQZHLeRoxX5cxqcRTtUjlL0EnEz2zjOGvJrMikSkzp76tmMJlf7H/UPEs0Gk45orYKVrXMGLafwt/9UkyLyaOlNQBiCSvNZHgv4mRr/2yKZ4/u5GsgvqqoXfhdaK6Qh0q1skZgxB353NidBHZvX4GLwscqfz6NGc9gaR6LSDalp1bdMyyPY6qaY10iHzNI+8dDG3ZvaN8AKcA0aXnrb0LrQULabT5vXOxkInie3gaevnLuOFliDlbQ05kjbiNoUo9QR9LEmoxZ7ynNRhfa8UE9mbWHvhxg/Dpia9yJDnMyjPtn/CQtDnJD7ecXz0bOW/9jYJaueOFyFg5aXfMw/nRxNr0Ck7XZmljxZcHvA+O4sEWvjelvcsjYaEw5GxsO6a8= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CH2PR12MB3990.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(366016)(10070799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 2 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?Z3A2WUlBbkpqQkdFWXRFemUvWmtLVmZFU2htT0hvQkp6by8xVVROR2VqNTdy?= =?utf-8?B?R2Q1TU9wMG1CaHBGak1VblFlQURIL2ZLQ3FpQnNBYW1ldTNEc25MeWpjZlpo?= =?utf-8?B?QW8rK1VDUXMyaTRRS2I1UWVCTWlIN2pycmtWaTk5dFpxbnNTbWRzckFFMmJa?= =?utf-8?B?ZUFDdjRreFZiVGQzVWtUT3NtUS9lR1d0eVF0cXgzTzZsWVNhRDVoWVNwYjRU?= =?utf-8?B?Mnh2Q3N4eVpsTkxzendZd2d5NlJJa1N6NTJsWGdWQ0dHRHA3Rnd3VWNoeXVi?= =?utf-8?B?aHFUczdoM0l6YkdWMWxCZUhBSWtRR2ovOTlUUUora3VvdFptWXVXNVJFQlpX?= =?utf-8?B?U1JyUjhRcDFRQnJtdjhUdG04YkpxRmZDV1c2YWVrcDJkYVhVQ3F6WjlKRUxO?= =?utf-8?B?U1B3dHdhaVVUTTdFZTErNEQvaTE4UkN2bC8rZmgrZEd3czVuaERuT2xnK2xo?= =?utf-8?B?aHAwblBEbHJNWFhmK2JacFhkSkJ2YU9Zc1EvVE5YR0k4RzZqR2NObTB4NXZp?= =?utf-8?B?dWhob244UWhXMmlFWXNYSVdDU1pMcHVoL1F5dWU0Q3IvV0NKZmtYdmFOdkNn?= =?utf-8?B?NzlhWXQ1NnZtblNsVnVneWFMQ1JXS1pMTTFZSHNhVzU4aDVIaEVFaFo2SHdL?= =?utf-8?B?dWRUaUtnS25XSXZyd1VmamNxZ1crTklnOUVhMHdLUzRkcWRTemoxQVRrVjNB?= =?utf-8?B?aGVDUFQzZXJ1OFRPVnpZQ2xXS3IzUG5lQ1c3VjhqK0VOWmtvWGZTcGNxZDJy?= =?utf-8?B?NER1bG41S0F2MjdPY3MxZGI2M09KL3JYMVRUbDY2NFBRNWFYYnNhREYvUzB0?= =?utf-8?B?NnozZ2NPWEJHb1pSUDBDTEpFTk9kZzZ6c3V4STdoVmhudGZKNFo2RHlweFJ4?= =?utf-8?B?STRhOG45M0dpK21xcnlneEFFdzR6dTZsdEV6WlZGZXhNc2daSzl6SDMwSlBL?= =?utf-8?B?U1lEUTRnNVNyVTd2b1pZOG1IUGJKUDcrQmRmVHZoODJISUtZOUZycnNQb2RL?= =?utf-8?B?dk1zanlBbFNBdUdHY2RySldtTmFiejB0SzEraU9kMXN3TTU4MkdCYWZHaHFV?= =?utf-8?B?c05uSjM1UTBUam5UNERZNkVyRmEyMjJqUnJhZWlrNlgxaXlYWnFWWkFqWGdP?= =?utf-8?B?V0o1MUJuTk1TVmZVQ0l4Y25zR1RIU0JRMFlyYU5RUlF6VEZjcjM3YUlNUXg3?= =?utf-8?B?aEwwdGxGYzYrRG8yTVNKV3Y3SnZmb2VQTmdQQ1pCUHEyRzVIT2FwVnZxMmh0?= =?utf-8?B?ZmsyekIrQ29NYVIveVdEUzBoYjJkK283Vmd4WnpvY0MwYXIwS3RmbGlDbHh6?= =?utf-8?B?R2lVWkU4djBITTl0THBQRFJzVUJMU3pLUzZxVE9MRmRZZ2FqSWRkOU9JMXJs?= =?utf-8?B?aU5FOStpb0xGZ1o3SjlVOWdlNjMzaUcwNVpBcitGL0xLTXAzNmJhb0FoWTdi?= =?utf-8?B?UWNBTmRjZmUveXNDZG5hdTI2K0tISHBONzRoM3Jsdm5xc0NjaTdUampMNFBC?= =?utf-8?B?RTZnWHVZYS84WElydER4N1dlQWVjTVNwWUsrVFFFOTVXb0RMbnBaWm5ZZDVU?= =?utf-8?B?dnlsd3VFZWd6YmwyU2dTemVpbFg5TVlnbW11OW1MODVVSERLUVdGeFBmaUUz?= =?utf-8?B?Rk9ERS8ycnFZKy82OTd4YzZybkdKdmhEVzlNNFRnZFJQYnpta0p4MHdFQW9Z?= =?utf-8?B?TmJRNExXVkdIVzk3K2lkU1BNS0Y5QXJDNzN4eW1DTWg1RTkvUHhQbUxSbytL?= =?utf-8?B?YWJqbitpdS8wOXg1cnZybktjWTVCVC9Ka1BSNzJYeUVCTXZaQ29kZmYzbENM?= =?utf-8?B?WUllbVQ1WXlTaE5xUFJSNHhQRS9XeW5EcExLV3p0MWk0SjdIUEtMMng5S1ZD?= =?utf-8?B?cTJnak8vQ21pQklkV2k3Z3pHdVdVVlU0d1ZFTXgwN1R5ajQyM1poZTYyVnNs?= =?utf-8?B?Z2ZPY2JybHRrMTlFR25MSHA3UUNvN1JJN3RDd1dEKzRBdDlFOXpIQkVlVG45?= =?utf-8?B?ZHpxQnU0ZkhiSzcwTTloUWJkRElFNi9MODhTV251V3hQZ1ZZV2JsMjhrZUF0?= =?utf-8?B?ZG8zdGJMMjQybU5xMzVxaWF4RzU2cFFOQ1FNTklXd0hIR3ovNkxwOTR2YzVj?= =?utf-8?B?Qk44S1V6RVpkWUMzS01mbkkxWjJiZDJBaTJDYmIyQlJ6Q2IxT2xFN25OUDAz?= =?utf-8?B?N2ZJaHlvc0RmUmxScWw3WExkRlZmTTZkYWkyci9GNGZoSVg5bzA4MzhwN2N3?= =?utf-8?B?Z2FGWVZyWjdSdUFnY1ZXOGYxdmF1enhoWnN5MHNPV2c0YW84UGtsdEJHQk9J?= =?utf-8?B?NVZXc1lpL2kvUDg4ZjkvdmVrYmdZMXcweEcyZmM3T3p2a0VRVjVzNHp6OGh4?= =?utf-8?Q?drqHD2nSgLlx4vajKIR9tXpFSpc34m42xZ0qEx4w8cVNQ?= X-MS-Exchange-AntiSpam-MessageData-1: mlaTmKC9tJtUgA== X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: b5ca7dd7-5ace-428c-7ecb-08de779b6e22 X-MS-Exchange-CrossTenant-AuthSource: CH2PR12MB3990.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2026 14:04:18.5740 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: iOpckmCtzYLdCOd+hMk+6179N3Eosx5kTenx14kik/2BC8x58vBLqs8309Gq/SZtK+aZ5eLzlyHivcKqt9Djhw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6632 This safety check was an assumption based on the firmwares we work with - it is not based on an actual hardware limitation. Thus, remove it. Signed-off-by: Alexandre Courbot Acked-by: Danilo Krummrich Reviewed-by: Eliot Courtney --- drivers/gpu/nova-core/falcon.rs | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index 450431804e1c..c02b73b1cfe6 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -527,13 +527,6 @@ fn dma_load + FalconDm= aLoadable>( bar: &Bar0, fw: &F, ) -> Result { - // The Non-Secure section only exists on firmware used by Turing a= nd GA100, and - // those platforms do not use DMA. - if fw.imem_ns_load_params().is_some() { - debug_assert!(false); - return Err(EINVAL); - } - // Create DMA object with firmware content as the source of the DM= A engine. let dma_obj =3D DmaObject::from_data(dev, fw.as_slice())?; =20 --=20 2.53.0 From nobody Thu Apr 16 08:34:48 2026 Received: from BYAPR05CU005.outbound.protection.outlook.com (mail-westusazon11010053.outbound.protection.outlook.com [52.101.85.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95CE02C0F84; Sun, 1 Mar 2026 14:04:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.85.53 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772373866; cv=fail; b=NAH94hvmpd9Fi8bHz8QjmxugATXG6YG9U2sBbPrHv7HJwDOUyh/RL1Es9cUZmi5ZZ4O/EM4kGryMXtQmsDLIOVy1Vu6nDj/Bx5PXUMWFfxIKaMGfSxBn3MwSbwKl8q3QppCNfuzjJ/9pNl2cTSmlzS5o0nWpy2SWd+sAIzpO3+g= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772373866; c=relaxed/simple; bh=Y8Oe17Wn0/gORB9jmlkfeyn9wqUYp0QrkVvInQ5wt1o=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=oKk9zibD8cyB43ULyaD6s9NSbeZShtqCQ8VpTlviL7aTKwSDIzC366RfYsrixR5dQBTudN1NM6nbLmy7cyuQmhoRoi3/dKAloNZGL7U95n2e3gtc7H39MGYwA+oHIb/At3MGQNSUbsA+NgL9Hw+aaXy35AufaW7APT7zuoiwuI8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=Z+/K4iaz; arc=fail smtp.client-ip=52.101.85.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Z+/K4iaz" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=mvhvTJPtEiIEuRh4XBuJKqYeVoPJGFLJv5LXn3b6zOT9nbRhXnemHc7dbhCUTwyzzHHnFVGphLWjKPaTpudw0XphQG8rLsKmjryN4k6WqGZ4b8dEqTgoaQqdN5UFATzxYwenX4MKKQYObWZisYvmn7KL5zvmmkTFrMCadl6m4aOx6PfzS28FfNiR20wt7PmvdiVoTYxtL/uhtCjnwJP/y7xFuLJYSWBnFwEr4d7354CNFB3tGzsf+y+01d/an7A2CENq9mCvIr3cRAtBDOsYfOlYMdI448VnZQVynlaBB8Iofo4tHp1uksna0lkDcSf67j7xL5Y2zYgP6WXOJ3CJbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=s+X5sNU6wYFcq5pGXZfVIeGBeYeVrgsV8nc6nc0dHzQ=; b=JA6cu/SKl4NdzeKdE9w1rCzMaaSKk8XgT9kOiEW1GXes7sphiEcxFBvC5BVBNoge7SZ24Bl0h/WjZOI3opqKX3+JRA3dcWn4JeCMq+2tMPYjZxIDPY683S+al/XT0cb0au6e4eUUOQFDlTPagDdgBswj3kDsc9rLpMK/K+AqABD9ZkWbe9bbYvhXLhcspD5oXpIjmoas4HUQNsIXAxJB4pEoO7ApLBoDXukCS4bnIKu2zjbbNVqhn7kh6uIqPmZCRIMeH8kxGrTeDl1HLdajS0ceyZz73pDfNJU/aueZwEeAlvEGDzhu7wC9bpHTxKvIIeiPziM69Hyf3NMAneCXEg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=s+X5sNU6wYFcq5pGXZfVIeGBeYeVrgsV8nc6nc0dHzQ=; b=Z+/K4iaz9AOfiJhhvh7+PPmPUfpGvxJjXPlD3ISpON97taHVwCSctgS52CSL4ghvgXUUyqm69CB1T2pDe8EnbrxenTM5mdyKPTUXzP0GBkMRkbCIkc05fZ/i9bLu38wHqhtyWdiYEKz3CoLvp5vnUFpehE4JljAZxzSHSVOsYZEw6+ZuX5DAJL1mVNPIFSAa/AVLwN0qyx9FDMzEMMQUEz9oRFIyDAH08Y2cnPJu/MeES5YNdrqUrpvsV4TeJtN/BOX/xluKdFpOJClKQw5lhz8oOLlviZ5zHZcliPKnqQruTlsdD2FU6hIbCxPCYcaYAjJtlmi1g+bms+rHsYrSUA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) by DS0PR12MB6632.namprd12.prod.outlook.com (2603:10b6:8:d0::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.19; Sun, 1 Mar 2026 14:04:22 +0000 Received: from CH2PR12MB3990.namprd12.prod.outlook.com ([fe80::7de1:4fe5:8ead:5989]) by CH2PR12MB3990.namprd12.prod.outlook.com ([fe80::7de1:4fe5:8ead:5989%6]) with mapi id 15.20.9654.020; Sun, 1 Mar 2026 14:04:22 +0000 From: Alexandre Courbot Date: Sun, 01 Mar 2026 23:03:49 +0900 Subject: [PATCH v10 06/10] gpu: nova-core: move brom_params and boot_addr to FalconFirmware Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260301-turing_prep-v10-6-dde5ee437c60@nvidia.com> References: <20260301-turing_prep-v10-0-dde5ee437c60@nvidia.com> In-Reply-To: <20260301-turing_prep-v10-0-dde5ee437c60@nvidia.com> To: Danilo Krummrich , Alexandre Courbot , Alice Ryhl , David Airlie , Simona Vetter Cc: John Hubbard , Alistair Popple , Joel Fernandes , Timur Tabi , Edwin Peer , Eliot Courtney , nouveau@lists.freedesktop.org, rust-for-linux@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-ClientProxiedBy: TYCP286CA0374.JPNP286.PROD.OUTLOOK.COM (2603:1096:405:79::9) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|DS0PR12MB6632:EE_ X-MS-Office365-Filtering-Correlation-Id: e6c3cdbd-8840-4d94-9b21-08de779b704c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|366016|10070799003; X-Microsoft-Antispam-Message-Info: 93RuhsVdYh/6/IHzhoctnKlLxrEcfghrjHN82th1vA7J6GBqWcwHYOl8A1bCOzTyg+zt8ZiWr2areI2uo+isQoElseC3fO8J/Xojo2bOupH51zuMF45sUxxgdPCeskMJchzPOk8RxGNeG2Irzl5Im6oBG8wvasIKYod6YZm3ud+PEYMGnnGh7DanZ1MXCnowHhwmNelaQcZfuWmwfO7d+7UU+ptI6YoJU/kNujwDJ5fhYchAXJn/qskC2o/jMsIDFg9g0qpdW4GJN7huVLBHecuPx/9gno8QphjwCkleR42N0pvlU1JByEt0pjPwudliNugckFITU7mmWXoo09giNPqXj1QURnGdKxCtd0AYOzIKCFrf4QoXMBM0k2XYJ0/lvUbBDYNsfLyOTeRf8T+aKYVAXU4NtAbgBRrwDPKSeEPg2fd+w99XhIdpq4zl03UZFFb2nH4mMD1Dvok2u0B99LmNxKBXx58xJKgh2pfpJDfUNVM9vtUiSzL0Wf4Hpszx5Q7j+VXITBPU42Yv1ARO79FAKUXAZnw6l94gdQrep/IbCQruRCqu0ldFc5wR+4dopNYn4liCtHW7RVSiSx8dRpEtpUVg4dQ9ycn2Toi1Y1oWcooK6mi2M0fzyE1ci2T3ADHIlX5PqXbzVwV04f5Q77tJWeBbj5N1fnqrckOsvJhPglkqNBgvWMpTtbYdz9ubfDv/usq48cWein3nKgw8hJ61lbj1ndAX0UVdJRZ47Ws= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CH2PR12MB3990.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(366016)(10070799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 2 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?OVlEMmtueUdMdkIwMGJRZ3lZdVJCRmU3UkFtWlZ3S2t1bjNFMXllSTd0YW9V?= =?utf-8?B?bFpTV1hualFuWnprdVU2aWtnUEpwMlJLTWcveEs1dUdiR25xSTh4VVExM241?= =?utf-8?B?c0xQUDcycnQwRVZKMUVYUTUyeHp5b3ZXM2ZzRWdxbXJ3VFJZekt3Z2I2OXEv?= =?utf-8?B?ZzJoeEtXR1JpK2Z6VFhlSmgvSnBSSEZJa1NNUkpaNXBta0VCcVhFci9SMUVr?= =?utf-8?B?Zmtvb0xCV0oyM29WTmZRTWw2VVdrQmI1cFQ0LzdxZitQbStjbzQ1VWhvYVBM?= =?utf-8?B?eHFsZ0pnZVYwdU9aaEJQdGVwbngwczZ0dkVSM0UzTUJ0emJqSHlmeXdXcFpn?= =?utf-8?B?LzdzWm9pcUJUWDdGWTIvNncyNEk0dkJUV1NpK1pSYytzamFqTnhWUldNOXdR?= =?utf-8?B?aGNidHBZUXJDT0ozbklObld0QkVwZTZVdW84Q3dpakFBMWh0eThXS2hzRlF6?= =?utf-8?B?SUJ6V2R5NFZNMWw3cDMrQUVJUFk2L1l3b2lkd1QvR2lZYzI3eUlyRk42WDlz?= =?utf-8?B?d25QZlExWllLc3NXb0h3a1Z6MmlxNW1KbmV3aXpPTE9LeVBCSkRDSFZSTlJM?= =?utf-8?B?b1JyNjNwNEFkZDdzaDdvWmk2SFhZR2dtaEVXSUNKS2hhWGFZVUN6Wk1KS1lE?= =?utf-8?B?c1BiRXp3K0NTMzFseTg3QUwyR3hFREhaUlI3UFpReDJuUFkzdzRRTVVwSXha?= =?utf-8?B?b3hQQmxSSzJLNVVpTENKd0YxRGdJL04vMmVVdGhDb2hPZXNGMHVYWG90bWcr?= =?utf-8?B?YWhWbEJVZkh5akxyeUQzWEJUeVZmMThScW92L3ZKSXdNS1ZDUXZyQ29Ia052?= =?utf-8?B?TkxUdm84TGNWYnRHWEpvbThJd0lNcUdpbGR2TEtPMTJTVldLSWJZTUR6WkZt?= =?utf-8?B?ZFcwMllYeWI4WVJuaDVpS0hzei9DaExnYjBCT1ZpTFlYUTFNZXFrQTZydmxK?= =?utf-8?B?SHU1SzdLT3RBdWRZOGtIQWVOeUc3R0dkQWZTckpsZHB5OW8xNHRkdTJhTGlq?= =?utf-8?B?bGNJMDdJcElYSzh5M21YWiszUnRVWE9nbFYyVDl3bVd1dEkvZXp0eU90QStY?= =?utf-8?B?cHVsVU15bmRSZTZtV0pHUmt3dzMxN29XeDhyZG1OdEZINy9tcTN3czNsaVh5?= =?utf-8?B?cy9NV3czVjJZVmVaQ2V0ZDM5MHFIYUtSZXRJUG0wV1RCc2p4M3VHOGw2am00?= =?utf-8?B?NHdNc1BKZFozWWpWQUdsaVpuSHBJS1hyY2NHNjFlSGNmeVlQQWhSdmJ1QlBW?= =?utf-8?B?eThaaThJbzI2NVduaXlDbndwUEVwcGtJMmhoVGd6SXpFL2JWWG1CQWowZEJ5?= =?utf-8?B?NHM5ditPTmpPaW1MRnlLQ2xYOW43b25vNEw3QS9jbE1wdjIzR3Vld0dMUW4x?= =?utf-8?B?SWc1ZW1mWG5aaGRNQjdxODZhd1Y4Q3pVbFRHL1FMZ1RTL1hEbkREZnY2dHBh?= =?utf-8?B?RHMzK3FYUzRNaGp4OXgwWENXemNBdnJzZm9nUnBsUHJ2MCtBVHFPME4rYnBP?= =?utf-8?B?NUtpSzNZRzB2YzlRaEF2c01VVlFkUElibzVGcDAvNzVValQ3MnRXM2ZYbVd0?= =?utf-8?B?R2llUUM0by9ZbWRVTHRjUUZRR29vOG9kT0h3QkZkZU54STRqS3NsYzhTNC9t?= =?utf-8?B?Tm5IWVN0WFN3b0g0NjlBREhMaWJPSjF5U295ZkZGdU40ZVhTMDUzQm1RN2Z2?= =?utf-8?B?ckJXZHpUOU5FU2NwOTZVVTU4S01hZEtBQlBlUERGa0xDTlRtSEY4THlWZ0xz?= =?utf-8?B?aGcvVDArVEthVW1ZZ2IwTEo1K2JSeGNTajR4cUk3UHBVVE5CV1dWaERyeThY?= =?utf-8?B?MTdBYm1UdkFMaGtqdzVDcHZITmJVb0hZNDdqd1dUeTA4aHJYQ0swc1FZSkFr?= =?utf-8?B?VDNjWnJkcUcwVHRYbDZPOCtHVVFOV3BjM0psZGR2UTNCam5pOGJ4MklhYnVv?= =?utf-8?B?T3F2Vzl2TnRiTTI5dDkrcE5oeFJSaE9MS0Y3eEpxL0NvMXJPdXhqNTJzditi?= =?utf-8?B?MkJPTHN4UHdCMlZRbkMyRnhHalJqUXlMaENTR0FDdHg3aUVnNXgyemFSSXZL?= =?utf-8?B?MURHcERtdVlXSmROeHhXc1J5MUJEZWZ6NyttS2w3OERrVjR1TjhJeTZ2V1VH?= =?utf-8?B?NzY1OXlmUjV3bjM5QmVFcDhycDU3QlVmV2lnMkkrci9icTVBZWpLQno5YS9U?= =?utf-8?B?RlJDUm1yNmF5cjRFdmpMOWhQTjNoR0VqVlJlc0d6MUdEVi82WjVZVmdML3Za?= =?utf-8?B?TVdjdEJDemFvSk1xNkxOOE9mMmo5aU4wZ1NCOWNCclREeEpseHdXTEgxVFhS?= =?utf-8?B?Sk5MRmlXVDdUYmx2TFFrNjFzSVVMV0NqWTJOaEdTU3Y2bE95SitqMlpueUk0?= =?utf-8?Q?y1W2kXWuOgv9Cyq/wBvodYPf8pnkeBKqhbm0kOwJJDRSi?= X-MS-Exchange-AntiSpam-MessageData-1: m6GdNRDUr2obtQ== X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: e6c3cdbd-8840-4d94-9b21-08de779b704c X-MS-Exchange-CrossTenant-AuthSource: CH2PR12MB3990.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2026 14:04:22.2092 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: nZj6t/MMGXFnwU3GU0HWkuzDlvPBFv8IYyNKBuCk5YF8WxUVkrtrhr4P9hB/hegktT96/IgZW/BvMzM8Xzwo2Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6632 These methods are relevant no matter the loading method used, thus move them to the common `FalconFirmware` trait. Signed-off-by: Alexandre Courbot Acked-by: Danilo Krummrich Reviewed-by: Eliot Courtney --- drivers/gpu/nova-core/falcon.rs | 12 ++++++------ drivers/gpu/nova-core/firmware/booter.rs | 8 ++++---- drivers/gpu/nova-core/firmware/fwsec.rs | 8 ++++---- 3 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index c02b73b1cfe6..53ee388f88be 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -367,12 +367,6 @@ pub(crate) trait FalconDmaLoadable { =20 /// Returns the load parameters for `DMEM`. fn dmem_load_params(&self) -> FalconDmaLoadTarget; - - /// Returns the parameters to write into the BROM registers. - fn brom_params(&self) -> FalconBromParams; - - /// Returns the start address of the firmware. - fn boot_addr(&self) -> u32; } =20 /// Trait for a falcon firmware. @@ -381,6 +375,12 @@ pub(crate) trait FalconDmaLoadable { pub(crate) trait FalconFirmware { /// Engine on which this firmware is to be loaded. type Target: FalconEngine; + + /// Returns the parameters to write into the BROM registers. + fn brom_params(&self) -> FalconBromParams; + + /// Returns the start address of the firmware. + fn boot_addr(&self) -> u32; } =20 /// Contains the base parameters common to all Falcon instances. diff --git a/drivers/gpu/nova-core/firmware/booter.rs b/drivers/gpu/nova-co= re/firmware/booter.rs index d569151982d1..7bb732aa4cd6 100644 --- a/drivers/gpu/nova-core/firmware/booter.rs +++ b/drivers/gpu/nova-core/firmware/booter.rs @@ -414,6 +414,10 @@ fn imem_ns_load_params(&self) -> Option { fn dmem_load_params(&self) -> FalconDmaLoadTarget { self.dmem_load_target.clone() } +} + +impl FalconFirmware for BooterFirmware { + type Target =3D Sec2; =20 fn brom_params(&self) -> FalconBromParams { self.brom_params.clone() @@ -427,7 +431,3 @@ fn boot_addr(&self) -> u32 { } } } - -impl FalconFirmware for BooterFirmware { - type Target =3D Sec2; -} diff --git a/drivers/gpu/nova-core/firmware/fwsec.rs b/drivers/gpu/nova-cor= e/firmware/fwsec.rs index 2ba70e0c5a30..07404164ef12 100644 --- a/drivers/gpu/nova-core/firmware/fwsec.rs +++ b/drivers/gpu/nova-core/firmware/fwsec.rs @@ -196,6 +196,10 @@ fn imem_ns_load_params(&self) -> Option { fn dmem_load_params(&self) -> FalconDmaLoadTarget { self.desc.dmem_load_params() } +} + +impl FalconFirmware for FwsecFirmware { + type Target =3D Gsp; =20 fn brom_params(&self) -> FalconBromParams { FalconBromParams { @@ -210,10 +214,6 @@ fn boot_addr(&self) -> u32 { } } =20 -impl FalconFirmware for FwsecFirmware { - type Target =3D Gsp; -} - impl FirmwareObject { fn new_fwsec(bios: &Vbios, cmd: FwsecCommand) -> Result { let desc =3D bios.fwsec_image().header()?; --=20 2.53.0 From nobody Thu Apr 16 08:34:48 2026 Received: from SN4PR0501CU005.outbound.protection.outlook.com (mail-southcentralusazon11011050.outbound.protection.outlook.com [40.93.194.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F6EF2E093A; Sun, 1 Mar 2026 14:04:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.194.50 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772373872; cv=fail; b=C8xTW5LYoCiIzKHG/0BA5o9F1fFmnymjhKmz0GyKxsUNbcNMszYl3Xzcqu4Dfi9PuY7fXvqRmLR6k6M8LqSomtzPDs5NsO48pBTtcPD5+iexjtthCpxv+NXNeMqX8F5eYuBczbsMWHBdNyO+zlsv4sUPKFnOpWKVqczNbSB5Qs0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772373872; c=relaxed/simple; bh=enW7hLE5p85owbpuocBRKPDw26meHOXxZxyBIywTZdo=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=Z8AI9g2RJ5MnBdYowZ64wGC0wKFPf7MSpDhAJRJkU1kwIzSwLVWeuwgMb5uLO08nBFr9lB1n86K/xYPO7f9Efb5iXT0xgceMNSjby2hkJVlZCYLhY0E6Rb1fgMEQ6h4WbqZ5aTF0AuPhaVaIwY65JKM/bBCOsu+ofTwE19VwXnQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=ApKMGljU; arc=fail smtp.client-ip=40.93.194.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="ApKMGljU" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=cbeiF9LaLQBYUAbi9OcNU43XDJ0sSQselisrjSdqGl3bwDsIJoCho3Ij8uB/UAK18RJGG+AcomsIINh4SA8snHsZkcwkqf73dc5eyxa41pyjMOzG9CWYxhcT7gT14X7vyJQcBISqakJTFV39J/c7YsjCN8WX8FjTbwkW/0Tz/1JepWjX6XlNF4KEsSVZe1OiCj/w2p7JuxV09QQ08+cJaQKjjMwnXzpIGbXhNhJxIyMAhTbSANUSOU032rDBuOb6fBX7AewhL2q8kmQjJET9wNefXpt7ECzg6UxgnTx8HyG1jE2fESgNf/BBNUbVzuVTjWL9Nt8tZx9QoHvobnibzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=tcI1DYyWJor8M7bTf0EZ1PwbMPr6PQlJuNaACoWqGzA=; b=JHzCwhgHuAJpyFybHHypqEM/6uIjhKEE27BthdKoxlfqg2NTcO5l6JoWsIO8n1VA0AbhqcpvSCfvwh8jKvp1sYwBilBrpM3Z69pn+tL+FMhbYOOFMZ1kpBkWPofAph/EQBLp1laJTAtQ/FmnMPQ5qbmeHPTsBSWlx/f3s4gdlp+uJWoq1LB/Kxuj+gLSK7+xkkBZT+VWuQMh4IS5k5yyuet0Y2srgbvqAJ5nqXO+UgqDNeQcaNc8FWITC88l+TJm3rZt0AVWRwnZ0tAStDrepAUFZqghkaqQTv9HxKDWctMYrOqmDX/SN8ga674AIvTn+2/gBErWymqgXzCxDOF58g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=tcI1DYyWJor8M7bTf0EZ1PwbMPr6PQlJuNaACoWqGzA=; b=ApKMGljU9X9FYGUpRCO1YG8I4ITcLvkArjSdtRFZeQwdZR+gYqYct30gbXYlQtWAgKcWWnV0pjyOaM5Ys5cyhXztnzn7S1PhJkeJheClpquCsC04bZVzh32xcJ52XdLGe3Vv/4a2KR/RdCBVT5WW796/LTQp3mcE2Cl2FKWDcTokWDFTb/RErJ7grSg5iNE5g3UcaMAoD0/kmrnUPYg5t9USlmNhKQ2k5ISmO+CTaw0sD4zam8Y/lQ1Iik7uWpasloDarbxplKc+KNpxjtIgp2of+HBUKwAyxFEXDukXU52poTT0jab1+6ll+X2HwHgHUkPCd09EcsuNOrc5+ERjtA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) by DS0PR12MB6632.namprd12.prod.outlook.com (2603:10b6:8:d0::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.19; Sun, 1 Mar 2026 14:04:25 +0000 Received: from CH2PR12MB3990.namprd12.prod.outlook.com ([fe80::7de1:4fe5:8ead:5989]) by CH2PR12MB3990.namprd12.prod.outlook.com ([fe80::7de1:4fe5:8ead:5989%6]) with mapi id 15.20.9654.020; Sun, 1 Mar 2026 14:04:25 +0000 From: Alexandre Courbot Date: Sun, 01 Mar 2026 23:03:50 +0900 Subject: [PATCH v10 07/10] gpu: nova-core: add PIO support for loading firmware images Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260301-turing_prep-v10-7-dde5ee437c60@nvidia.com> References: <20260301-turing_prep-v10-0-dde5ee437c60@nvidia.com> In-Reply-To: <20260301-turing_prep-v10-0-dde5ee437c60@nvidia.com> To: Danilo Krummrich , Alexandre Courbot , Alice Ryhl , David Airlie , Simona Vetter Cc: John Hubbard , Alistair Popple , Joel Fernandes , Timur Tabi , Edwin Peer , Eliot Courtney , nouveau@lists.freedesktop.org, rust-for-linux@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-ClientProxiedBy: TY4PR01CA0014.jpnprd01.prod.outlook.com (2603:1096:405:26e::17) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|DS0PR12MB6632:EE_ X-MS-Office365-Filtering-Correlation-Id: 5c58d95a-8b4d-44d8-a769-08de779b7255 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|366016|10070799003; X-Microsoft-Antispam-Message-Info: kc9MP1N8jRzmy/6Oulw141fa+n5NEzFANLldEEvRgk6WeMrOWRzuWR2itjLw86m0Yd5SyqbDvpYnk3WAKVHqTAcXaj8r1kAQAgOUdSoPzELRfuMHYdoxhYz61d3koKYVUPlCc2wSXFTfiM0kJBgUg3mw6Okzv/tQX28QTxfC1B9DM5wAPNKaGU7x1Nh6iJBS2ErB4U2j3sLI5ho3F0R33GBDVirqIJRagqhvw87/ogb8EJeqBHQIVzrjsJoG0TU21aIKwS6VCh+2Xe9jSYQ8HTFjZqEeYWBQWFm+P6yMrF4mNAuV76Em320tufCGnvLWMGq36N0/3qtMXHvd6w7pDmq4g9VEXIs+eUZ5J8VGYM1jN+HmbpgmWXxnr3YNkPvPZtxLflirBOtGG/5CvMbupUz06Q3ydB6zIvnsmE6RnJvxWh6VCQk88CtTh8pioyHt8lvPa+pdQuh76dNnwk/Gt0VRD+FSRASr6KkSBMAtaQUWzDPe1mKWttN6R04WKN9TT3vQ/ySrz9w/lfGYLO5MsxtxKqTUuBiO25dN6/Riw5f8NP6LTzHi+fSiX2f9tCQIxzzFENnvV9t5nLPjMY/yX9XAYXwYAzCyA125NgJhw7BDZjEdOz4RsC/LfbouS0VXLScvAI8S4NQDh+hJGiLzUEyX4gW/mVRnjYWcN0wsUq6swYLnkQfwjOTIjzfdwSmVbFgA/QMIy/2o8WUMiqQbpxDNJ4Sp+vW37q4mwBeRIao= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CH2PR12MB3990.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(366016)(10070799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 2 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?T09KQk1tZHFVSU5mUG1QN2g0eU5Pa1VSa1VFS0dJVk1GRGpraU9zazdrazFC?= =?utf-8?B?Z3dmdmltQjF6RUR6blF6am9qbWgzbnZPdWEydC9xcTJ4Vm9XTm5iL29lY2JD?= =?utf-8?B?eGhHOHdNUlBEc0tOTU14ZXhGU2RmbnluUjNOVUVGeGhsUU1xcVhHTE4vODBS?= =?utf-8?B?NENTR042a3VMWE4vaEVMekV1UUk0eVMxdGtRZTZOaldhRitsTDhDd2piWS9N?= =?utf-8?B?ZFVTV2tNMHVaSTRKcHB4Vy9CMU9Gb0xOdGN1aVBaWEhPRW8wL3lDdlhBK2Jv?= =?utf-8?B?YmoyVE5uYXFzc2ZQOCsyVkNUdzNXaFd4VXZIRjBXNU0zSUNWL3JydC9KaE1M?= =?utf-8?B?dHRSbGFpWitIb1U5azhOL0g0bnlmZXB1YU5HNUdIRC96bUZGemt4V3dRbzRF?= =?utf-8?B?QjBZTFJiZkdzTzMzRmlGOE5DaUFDbUJxMlphT0FoSkJpakJoT1RuWmM5Wks4?= =?utf-8?B?cm00Qk95L211N2wrbDJxcDN2N2N1SFhxSy9uZ3llTFMra2hqL0lJUXRlNnFn?= =?utf-8?B?TXVBa3J6UGNkQ0ZPeGlqR1RZWjdpUHFuZGlyR2ZsU1MyeHJ5L3FoVVlZK1lE?= =?utf-8?B?SVpHY2tSRWJvbjhzNFB0VEVQVWlLNlFqeU5qdHhpSUtwaDNybEJTS0l0S0lm?= =?utf-8?B?NHJxeWpjSGJ2U2N2cWJTbk9ZbGkyem9pRmdVUXNQb0ZNZ0svUTNrTWUyWk45?= =?utf-8?B?bjgrU01oZEFkWUkwS2E3cjJBNnNQckNha2NqdTB6T2UxWlVJQzZKS0NIRVJm?= =?utf-8?B?bEhyNzVUS1ZWYjd3K0hwRFIwaDF2aVRUcUVqNndGZWJQVkZUSFUzNnNOUGph?= =?utf-8?B?THMxL2NJWldnS1RqVkMrSTVNK3FuaG8vT216ZWVFcXFzbTdaSTQ4dVBrRkZ6?= =?utf-8?B?WXF5aHdMcDZLNEhKdmVQb3UwOUs4VHVqcUNRejNxQXovc1dJWGVibFBEeTM3?= =?utf-8?B?UlhiQnZpQy8zNG1ZNEdyekNKOEpiQktCdEdadWtmUnI1cUVrVzdNbHlBMEVw?= =?utf-8?B?cXg5Mk9oOUt6clpxdC9FYXY4Z0FQaTlLQVpxUVdUNk1DYUdvSHRSdkFNdWRY?= =?utf-8?B?MEZZRjRrMmJqUXNWSTR1emhpV25qWTErenZlSGdsOGN4VGNmUUJqa2lpVndo?= =?utf-8?B?Zk1YM0c5Q2ZnS3NGTVcyWE1nWjE2SHgzT3hhOThnUkN0dzlhR3ZFYmhJKzRX?= =?utf-8?B?SlNiS2doVXFxcFNLb2ErL3F3RllQekNnRXZiUzRLM0Nxd3BTVXdnYmJhUGtP?= =?utf-8?B?RHdGRGpCYUZIS0RuVmMydmx6cVNpS09LU294T2VkbHpLTS91RlFIK3pHUXAv?= =?utf-8?B?TFNuOCt2SlNYWlpFMDBzRTNBMHQwMW1MUExYaTBOU2Z6QW0zcnd5bGNJWTRC?= =?utf-8?B?MWJZeHZNZWxtMWUrNnNtRHNsRDF3WWljM3J2NVY0WjdwVFhva1Mwd1orSkUw?= =?utf-8?B?MGM1RkdaQUtrMnZiYS9HV1IyUzUrQmtuMHdUa3YrY3ZhZmJJdm05eWk5WFIy?= =?utf-8?B?TmNOdWlzV3VHUGt2czc3aDVyajMxTlBSSnA2NWtVU0t5cFRNMTdsTEVjTHVK?= =?utf-8?B?dVZHV2ZWMjl0UE1ld3VMdjJCcmxZeDd4aGNrbFhpRGZGck5NVHhHaUhhN1N4?= =?utf-8?B?OUhXRU1Tc05ybU9lcXVOVzc1UVhacml4WnQwWUl0ZjZDYWkrREVvR0s4WVRl?= =?utf-8?B?aHp2ZG1FTkNBSnFCbDFKaFZlczdqWGd5U1hMNXBUM01GMGFBSVlQSElRRzVM?= =?utf-8?B?a2JXbHg5QWlTMlUvaVF5U3RIaXBWK1M4TE1JaitIYVNqUmJORDRzVGxCb3Rs?= =?utf-8?B?S1d3ZzU5MFdOd01KMkNrOTdod3hXdmpKYWZnR2xFdXlrQzg3Mnp3cnhpbENZ?= =?utf-8?B?aWxBWVFDZ2VJRm5QSFYxR0p2NTFBY2hybDNUVjZWOWZGYWNoM2REUkdZM2NN?= =?utf-8?B?aVR1QVBjYXNVOG1RVHVldEhsMTczK3g2dEIwK3lBaS8wL0VlS1ZxWU1RVTVP?= =?utf-8?B?NCtZUHdGL3I4dndLeGpkeXpUSTh6TVc2bEZ3b1RNY2wxTlBKZjRCOUxVdksw?= =?utf-8?B?YlQ0Nng4ZFp3eFVsNTR5RFBpdWlBS3FuMVFBK0JvNEtWdklPTUlxVEw4Q2dV?= =?utf-8?B?ODJrS3RQQy9pUjZ6R0FkSklDQXJuVnI4aW9CaHg1b3FuOWdBdFNlU3RPVFhQ?= =?utf-8?B?VTFkMVZBWExHZnVnazBucXE4WGViZG4zTVNlRFpjeU9jNVZKcGRuTnNiVjRo?= =?utf-8?B?L0liSjQ1dU10d0lGWGtzOFNsak00QnNJaWVWODBOalpoT3VCczhEM2grMlBC?= =?utf-8?B?bmpIeDdna0c4MGNoa0laTkRGRG9LT0NLZzdGZ251SU41M1BweDM0ZmxwMlpz?= =?utf-8?Q?ZhGXVzAQH3pPrdwxWEy5j0RtDDVtaTvRfjaPlezWqA9Pz?= X-MS-Exchange-AntiSpam-MessageData-1: zYt2amzn8XAk1A== X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5c58d95a-8b4d-44d8-a769-08de779b7255 X-MS-Exchange-CrossTenant-AuthSource: CH2PR12MB3990.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2026 14:04:25.6298 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: rOYnhW+WTJ3dDeHZoov7Fug6XZwyyvdLgYsIsPdcaX4nFjeos1blHhcdnZad1aj0+ZMVIT1CbFgzx+t+gSW0sg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6632 From: Timur Tabi Turing and GA100 use programmed I/O (PIO) instead of DMA to upload firmware images into Falcon memory. Signed-off-by: Timur Tabi Co-developed-by: Alexandre Courbot Signed-off-by: Alexandre Courbot Acked-by: Danilo Krummrich --- drivers/gpu/nova-core/falcon.rs | 218 ++++++++++++++++++++++++++++++++= +++- drivers/gpu/nova-core/falcon/hal.rs | 6 +- drivers/gpu/nova-core/regs.rs | 30 +++++ 3 files changed, 251 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index 53ee388f88be..7097a206ec3c 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -367,6 +367,127 @@ pub(crate) trait FalconDmaLoadable { =20 /// Returns the load parameters for `DMEM`. fn dmem_load_params(&self) -> FalconDmaLoadTarget; + + /// Returns an adapter that provides the required parameter to load th= is firmware using PIO. + /// + /// This can only fail if some `u32` fields cannot be converted to `u1= 6`, or if the indices in + /// the headers are invalid. + fn try_as_pio_loadable(&self) -> Result> { + let new_pio_imem =3D |params: FalconDmaLoadTarget, secure| { + let start =3D usize::from_safe_cast(params.src_start); + let end =3D start + usize::from_safe_cast(params.len); + let data =3D self.as_slice().get(start..end).ok_or(EINVAL)?; + + let dst_start =3D u16::try_from(params.dst_start).map_err(|_| = EINVAL)?; + + Ok::<_, Error>(FalconPioImemLoadTarget { + data, + dst_start, + secure, + start_tag: dst_start >> 8, + }) + }; + + let imem_sec =3D new_pio_imem(self.imem_sec_load_params(), true)?; + + let imem_ns =3D if let Some(params) =3D self.imem_ns_load_params()= { + Some(new_pio_imem(params, false)?) + } else { + None + }; + + let dmem =3D { + let params =3D self.dmem_load_params(); + let start =3D usize::from_safe_cast(params.src_start); + let end =3D start + usize::from_safe_cast(params.len); + let data =3D self.as_slice().get(start..end).ok_or(EINVAL)?; + + let dst_start =3D u16::try_from(params.dst_start).map_err(|_| = EINVAL)?; + + FalconPioDmemLoadTarget { data, dst_start } + }; + + Ok(FalconDmaFirmwarePioAdapter { + fw: self, + imem_sec, + imem_ns, + dmem, + }) + } +} + +/// Represents a portion of the firmware to be loaded into IMEM using PIO. +#[derive(Clone)] +pub(crate) struct FalconPioImemLoadTarget<'a> { + pub(crate) data: &'a [u8], + pub(crate) dst_start: u16, + pub(crate) secure: bool, + pub(crate) start_tag: u16, +} + +/// Represents a portion of the firmware to be loaded into DMEM using PIO. +#[derive(Clone)] +pub(crate) struct FalconPioDmemLoadTarget<'a> { + pub(crate) data: &'a [u8], + pub(crate) dst_start: u16, +} + +/// Trait for providing PIO load parameters of falcon firmwares. +pub(crate) trait FalconPioLoadable { + /// Returns the load parameters for Secure `IMEM`, if any. + fn imem_sec_load_params(&self) -> Option>; + + /// Returns the load parameters for Non-Secure `IMEM`, if any. + fn imem_ns_load_params(&self) -> Option>; + + /// Returns the load parameters for `DMEM`. + fn dmem_load_params(&self) -> FalconPioDmemLoadTarget<'_>; +} + +/// Adapter type that makes any DMA-loadable firmware also loadable via PI= O. +/// +/// Created using [`FalconDmaLoadable::try_as_pio_loadable`]. +pub(crate) struct FalconDmaFirmwarePioAdapter<'a, T: FalconDmaLoadable + ?= Sized> { + /// Reference to the DMA firmware. + fw: &'a T, + /// Validated secure IMEM parameters. + imem_sec: FalconPioImemLoadTarget<'a>, + /// Validated non-secure IMEM parameters. + imem_ns: Option>, + /// Validated DMEM parameters. + dmem: FalconPioDmemLoadTarget<'a>, +} + +impl<'a, T> FalconPioLoadable for FalconDmaFirmwarePioAdapter<'a, T> +where + T: FalconDmaLoadable + ?Sized, +{ + fn imem_sec_load_params(&self) -> Option> { + Some(self.imem_sec.clone()) + } + + fn imem_ns_load_params(&self) -> Option> { + self.imem_ns.clone() + } + + fn dmem_load_params(&self) -> FalconPioDmemLoadTarget<'_> { + self.dmem.clone() + } +} + +impl<'a, T> FalconFirmware for FalconDmaFirmwarePioAdapter<'a, T> +where + T: FalconDmaLoadable + FalconFirmware + ?Sized, +{ + type Target =3D ::Target; + + fn brom_params(&self) -> FalconBromParams { + self.fw.brom_params() + } + + fn boot_addr(&self) -> u32 { + self.fw.boot_addr() + } } =20 /// Trait for a falcon firmware. @@ -417,6 +538,98 @@ pub(crate) fn reset(&self, bar: &Bar0) -> Result { Ok(()) } =20 + /// Falcons supports up to four ports, but we only ever use one, so ju= st hard-code it. + const PIO_PORT: usize =3D 0; + + /// Write a slice to Falcon IMEM memory using programmed I/O (PIO). + /// + /// Returns `EINVAL` if `img.len()` is not a multiple of 4. + fn pio_wr_imem_slice(&self, bar: &Bar0, load_offsets: FalconPioImemLoa= dTarget<'_>) -> Result { + // Rejecting misaligned images here allows us to avoid checking + // inside the loops. + if load_offsets.data.len() % 4 !=3D 0 { + return Err(EINVAL); + } + + regs::NV_PFALCON_FALCON_IMEMC::default() + .set_secure(load_offsets.secure) + .set_aincw(true) + .set_offs(load_offsets.dst_start) + .write(bar, &E::ID, Self::PIO_PORT); + + for (n, block) in load_offsets.data.chunks(MEM_BLOCK_ALIGNMENT).en= umerate() { + let n =3D u16::try_from(n)?; + let tag: u16 =3D load_offsets.start_tag.checked_add(n).ok_or(E= RANGE)?; + regs::NV_PFALCON_FALCON_IMEMT::default().set_tag(tag).write( + bar, + &E::ID, + Self::PIO_PORT, + ); + for word in block.chunks_exact(4) { + let w =3D [word[0], word[1], word[2], word[3]]; + regs::NV_PFALCON_FALCON_IMEMD::default() + .set_data(u32::from_le_bytes(w)) + .write(bar, &E::ID, Self::PIO_PORT); + } + } + + Ok(()) + } + + /// Write a slice to Falcon DMEM memory using programmed I/O (PIO). + /// + /// Returns `EINVAL` if `img.len()` is not a multiple of 4. + fn pio_wr_dmem_slice(&self, bar: &Bar0, load_offsets: FalconPioDmemLoa= dTarget<'_>) -> Result { + // Rejecting misaligned images here allows us to avoid checking + // inside the loops. + if load_offsets.data.len() % 4 !=3D 0 { + return Err(EINVAL); + } + + regs::NV_PFALCON_FALCON_DMEMC::default() + .set_aincw(true) + .set_offs(load_offsets.dst_start) + .write(bar, &E::ID, Self::PIO_PORT); + + for word in load_offsets.data.chunks_exact(4) { + let w =3D [word[0], word[1], word[2], word[3]]; + regs::NV_PFALCON_FALCON_DMEMD::default() + .set_data(u32::from_le_bytes(w)) + .write(bar, &E::ID, Self::PIO_PORT); + } + + Ok(()) + } + + /// Perform a PIO copy into `IMEM` and `DMEM` of `fw`, and prepare the= falcon to run it. + pub(crate) fn pio_load + FalconPioLoad= able>( + &self, + bar: &Bar0, + fw: &F, + ) -> Result { + regs::NV_PFALCON_FBIF_CTL::read(bar, &E::ID) + .set_allow_phys_no_ctx(true) + .write(bar, &E::ID); + + regs::NV_PFALCON_FALCON_DMACTL::default().write(bar, &E::ID); + + if let Some(imem_ns) =3D fw.imem_ns_load_params() { + self.pio_wr_imem_slice(bar, imem_ns)?; + } + if let Some(imem_sec) =3D fw.imem_sec_load_params() { + self.pio_wr_imem_slice(bar, imem_sec)?; + } + self.pio_wr_dmem_slice(bar, fw.dmem_load_params())?; + + self.hal.program_brom(self, bar, &fw.brom_params())?; + + regs::NV_PFALCON_FALCON_BOOTVEC::default() + .set_value(fw.boot_addr()) + .write(bar, &E::ID); + + Ok(()) + } + /// Perform a DMA write according to `load_offsets` from `dma_handle` = into the falcon's /// `target_mem`. /// @@ -652,7 +865,8 @@ pub(crate) fn is_riscv_active(&self, bar: &Bar0) -> boo= l { self.hal.is_riscv_active(bar) } =20 - // Load a firmware image into Falcon memory + /// Load a firmware image into Falcon memory, using the preferred meth= od for the current + /// chipset. pub(crate) fn load + FalconDmaLoadable= >( &self, dev: &Device, @@ -661,7 +875,7 @@ pub(crate) fn load + Fa= lconDmaLoadable>( ) -> Result { match self.hal.load_method() { LoadMethod::Dma =3D> self.dma_load(dev, bar, fw), - LoadMethod::Pio =3D> Err(ENOTSUPP), + LoadMethod::Pio =3D> self.pio_load(bar, &fw.try_as_pio_loadabl= e()?), } } =20 diff --git a/drivers/gpu/nova-core/falcon/hal.rs b/drivers/gpu/nova-core/fa= lcon/hal.rs index 89babd5f9325..a7e5ea8d0272 100644 --- a/drivers/gpu/nova-core/falcon/hal.rs +++ b/drivers/gpu/nova-core/falcon/hal.rs @@ -58,7 +58,11 @@ fn signature_reg_fuse_version( /// Reset the falcon engine. fn reset_eng(&self, bar: &Bar0) -> Result; =20 - /// returns the method needed to load data into Falcon memory + /// Returns the method used to load data into the falcon's memory. + /// + /// The only chipsets supporting PIO are those < GA102, and PIO is the= preferred method for + /// these. For anything above, the PIO registers appear to be masked t= o the CPU, so DMA is the + /// only usable method. fn load_method(&self) -> LoadMethod; } =20 diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index ea0d32f5396c..53f412f0ca32 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -364,6 +364,36 @@ pub(crate) fn with_falcon_mem(self, mem: FalconMem) ->= Self { 1:1 startcpu as bool; }); =20 +// IMEM access control register. Up to 4 ports are available for IMEM acce= ss. +register!(NV_PFALCON_FALCON_IMEMC @ PFalconBase[0x00000180[4; 16]] { + 15:0 offs as u16, "IMEM block and word offset"; + 24:24 aincw as bool, "Auto-increment on write"; + 28:28 secure as bool, "Access secure IMEM"; +}); + +// IMEM data register. Reading/writing this register accesses IMEM at the = address +// specified by the corresponding IMEMC register. +register!(NV_PFALCON_FALCON_IMEMD @ PFalconBase[0x00000184[4; 16]] { + 31:0 data as u32; +}); + +// IMEM tag register. Used to set the tag for the current IMEM block. +register!(NV_PFALCON_FALCON_IMEMT @ PFalconBase[0x00000188[4; 16]] { + 15:0 tag as u16; +}); + +// DMEM access control register. Up to 8 ports are available for DMEM acce= ss. +register!(NV_PFALCON_FALCON_DMEMC @ PFalconBase[0x000001c0[8; 8]] { + 15:0 offs as u16, "DMEM block and word offset"; + 24:24 aincw as bool, "Auto-increment on write"; +}); + +// DMEM data register. Reading/writing this register accesses DMEM at the = address +// specified by the corresponding DMEMC register. +register!(NV_PFALCON_FALCON_DMEMD @ PFalconBase[0x000001c4[8; 8]] { + 31:0 data as u32; +}); + // Actually known as `NV_PSEC_FALCON_ENGINE` and `NV_PGSP_FALCON_ENGINE` d= epending on the falcon // instance. register!(NV_PFALCON_FALCON_ENGINE @ PFalconBase[0x000003c0] { --=20 2.53.0 From nobody Thu Apr 16 08:34:48 2026 Received: from SN4PR2101CU001.outbound.protection.outlook.com (mail-southcentralusazon11012002.outbound.protection.outlook.com [40.93.195.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8BA5236437; Sun, 1 Mar 2026 14:04:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.195.2 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772373876; cv=fail; b=MMvqcmnMbE6UfwpQ/daLWWPtGfyfEWQuSsE2uAJK+cSclQ2IifWwOMBEttZr/VMwThRn9ZzA95XGdySK3iGLZ/lwOIP7ctNTrnyqu+x2kVAu9cqvtXFAe2X4mgDdOgdNl1wIu3x7DWJR9vqeqXcXvNSPEPydP4YVUEQ4KcNAcjc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772373876; c=relaxed/simple; bh=EblsvUXxW7LeRJRcs6Cbr5QE+Et5IwP1+mrcv6ABk68=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=cLghKsN7lPyd+r4hCMmgLJj5CH3QcGxBPB/RUgRGvODfELFN9Pf1TZh+1ZonEzPw1jCEpBlEgLaX4WzLBk7Fosapw8JxjXPZBQrXLfIBrk4GFxyyJrXT2rvwAn0EmLdCaBxe3r0yfqaU+qSk7t8yRbTDfLDU0FHzcn/sfu6ANeI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=NUWzWBOt; arc=fail smtp.client-ip=40.93.195.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="NUWzWBOt" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=WYf41rcVXvlgOdRl9GUV1sEmsCdjeD6L95ZbTVzzmXUffmcwBVy6sz2RgwkMYn5JwvpUYm5H4iQQDa9ly0epPHO7aEyX4KFw1NyDIyvmfxxPUq1JUBIRpzmrqdU0kzEmswbWcScfX0tPBWVAu4ZSuPlVy7pCt45zM1TI/1yHmTEkVpEpkp+b3iX8qHLn1uT+/nq5guTT4ij4BONH0J2oEIo1KjpNaDvDKOqUxI9xqeiNLmwDydnmBc/ym7VzEKo/jH8UpY6PiZa9le0SCOLzF0XZ30DQKMpvYYx2OL+eAY4unSAu9u8fNm/ip9GIFcGh9ymTb38bCMA9awsok7KoEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=pkt90Vjva5r/lyTLtWUJ71F1ymOkq45s2ga8Pq+ASd4=; b=KW5iNshQnhbgIW8lJPWARiMMfQxrKnInP7DVRUwD6kYLXwhdk/s800nmJg//JRKQNyfjHiYjDP15UlwL0CPoUf9WGE7Opn9+UFs7Ym0D9OwqHLGy363l7E8RBsO7/6syHjshokeA3X3Y2QMMhBSmsnTyvLlNJBgoDQ1tDHhfWn8xEpQJJi/wOy2NwZHSw+ie67pYXVgRXXRrrQl63+Z8ddVFBl2ouOZ2vA21kKZbkih3/Xgp6jdUnnjvcChENCKwiuas9XVAlMntDiZUedGcDZ8H2WYLERxi+UMA4A5Nof5GQMzM+DAXNnlctMfr+K/ddFEDu4hAv2CjZs6+7uuPYQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=pkt90Vjva5r/lyTLtWUJ71F1ymOkq45s2ga8Pq+ASd4=; b=NUWzWBOt5LXT1IwI5VD9qIvz3KHysCsxdcvZZqMtmqgcnM60qmghrKaft/zTxSKXFyzniGpucCsxbkTROOMWc70tjSY9prop1pLbi0yhq3N7YtZzY3Yt9fuycWXuhIIghN0II+1H0DSdeGSVsXuxS9dtO8GryNEBmddy4N6mAvcF5Q3J9do8FKWx7fXld3HnXeF1W5qJamK0opxX8GOgscss7Mzu3CAMQqImlP02zP4+5IJp1Q4933i8vhvRhqjmCP+GHNNMejtPvy8EOSXf1sSGzL28QYk4/Wosd788u/d6z5rK+LkXJWv3DdrSLjAxGFMVPCcJcsn25tXSxXm5OQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) by DS0PR12MB6632.namprd12.prod.outlook.com (2603:10b6:8:d0::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.19; Sun, 1 Mar 2026 14:04:30 +0000 Received: from CH2PR12MB3990.namprd12.prod.outlook.com ([fe80::7de1:4fe5:8ead:5989]) by CH2PR12MB3990.namprd12.prod.outlook.com ([fe80::7de1:4fe5:8ead:5989%6]) with mapi id 15.20.9654.020; Sun, 1 Mar 2026 14:04:29 +0000 From: Alexandre Courbot Date: Sun, 01 Mar 2026 23:03:51 +0900 Subject: [PATCH v10 08/10] gpu: nova-core: use the Generic Bootloader to boot FWSEC on Turing Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260301-turing_prep-v10-8-dde5ee437c60@nvidia.com> References: <20260301-turing_prep-v10-0-dde5ee437c60@nvidia.com> In-Reply-To: <20260301-turing_prep-v10-0-dde5ee437c60@nvidia.com> To: Danilo Krummrich , Alexandre Courbot , Alice Ryhl , David Airlie , Simona Vetter Cc: John Hubbard , Alistair Popple , Joel Fernandes , Timur Tabi , Edwin Peer , Eliot Courtney , nouveau@lists.freedesktop.org, rust-for-linux@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-ClientProxiedBy: TYCPR01CA0180.jpnprd01.prod.outlook.com (2603:1096:400:2b2::20) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|DS0PR12MB6632:EE_ X-MS-Office365-Filtering-Correlation-Id: aee14834-7115-4a2b-bf44-08de779b74b7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|366016|10070799003; X-Microsoft-Antispam-Message-Info: GbG6nUSL1v9Sj8gkfSIdAsfmq12HqQvIKedwFG6w9/Msg8Zy//HDRybqs495elJ4HYnUS9u8QYmHr52CNgiPI//MOBw2CoHTBojbQ7x7j3Bxq0Wf/9RY4fzv0myN5opVU3fwmZetf0WtTBb+a97j0FeLRU3u72Ze49oBA3nk0p3o8fPjEVFuikpcjDTRiD8GvzblYopYXa5MsL7r61jV0l90SQjZTfFsIdXQST7mRJOutej72BrAoJFi4xGYj3cxgZzQ/Dv0AcqsuyVTxr0mBV4NrCLivGmoH1Se2UMKjQcoy5k5+AAX0F8zm5IG0eYSw3JnySiltgGZNiNjvDgTXm2RFGPxFmc3kAR+GQbL4jnTOCh0lnaIfZZ53iBeEvjGq+eHr5dVVicaafxSLeAIEc4YB1ckQunhEnLQk1OnegsXHXME7NmASTmz+StuR38WUQYglQv1pTRgl1bhWPPhyN8Qmn5mIP+HOHok/vxi/0ORFzO2oy4Unz3hqoVz4zpdsyUru9G420KXvSwiQAQzzeVte4WNnL/rfwWSXhNvUh2keqynLnqCO7JYmob3GoYFPxOgw9jfgypQh8bm8v3Lc9dp5liaLxHS6kOX1uQdiId02VFVKp2CzF8m3olsuDxL7n/3TcDBNYF9XxePPAd2Vrk8ACl06WUSnhaNzhUoABM73WspSLU8PSMDEypG0IPeYUlOlIXuQxTLuWYWX5G6GMKIgxLNjGfy78CoXmbCUPo= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CH2PR12MB3990.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(366016)(10070799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 2 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?ME5lZTIzbjJMU1U0TlZQOXM3REt1bkU3djNUSzdJQTRWQ2JqbXlQajErVm1p?= =?utf-8?B?S2FsTm5TR3FKNDdjQ1NMMytVUXpETmxNaVd3UjNJRlI0QXA0a01PRUxuaWEw?= =?utf-8?B?NkhsU1c4SThiRGdmcGlWNnp6Tnp4ZVBvRkVacDYvdmVlR0hyZHJhOUVISjlT?= =?utf-8?B?NlFPaWR3dllWb2hHYzRYK2ladDhublNRc0NkaGpPRjYvMWh2YU1wY01ab1k0?= =?utf-8?B?TitkZXdWUjVzRjZJQm1GU3FmMm1vd2MyWDZpcU8yeW5aRE9tcjdwN0pjM1pF?= =?utf-8?B?UmlLaHVtNlN3azM0TXpKdVFsVXRURDNsOXgzNU5iaVhyejUzb2ZTWXc2VXFJ?= =?utf-8?B?ZUFHRHZiVStUSkN0R0s3WHdRTHpHcGkxN013cFV2cTlHd2dKeEtaT1hTZmpO?= =?utf-8?B?NVVXem9nbUtDdVNLNEljV3J0NkdTKzl0V3ZEMU0wZlNQU08veGdpUFFrRnNn?= =?utf-8?B?NGdCUWZRbldRSnQwK0dlMzVUV1RBYVhabnJMbWJCZ3JzLzhtcVZ1OHlmcmRa?= =?utf-8?B?TXlmT0dEVTZSeTMxNk40dmNoWDBiaDIrdkoybGQ0cU9NbmdZSlRlcjZ5VHdj?= =?utf-8?B?S3lLWjdJYmFWMXNkM1NSQ3V3elk5ZTNIZXhqTU5rYU1vQ2VweE96Q0YyZGNw?= =?utf-8?B?cEt6TFF0cHppUy9naXo4Q2Q2WFNFN2JsSDRYTWhMYllrSjNCbEx0Y0x0UHRW?= =?utf-8?B?YnYzMUMyTjVVTmhDRk1MUXNEYXZlTkJzVVVEcllvbE1FNFVqTUFSWEt0T2Vr?= =?utf-8?B?MGJ6NHJOd3hIWHdQTFZLTVBpdm5YNVVrL2lGb3hrTWwzYVZHK0h5dXNXYnVp?= =?utf-8?B?dTNCL2FjMUJjaTdJNjNSUFFoYWVjQUpEeHF6SGI1REh1ZDhCSW5URkI5cEJO?= =?utf-8?B?bSs0TEJwZGFGdHduZXVpV1V5Sk1LZmdRUktzRW96WmJZQ09TS0VvV0Y5M0xM?= =?utf-8?B?Q1cxcnRIQUN6dFBjK1lOcEJlUHlwYmN3S2ptVEJaYWsvVkxJc3E3ejd4NVYy?= =?utf-8?B?TytTcjM5MzkvdW1LdHA2ODc5M3FOL0RaWTlpVkJDOVRHZjNoMDBzL0NhY0VS?= =?utf-8?B?MTlkZlVPYkw2cklOVVd5bDI0QUF2T0c2RVFjMk1vblhvbVA1NWYzOGcxRDhh?= =?utf-8?B?NFVJSFdFdUxlVjhhbUw1WnNLR3o5Y2NMQjNVTW94aHBaL0pzdHlaOVlQOExD?= =?utf-8?B?eGpiUURHRlQza0RqQWNHV01MdUJGUDN6VlNIbzJxMzlmM0szRFNDNzd3MnM3?= =?utf-8?B?UU1Xb09uWXhqOE5GalBkZlpraFEwaHF5cnh5WU5LZmgxOVJBU2FTc25rdjJv?= =?utf-8?B?QUlHb2RvVDlZRE9jMUNwNmZzSnp0K041MXJjUllsaGtzcFFoNUxRZm1mcmpW?= =?utf-8?B?UUxya1kyaTc4emRCVjEzRm9vWE1XOXlMdUlFMmN4RTY0NEdBdUd0a2F3aC9y?= =?utf-8?B?QkJHQThkSXZ4Z010b1pDZlFTeHNXOWhXK3V5eFh2VEVQQjdnUWdZeG8yR3NK?= =?utf-8?B?bnNsRlM4c1VUZDZnQnFsQmE2cWN1eENIakpmK0FPQ0UxRXFYQXAxUUpSZ3Vy?= =?utf-8?B?OTBtczBuK3RVamllcHJNMjZ5OGJWR1o1MUUvVFlqOVBXU2tQY1o0aVhpWlZH?= =?utf-8?B?anpiM1A5RFdUSENZdGVCdnI1cndmOWw5bVlSQjloS1hoTlNCeUlRNDQ4ZFpZ?= =?utf-8?B?Um9LUi9pbUdzN0czakJZeHRGUytlNXVnZ3BVU1lkcU9zSFc1LzVIUHhtcEpq?= =?utf-8?B?SXBWUGorMHVmdUJkSFUrQ2pLQ0RGZlZNeWJtR3c4amptalROYjlVb2pmQUx5?= =?utf-8?B?SVNEa01PYUYxWWU0ZkxTMW1UR1FNMVY1cStmelhmOTFISHp6T2hmeU53d1B4?= =?utf-8?B?QWw4RUh2cEhtay9MQkkxajVIZEhSQ3d2QjBwWE5vMGd5cHVqZC9kSnBQTVNH?= =?utf-8?B?K05FbGpxVEhtcEdRV1NRa1c5dzdXZ3NEZmxqWWdRTEhqUWtHcEpWNms0MnRE?= =?utf-8?B?Z3BtTWhsQkhrZ2pKdXI0OFh1clFaRzd6WElHYk1kbXk5NUpBSnZmYVpkY0Mw?= =?utf-8?B?UGhKamx6aTJOeE9tYnZXYmdSWmlHTmw4RTZNcXJaMzFMeUFkT0E2NkFDd0Vi?= =?utf-8?B?TlIwRmxkeXJQMHVRclJYaWk0M29XS1JSWjVqa2xrY0xVUW8yVU9tNFBjS1dS?= =?utf-8?B?QkpDK1N5Y211Y3o5MHlqcy93b29RbDdlSjc3d1RVMzFGNEFKK2ZiSXhDcUhk?= =?utf-8?B?YjhaSlQxUUYyNGxvTlVLenp3UVpZMlROLzE5YlQ4OEpwWG5ZM3ptV0xmTHcw?= =?utf-8?B?eUhMU3ZiRU5uVVBvQzZQZ2lGakMxRHV5Yk1pNHZMbzVCR25JSlkvZGFKQ2Jk?= =?utf-8?Q?DBAKhV0QQJiiv35FYYiNW/nga5J+ETOoWuJDsx5Fw8pJL?= X-MS-Exchange-AntiSpam-MessageData-1: 8VQVMgNKm55uBQ== X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: aee14834-7115-4a2b-bf44-08de779b74b7 X-MS-Exchange-CrossTenant-AuthSource: CH2PR12MB3990.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2026 14:04:29.6688 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: lERJmnNSXq6EFW5PvQmPVSh2Sfldyfu/YXwSIbjIGpJcHsiuWJMMOu+ax0XlbuYJwmv5esLIRskkq+1FIHw8Rw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6632 From: Timur Tabi On Turing and GA100, a new firmware image called the Generic Bootloader (gen_bootloader) must be used to load FWSEC into Falcon memory. The driver loads the generic bootloader into Falcon IMEM, passes a descriptor that points to FWSEC using DMEM, and then boots the generic bootloader. The bootloader will then load FWSEC into IMEM and boot it. Signed-off-by: Timur Tabi Co-developed-by: Alexandre Courbot Signed-off-by: Alexandre Courbot Acked-by: Danilo Krummrich --- drivers/gpu/nova-core/firmware/fwsec.rs | 6 + drivers/gpu/nova-core/firmware/fwsec/bootloader.rs | 289 +++++++++++++++++= ++++ drivers/gpu/nova-core/gsp/boot.rs | 15 +- 3 files changed, 307 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nova-core/firmware/fwsec.rs b/drivers/gpu/nova-cor= e/firmware/fwsec.rs index 07404164ef12..afa39f04cc8a 100644 --- a/drivers/gpu/nova-core/firmware/fwsec.rs +++ b/drivers/gpu/nova-core/firmware/fwsec.rs @@ -10,6 +10,8 @@ //! - The command to be run, as this firmware can perform several tasks ; //! - The ucode signature, so the GSP falcon can run FWSEC in HS mode. =20 +pub(crate) mod bootloader; + use core::marker::PhantomData; =20 use kernel::{ @@ -378,6 +380,10 @@ pub(crate) fn new( } =20 /// Loads the FWSEC firmware into `falcon` and execute it. + /// + /// This must only be called on chipsets that do not need the FWSEC bo= otloader (i.e., where + /// [`Chipset::needs_fwsec_bootloader()`](crate::gpu::Chipset::needs_f= wsec_bootloader) returns + /// `false`). On chipsets that do, use [`bootloader::FwsecFirmwareWith= Bl`] instead. pub(crate) fn run( &self, dev: &Device, diff --git a/drivers/gpu/nova-core/firmware/fwsec/bootloader.rs b/drivers/g= pu/nova-core/firmware/fwsec/bootloader.rs new file mode 100644 index 000000000000..dcde2d21dd4e --- /dev/null +++ b/drivers/gpu/nova-core/firmware/fwsec/bootloader.rs @@ -0,0 +1,289 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Bootloader support for the FWSEC firmware. +//! +//! On Turing, the FWSEC firmware is not loaded directly, but is instead l= oaded through a small +//! bootloader program that performs the required DMA operations. This boo= tloader itself needs to +//! be loaded using PIO. + +use kernel::{ + alloc::KVec, + device::{ + self, + Device, // + }, + prelude::*, + ptr::{ + Alignable, + Alignment, // + }, + sizes, + transmute::{ + AsBytes, + FromBytes, // + }, +}; + +use crate::{ + dma::DmaObject, + driver::Bar0, + falcon::{ + self, + gsp::Gsp, + Falcon, + FalconBromParams, + FalconDmaLoadable, + FalconEngine, + FalconFbifMemType, + FalconFbifTarget, + FalconFirmware, + FalconPioDmemLoadTarget, + FalconPioImemLoadTarget, + FalconPioLoadable, // + }, + firmware::{ + fwsec::FwsecFirmware, + request_firmware, + BinHdr, + FIRMWARE_VERSION, // + }, + gpu::Chipset, + num::FromSafeCast, + regs, +}; + +/// Descriptor used by RM to figure out the requirements of the boot loade= r. +#[repr(C)] +#[derive(Debug, Clone)] +struct BootloaderDesc { + /// Starting tag of bootloader. + start_tag: u32, + /// DMEM offset where [`BootloaderDmemDescV2`] is to be loaded. + dmem_load_off: u32, + /// Offset of code section in the image. + code_off: u32, + /// Size of code section in the image. + code_size: u32, + /// Offset of data section in the image. + data_off: u32, + /// Size of data section in the image. + data_size: u32, +} +// SAFETY: any byte sequence is valid for this struct. +unsafe impl FromBytes for BootloaderDesc {} + +/// Structure used by the boot-loader to load the rest of the code. +/// +/// This has to be filled by the GPU driver and copied into DMEM at offset +/// [`BootloaderDesc.dmem_load_off`]. +#[repr(C, packed)] +#[derive(Debug, Clone)] +struct BootloaderDmemDescV2 { + /// Reserved, should always be first element. + reserved: [u32; 4], + /// 16B signature for secure code, 0s if no secure code. + signature: [u32; 4], + /// DMA context used by the bootloader while loading code/data. + ctx_dma: u32, + /// 256B-aligned physical FB address where code is located. + code_dma_base: u64, + /// Offset from `code_dma_base` where the non-secure code is located (= must be multiple of 256). + non_sec_code_off: u32, + /// Size of the non-secure code part. + non_sec_code_size: u32, + /// Offset from `code_dma_base` where the secure code is located (must= be multiple of 256). + sec_code_off: u32, + /// Size of the secure code part. + sec_code_size: u32, + /// Code entry point invoked by the bootloader after code is loaded. + code_entry_point: u32, + /// 256B-aligned physical FB address where data is located. + data_dma_base: u64, + /// Size of data block (should be multiple of 256B). + data_size: u32, + /// Number of arguments to be passed to the target firmware being load= ed. + argc: u32, + /// Arguments to be passed to the target firmware being loaded. + argv: u32, +} +// SAFETY: This struct doesn't contain uninitialized bytes and doesn't hav= e interior mutability. +unsafe impl AsBytes for BootloaderDmemDescV2 {} + +/// Wrapper for [`FwsecFirmware`] that includes the bootloader performing = the actual load +/// operation. +pub(crate) struct FwsecFirmwareWithBl { + /// DMA object the bootloader will copy the firmware from. + _firmware_dma: DmaObject, + /// Code of the bootloader to be loaded into non-secure IMEM. + ucode: KVec, + /// Descriptor to be loaded into DMEM for the bootloader to read. + dmem_desc: BootloaderDmemDescV2, + /// Range-validated start offset of the firmware code in IMEM. + imem_dst_start: u16, + /// BROM parameters of the loaded firmware. + brom_params: FalconBromParams, + /// Range-validated `desc.start_tag`. + start_tag: u16, +} + +impl FwsecFirmwareWithBl { + /// Loads the bootloader firmware for `dev` and `chipset`, and wrap `f= irmware` so it can be + /// loaded using it. + pub(crate) fn new( + firmware: FwsecFirmware, + dev: &Device, + chipset: Chipset, + ) -> Result { + let fw =3D request_firmware(dev, chipset, "gen_bootloader", FIRMWA= RE_VERSION)?; + let hdr =3D fw + .data() + .get(0..size_of::()) + .and_then(BinHdr::from_bytes_copy) + .ok_or(EINVAL)?; + + let desc =3D { + let desc_offset =3D usize::from_safe_cast(hdr.header_offset); + + fw.data() + .get(desc_offset..) + .and_then(BootloaderDesc::from_bytes_copy_prefix) + .ok_or(EINVAL)? + .0 + }; + + let ucode =3D { + let ucode_start =3D usize::from_safe_cast(hdr.data_offset); + let code_size =3D usize::from_safe_cast(desc.code_size); + // Align to falcon block size (256 bytes). + let aligned_code_size =3D code_size + .align_up(Alignment::new::<{ falcon::MEM_BLOCK_ALIGNMENT }= >()) + .ok_or(EINVAL)?; + + let mut ucode =3D KVec::with_capacity(aligned_code_size, GFP_K= ERNEL)?; + ucode.extend_from_slice( + fw.data() + .get(ucode_start..ucode_start + code_size) + .ok_or(EINVAL)?, + GFP_KERNEL, + )?; + ucode.resize(aligned_code_size, 0, GFP_KERNEL)?; + + ucode + }; + + let firmware_dma =3D DmaObject::from_data(dev, &firmware.ucode.0)?; + + let dmem_desc =3D { + let imem_sec =3D FalconDmaLoadable::imem_sec_load_params(&firm= ware); + let imem_ns =3D FalconDmaLoadable::imem_ns_load_params(&firmwa= re).ok_or(EINVAL)?; + let dmem =3D FalconDmaLoadable::dmem_load_params(&firmware); + + BootloaderDmemDescV2 { + reserved: [0; 4], + signature: [0; 4], + ctx_dma: 4, // FALCON_DMAIDX_PHYS_SYS_NCOH + code_dma_base: firmware_dma.dma_handle(), + non_sec_code_off: imem_ns.dst_start, + non_sec_code_size: imem_ns.len, + sec_code_off: imem_sec.dst_start, + sec_code_size: imem_sec.len, + code_entry_point: 0, + data_dma_base: firmware_dma.dma_handle() + u64::from(dmem.= src_start), + data_size: dmem.len, + argc: 0, + argv: 0, + } + }; + + // The bootloader's code must be loaded in the area right below th= e first 64K of IMEM. + const BOOTLOADER_LOAD_CEILING: usize =3D sizes::SZ_64K; + let imem_dst_start =3D BOOTLOADER_LOAD_CEILING + .checked_sub(ucode.len()) + .ok_or(EOVERFLOW)?; + + Ok(Self { + _firmware_dma: firmware_dma, + ucode, + dmem_desc, + brom_params: firmware.brom_params(), + imem_dst_start: u16::try_from(imem_dst_start)?, + start_tag: u16::try_from(desc.start_tag)?, + }) + } + + /// Loads the bootloader into `falcon` and execute it. + /// + /// The bootloader will load the FWSEC firmware and then execute it. T= his function returns + /// after FWSEC has reached completion. + pub(crate) fn run( + &self, + dev: &Device, + falcon: &Falcon, + bar: &Bar0, + ) -> Result<()> { + // Reset falcon, load the firmware, and run it. + falcon + .reset(bar) + .inspect_err(|e| dev_err!(dev, "Failed to reset GSP falcon: {:= ?}\n", e))?; + falcon + .pio_load(bar, self) + .inspect_err(|e| dev_err!(dev, "Failed to load FWSEC firmware:= {:?}\n", e))?; + + // Configure DMA index for the bootloader to fetch the FWSEC firmw= are from system memory. + regs::NV_PFALCON_FBIF_TRANSCFG::try_update( + bar, + &Gsp::ID, + usize::from_safe_cast(self.dmem_desc.ctx_dma), + |v| { + v.set_target(FalconFbifTarget::CoherentSysmem) + .set_mem_type(FalconFbifMemType::Physical) + }, + )?; + + let (mbox0, _) =3D falcon + .boot(bar, Some(0), None) + .inspect_err(|e| dev_err!(dev, "Failed to boot FWSEC firmware:= {:?}\n", e))?; + if mbox0 !=3D 0 { + dev_err!(dev, "FWSEC firmware returned error {}\n", mbox0); + Err(EIO) + } else { + Ok(()) + } + } +} + +impl FalconFirmware for FwsecFirmwareWithBl { + type Target =3D Gsp; + + fn brom_params(&self) -> FalconBromParams { + self.brom_params.clone() + } + + fn boot_addr(&self) -> u32 { + // On V2 platforms, the boot address is extracted from the generic= bootloader, because the + // gbl is what actually copies FWSEC into memory, so that is what = needs to be booted. + u32::from(self.start_tag) << 8 + } +} + +impl FalconPioLoadable for FwsecFirmwareWithBl { + fn imem_sec_load_params(&self) -> Option> { + None + } + + fn imem_ns_load_params(&self) -> Option> { + Some(FalconPioImemLoadTarget { + data: self.ucode.as_ref(), + dst_start: self.imem_dst_start, + secure: false, + start_tag: self.start_tag, + }) + } + + fn dmem_load_params(&self) -> FalconPioDmemLoadTarget<'_> { + FalconPioDmemLoadTarget { + data: self.dmem_desc.as_bytes(), + dst_start: 0, + } + } +} diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/= boot.rs index 78957ed8814f..9a00ddb922ac 100644 --- a/drivers/gpu/nova-core/gsp/boot.rs +++ b/drivers/gpu/nova-core/gsp/boot.rs @@ -24,6 +24,7 @@ BooterKind, // }, fwsec::{ + bootloader::FwsecFirmwareWithBl, FwsecCommand, FwsecFirmware, // }, @@ -48,6 +49,7 @@ impl super::Gsp { /// created the WPR2 region. fn run_fwsec_frts( dev: &device::Device, + chipset: Chipset, falcon: &Falcon, bar: &Bar0, bios: &Vbios, @@ -63,6 +65,7 @@ fn run_fwsec_frts( return Err(EBUSY); } =20 + // FWSEC-FRTS will create the WPR2 region. let fwsec_frts =3D FwsecFirmware::new( dev, falcon, @@ -74,8 +77,14 @@ fn run_fwsec_frts( }, )?; =20 - // Run FWSEC-FRTS to create the WPR2 region. - fwsec_frts.run(dev, falcon, bar)?; + if chipset.needs_fwsec_bootloader() { + let fwsec_frts_bl =3D FwsecFirmwareWithBl::new(fwsec_frts, dev= , chipset)?; + // Load and run the bootloader, which will load FWSEC-FRTS and= run it. + fwsec_frts_bl.run(dev, falcon, bar)?; + } else { + // Load and run FWSEC-FRTS directly. + fwsec_frts.run(dev, falcon, bar)?; + } =20 // SCRATCH_E contains the error code for FWSEC-FRTS. let frts_status =3D regs::NV_PBUS_SW_SCRATCH_0E_FRTS_ERR::read(bar= ).frts_err_code(); @@ -144,7 +153,7 @@ pub(crate) fn boot( let fb_layout =3D FbLayout::new(chipset, bar, &gsp_fw)?; dev_dbg!(dev, "{:#x?}\n", fb_layout); =20 - Self::run_fwsec_frts(dev, gsp_falcon, bar, &bios, &fb_layout)?; + Self::run_fwsec_frts(dev, chipset, gsp_falcon, bar, &bios, &fb_lay= out)?; =20 let booter_loader =3D BooterFirmware::new( dev, --=20 2.53.0 From nobody Thu Apr 16 08:34:48 2026 Received: from SN4PR2101CU001.outbound.protection.outlook.com (mail-southcentralusazon11012002.outbound.protection.outlook.com [40.93.195.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2778317141; Sun, 1 Mar 2026 14:04:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.195.2 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772373877; cv=fail; b=lQ7ZiIlZJwhkymhuHPk8SNgTPaNghvwVtuglRTx2yAf5lHDww/D4rhCvoDGL5zTgmYd6odcKf36eXQDtVOGhJbrOioeYm4ygPUEyFWOKLvZmfEFqjbTB8CQ3rivFI5i3AAmuo7V+IefEZtMuGTc+vH+++ic07q3HaWWhJMiC69c= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772373877; c=relaxed/simple; bh=Hdf0txdHZMsHojqGIAiyOzF9fjTXg9pnC85HJl5gpis=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=WdkeQFTsxOTNyxBqtkxid07sMUfOmIOcBQe2lSf5rGlS1gIH3TnUhz7FZhx4lhNfmnTl+tRBl0muMq5S2y2E6NSzr4a+4FwCof7hlHPYnySXuLJVZugYsWKnTCOOj20Ez6tNDa1KR6R4yhlN2Vh7inTbK49IcS+02r2BDdhpTZI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=o8qEyAGk; arc=fail smtp.client-ip=40.93.195.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="o8qEyAGk" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=ZtYPGMu81zPsbuOOJlTIHVpmJMJs3j7nxUHCg+930/hYnsblbHS4RhQS3WH+vZ0MBWZEZtdpcHt0NqTy73trJGSmwMwU8HXinz2qaEQF8X521/FEeRDIg/CfnM/Spkv0asGqfWeT2+YWuch0kPW6EA6nUSJXjgfMx5s5VirNgg+F9hlEWXNS1DViFPvaQdrKmYM6FX8c7GS/vEeYukJhftmfyJI67r/aVLxtPwjgvJ+kbUyY1dxQCSmbF2abANMPTQ7z4Nf6sRI6IqsMqiq5K2jof68lC+wYHAX+7rAahxZ0KGYhmiBfjDT2fjwoFVWfQH6rrXXtNJ/ivzZQcV4HXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ufSCBLZzhblP/LdxNde2CiCuCOyQCivSM6IIZX0xJBg=; b=YMyTusu0uqSsFvdrroV7ysAhZBdJweIohxzQ1S++Vpu88BUbB+on2ebOUBNsG1KtD+FfhjsBkiSwqkh9uDl1EzYBLTCsBOFrveIGKplyZmoUN2lafR+MuhR0ISEE4ay4kM0TU+7m8H5EKw2DrL0oziwqd7AnPINgqWjKHEVP1cGjDj9F+kRQQ23VQ6/kQANByrhxctB4uHFaDPwmPB3TXJKD5kWSRIENleel46f4ImvGMSWGgjNIuUUqgUit+6dgcJDalRGgfZhG1DT4MJj99CeZ2xo8Qz3DNeZt0RetPjKXpY3/QMoOVm3k3m+KUYf3xCk3+I9Hiy8GTma2n3afnQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ufSCBLZzhblP/LdxNde2CiCuCOyQCivSM6IIZX0xJBg=; b=o8qEyAGkAjLJUJBVcuXJNJ7kxrbNSxsUiAGJ9GODZcMLYB/ezlYhb/Vn+/qlTw5L21+sCum7wZ7H8FA4ihAGww5b3qkTLK6gFMeGhqR10awiudoFG0HyylXwu2vh90Koj3AplUk1vFQ+CPJY7rpOACfv8OKtsz9MNomMpkz+uYZetTv2TM1c2Au+X44adFjptbjXPgYEADjqt+GRT9hh14RgR5TeDdH+nqKyd3Yfzl8OpdlBL0FJQaG/Fz5NpgO1KW7G1r+dOcA2xsiUYZYwzNWL8dXnQz2aPxr3mKqxcRu1EafkGTif/V1J/9ls09DzVQu1hqE7TtoNuZoUSrk1ZA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) by DS0PR12MB6632.namprd12.prod.outlook.com (2603:10b6:8:d0::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.19; Sun, 1 Mar 2026 14:04:33 +0000 Received: from CH2PR12MB3990.namprd12.prod.outlook.com ([fe80::7de1:4fe5:8ead:5989]) by CH2PR12MB3990.namprd12.prod.outlook.com ([fe80::7de1:4fe5:8ead:5989%6]) with mapi id 15.20.9654.020; Sun, 1 Mar 2026 14:04:33 +0000 From: Alexandre Courbot Date: Sun, 01 Mar 2026 23:03:52 +0900 Subject: [PATCH v10 09/10] gpu: nova-core: make Chipset::arch() const Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260301-turing_prep-v10-9-dde5ee437c60@nvidia.com> References: <20260301-turing_prep-v10-0-dde5ee437c60@nvidia.com> In-Reply-To: <20260301-turing_prep-v10-0-dde5ee437c60@nvidia.com> To: Danilo Krummrich , Alexandre Courbot , Alice Ryhl , David Airlie , Simona Vetter Cc: John Hubbard , Alistair Popple , Joel Fernandes , Timur Tabi , Edwin Peer , Eliot Courtney , nouveau@lists.freedesktop.org, rust-for-linux@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-ClientProxiedBy: TY4P301CA0041.JPNP301.PROD.OUTLOOK.COM (2603:1096:405:2be::15) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|DS0PR12MB6632:EE_ X-MS-Office365-Filtering-Correlation-Id: fbe52652-ea5c-488d-fc47-08de779b76c0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|366016|10070799003; X-Microsoft-Antispam-Message-Info: 36m9TImnpwYjXVWTISRE/Usaticd6TqyOKzPK8yhjOQCbDIEzhYvzVvyCl7LdW6rx+MJjmO/Q4O/u/whGzlDD35uDwQrtaZnTTVyvZjA6UcQ4qepZPVTyJY6pbUXSzujtRH7hJZFvAtAJyqIYRxGPK7ocCOx5TseT6QCKm0QRuInej0y/r4QkKx7kiYRDSCXDRnGICWO/hEEQu+sekulMu1ge6gQAEXD6aNq7DTCx4CzdWtnI5jhEFgD/f4a6NdehjVS6WyCBtfC6DR1V9jtJ/k848KuReCL1Mfw1jZWZyl4oP83gOXRoZbaKOocGYqS8M8fjkkczlaiZPJS43IN8I+NMEThPYmCOg/x4YOqLvqaEvl4c4vTPc0N6NQKvRM+jYm6gX1ZMx07WY6/NY0cGMTLilarvnPzJ7Q6nrfRnOTKrCrb1tYLEPm5eEt9srZDdoFx1VWbyBIhoqoaTj9MQ5E+oDPdSjefwFrfQmemIxO5Yq1xHV+pESe+Lx7TGUySzDEhEfu5ZSn/L5tb5P527tzFENyk99uT83jrQgkxYzQTC+wdosqyWasE0paw4a1BE7WRlWao+kfDET1WvlMHTHpltk7V+IwriACOcU7aQf4Rlx2GLSsxg9TpAispEviQ264jBZAqO/mUml7IjuwSgWm9XERWB847rnFxXUI9kkUgkxkK64QO79xvAkyQ5Dv+2MT/7ZA6NjtVktm82tbIyBwVhOm1EchKGUVYDc5RcLY= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CH2PR12MB3990.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(366016)(10070799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 2 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?aTFJWk5mMHlTRWdzWVAvSjcwWDZuRVluWUdJWDVQdWVHc3YyK28xd3J1dXpi?= =?utf-8?B?UVp6akttd0FoekNLVHJOcGVuTXkra2lXa3hNMWFob3BUYmdVVVFFeUVMN2xO?= =?utf-8?B?WTA5MkJvcVlLY2dVVDZYR21HNHFPRElpTGZPbG8wUzdQTkh1bUtmTmVURHpk?= =?utf-8?B?aFNTUGh4MjBOWUw2SlBTb1gzVUd6RXVKZTBlTHkrV1QvL1cxZFpuTEx3VGtz?= =?utf-8?B?ZHpreDVtd3VkWEd4QjdhQ1EzbXl2ZlZtaGpXNEs0TkwvMnB1bmtjYmtIRTlR?= =?utf-8?B?NTc1YVp0OVcvOXVTYnluejN1NTg4bTkyZEhFRDNBUkozbjdBS2tMK0VpNkw4?= =?utf-8?B?N2xNSUlJY1NxMmo3VllLNnRHQVZ3VnhaaVY1aDRHOWhsVDJ1Ty9kRXh0Z1Z6?= =?utf-8?B?cmkrS21RUUQ5WTdLOEJ2czB0akV3NkJkcWpORE9SWVdDS1VOQVF0U0VyWEVL?= =?utf-8?B?YUNZckxaZVJrT0FZK2dHcW5QZ3ZJaE96UVNIWmtMVWlLOSszdW9SYnFvWFZQ?= =?utf-8?B?ajJ4UUxPRmFYVVFaWXhPamFYMG5MMlBHTVFuVFFBYWVnMndobHo0SDcwUWlP?= =?utf-8?B?Q0RKaTg3UkNjS0E3WU81SHc2bFFidDgrb3hlNmVnQXZuMGFud3Jlby8ybUY0?= =?utf-8?B?VHkzb29neVZxVUp4MzRybm1BcE9XOUd3N0k4eDduK3NwSTRwVXhPZkYxS0g2?= =?utf-8?B?WWtYOWVUMVA1QXp2UThvdjQyUk84ZmlySXFQTHZlVGlwMHF5aTJCMFI0UXBX?= =?utf-8?B?eWQxYXNrZm1LbzRkOUZiaDVxL2VDaDRqYS9ZVFM4YUFJYzF6N2k1U0FtdkNs?= =?utf-8?B?M3FaZms4cWpnZ29ibkthTlZrS0JFUlVOSUVyU2RrRU1HVDRVbDQzOGxEbnU0?= =?utf-8?B?djZVZWYrc3hQOG1mSFQvNHphN0VLRHdvVzhWdWdYUWZPU2NFczd4UzdOd3dW?= =?utf-8?B?Q2F2Z1J6N3gwbThEc2tIa00vNTczMWFzTERDUnJSTkJTQ1ZLYnVLdjRwLzBt?= =?utf-8?B?a08vMWR3ZmZibjJnQjZWaklOZ2dpa1AvNTFtTDVqS1NEbXlpOThVZ09GaW1P?= =?utf-8?B?bkJSUDlCM29jUnZkOVJucXV6RmJqQXRBbEp5UlE0R2FZM1lwN1hJUDcvMENL?= =?utf-8?B?diszc0hqbDEwL3NzRFkxQ2FhMTY0SGZiZmdmbzBjdHhMY1kzUmFIMnBGU2Z0?= =?utf-8?B?RUFpWjFmT1MvN0I1ZEN3Z2NSYnJJZjJlN1NUR1FFVG9Lb3BFSk1rZGJYUlRj?= =?utf-8?B?Qko0enV1SWVuNjV4RjRoRk1rQzRvSklmMGxDNFEzSVNuOUhiSFlKanVjMHBW?= =?utf-8?B?LzZKNkN1cjJwanVOZFVoOGVhLzdWYW0wQ2RJRGVGaVFDaTNvYmR0dm94c0pJ?= =?utf-8?B?N2ZGd0d6Ly85emdhaVZUWHdRdFB6b2tQQ0xsc3piT0FzYWljdFFPOHNuUXk2?= =?utf-8?B?dDRwVStwOHowR3ZLUU9BbkVPeGt3S0tPWnZ3a00rWlErQXVWc0t0YnBUaUww?= =?utf-8?B?bmpWMkYwNnl1UHlaSkJVVmpNYjV5am44bnNwZjBzVWlpNXhCak1FeHplZUph?= =?utf-8?B?d0lhZXZFZ1N2cm1lcDdmY1ZXMDVlcEsxK0dSRVFjenZycU85MDZHNXo4RXYy?= =?utf-8?B?bWc3RmpDcWd1dThYTDhwSGVreXpzZjZ4RGdpVXhPZHEzY0UwVmdaM3dzOUQy?= =?utf-8?B?bjZzTzVtaGhUTkxsSlpLcTFWcU1veVJHdUxBSjFnYXFZZWdMbUFPYXBsNTdw?= =?utf-8?B?VzBESDFJck0rZ1pqaDJxSWxHWDBpZlZjeEpsQUdnRmZXdndSMXdBM25ORUtB?= =?utf-8?B?bWFpYlFlUFR1NkR2S21XWkRqWnpTNzltazFmQ0MxZTV6djJYN1BtTHlGQTM4?= =?utf-8?B?blVWR1VmOUNVQXlURkhoc0FleW5XUXlxK0FuQ2xpVGgxZmFWZHlsTHlJV05E?= =?utf-8?B?dDIwRzdXR203cXlnSXN2RXZyM0FKYUhFQk9vdkxMT2tqczNCWkpDdFQ5UDdr?= =?utf-8?B?SkgwMHRuZmtXTkkrL0k4WUZhRExiNnoxWS8vbzRIczJNZUxEM0Q1RUxVTFdB?= =?utf-8?B?QlVwNytRWHd4aFJmVDN2bWVkRFVKRlpVMmpwQXNHdmcxbmpodTY5ZWUrNSth?= =?utf-8?B?Q0NrcjEwcy9oa1o0RTU0RmR4MjRKcG00KytwUGIrMXgwZ0gyZlBpM0h2T29O?= =?utf-8?B?ZnljYjRXUWl5VzRDYUJYeXNRbkk1N3g3WVVwR1ZGQWUyRWtVa2NFRnRSQ2FS?= =?utf-8?B?RVhyMXJpWXcwTUhSWlhDOGFwY0tDeW9MVVlKUUdEcyswQ3FPaXp2QnNuZnkr?= =?utf-8?B?bW9wWGV0ZW14aEx1ZHNQSVB6eXhOSDVTWE8vcGhBQ1dRODBjdWMyQkxiejBk?= =?utf-8?Q?8+ppiTNfz06KCQPys14w7GR2wsRb2BGwzS6K+9fsQfV1m?= X-MS-Exchange-AntiSpam-MessageData-1: xL81/dhz0SmNjg== X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: fbe52652-ea5c-488d-fc47-08de779b76c0 X-MS-Exchange-CrossTenant-AuthSource: CH2PR12MB3990.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2026 14:04:33.0354 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: XoI/DhNs9y/bmhpbNVVqSB/d9sqMNbzz7s6co5121g3s/zw8il0O3fxgRjk+9G9BXxvFKbPI38XNzS0edrBiVA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6632 We will use this method from const context. Also take `self` by value since it is the size of a primitive type and implements `Copy`. Signed-off-by: Alexandre Courbot Acked-by: Danilo Krummrich Reviewed-by: Eliot Courtney --- drivers/gpu/nova-core/gpu.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 60c85fffaeaf..c14d411c6759 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -92,7 +92,7 @@ fn try_from(value: u32) -> Result { }); =20 impl Chipset { - pub(crate) fn arch(&self) -> Architecture { + pub(crate) const fn arch(self) -> Architecture { match self { Self::TU102 | Self::TU104 | Self::TU106 | Self::TU117 | Self::= TU116 =3D> { Architecture::Turing --=20 2.53.0 From nobody Thu Apr 16 08:34:48 2026 Received: from SN4PR2101CU001.outbound.protection.outlook.com (mail-southcentralusazon11012012.outbound.protection.outlook.com [40.93.195.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CF7C31B80E; Sun, 1 Mar 2026 14:04:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.195.12 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772373881; cv=fail; b=uQzs3rpX7yEaTHQs9tiVT0IQcljgdevSgU0DkxAD7WbKjmduKm7oDochXZRpbWAApL4cpk8vXiJpbyONschVUp/Su55S4InqXPkVNWUyJzlFAE2aDo8Fu18OukOmBpEKZwE1LbseFRNA07qR9AgTEt7tR8hkOs04CygAHD1u054= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772373881; c=relaxed/simple; bh=Q4qBBrva5+Z8fPoEDTI4B8a/nGVNLhKu4nMOCM7bTyA=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=jQB715fekcMAnSSv+2Bpu4nI4qqpZ0E7aTq+PPfleh49IaPcINEI6f9p+Xe7vFjAmX8SUI8mmu/K3MaIOHbEzcheIfVyBGX+TlGZSOkR8CMQTKN0nU7oqBi2TE0qq65wPcxgqVge5xSpmw/hC6tfCQ5SHtzflKEjd+84zTjAWSk= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=DYHGDwMs; arc=fail smtp.client-ip=40.93.195.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="DYHGDwMs" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=JHfe/PUNebyx+ZeCSG7sx47i0g+AguXQ8tnSPS5fLcURpDvXp85jWiZ739uFyr9MUqaALgTsHz72bN5ah9IO3VOnnkO+mq972C0brhkEcSvWgznPPNSTItlGq3ur1Tfn9f+KNypcgijpAi0+nY4IlTFA+NJ1CJAGAxV3XCPDsy4Ij6OBYTErnYF+kDmfS59dedcoBvavlNGPkFORhOoEs296LGcVPofLJvEuqmIqq6VI8+kbnGeCeABFXn0j8yBfX3msUnih+pnoyTCL9TsFQan7P7nvqYhIFZwQOA4uKqQsX8HtAQya7eOD6R8ltcJUQe6405Nr3K7DSIIIe7Hwiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=n6qRJevJnyZ0nVdHsqUErwx2Tah8MwUipzOcOQHQFmY=; b=i3VOvXDSqD99rKPYJtCg/YhJVu0QZnxosBF+5usFT0xonAKzR4xlcVam5u/EWVpaBMjxU4VQqNaaRszsxLVYG7bQzIm1AQr/M/F0uK5fV43a6s84OU0YoPSS+OaWbX47dZVRRWvkMuCf0sz8dF3MWZCkWGduvIa5T9GrpYudFvuF6JHlkkS8Yn01L0xZBISILTBImQiK3Sw/ndBnrAGnlAK/tJS4QlzTNawwAOrlQQmxRhQGKaUtuMetgSRtGGuZZzT13bWP1UGpYs8K2WaKZ0a5VNOFGkSjgGgR0ipIXxx1a1l1VQ2MBB9qA4VWDVYaFQR4VNa9iDUmu4BQ631btg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=n6qRJevJnyZ0nVdHsqUErwx2Tah8MwUipzOcOQHQFmY=; b=DYHGDwMsWxhMLNdJKJAQ+zZ0/5T0+z9HTzLwpo4l4xxScDf5MeK7FsFp+ulpwZZ4kA+8umfjYZTQa6V/b9KP40XJ1qF3TaqLFDW0iCz/opbIURsTFxzv7FI1YUVlVSHQSBT+CSsaSzRpCiYBeX9JetjTQ+mpMjxigSJonGA+ZaXo4+nZfTL66gj4VFEPozwHX70ibcChSY5Ds/ZhHdbrIF6ztxIgeoZ4A3aAeNe1CEif2Ew/iez5M+cBspQDygXchlkB2iOtzIzdVVgYwTn/m75JC2sBMG6bnx+IKY5CygZqBmr+mxskSTpOK9qnD/mO3fwvuxnQOxQWMVrbNS66AA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) by DS0PR12MB6632.namprd12.prod.outlook.com (2603:10b6:8:d0::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.19; Sun, 1 Mar 2026 14:04:37 +0000 Received: from CH2PR12MB3990.namprd12.prod.outlook.com ([fe80::7de1:4fe5:8ead:5989]) by CH2PR12MB3990.namprd12.prod.outlook.com ([fe80::7de1:4fe5:8ead:5989%6]) with mapi id 15.20.9654.020; Sun, 1 Mar 2026 14:04:37 +0000 From: Alexandre Courbot Date: Sun, 01 Mar 2026 23:03:53 +0900 Subject: [PATCH v10 10/10] gpu: nova-core: add gen_bootloader firmware to ModInfoBuilder Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260301-turing_prep-v10-10-dde5ee437c60@nvidia.com> References: <20260301-turing_prep-v10-0-dde5ee437c60@nvidia.com> In-Reply-To: <20260301-turing_prep-v10-0-dde5ee437c60@nvidia.com> To: Danilo Krummrich , Alexandre Courbot , Alice Ryhl , David Airlie , Simona Vetter Cc: John Hubbard , Alistair Popple , Joel Fernandes , Timur Tabi , Edwin Peer , Eliot Courtney , nouveau@lists.freedesktop.org, rust-for-linux@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-ClientProxiedBy: TY4PR01CA0118.jpnprd01.prod.outlook.com (2603:1096:405:379::15) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|DS0PR12MB6632:EE_ X-MS-Office365-Filtering-Correlation-Id: f06ccc66-3bca-4402-063c-08de779b791b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|366016|10070799003; X-Microsoft-Antispam-Message-Info: UuEX8btFhJovvc2ZEJWjGlxXNFGTG5K/SUkLUEcuMyfRx2BBHl8Hi66V6A1Mrsog8j0lq0TmUhrCs1DqlLAIbrL69MnKRh9o+qlHRQ3ZBREglAdApVA0kWQsh6Gm9y6BhMXtO61V0t7jAICAlK/Q5xFj6h/zL2cDs5PIfHnGWJ5wvmrs9vTXWXtn+lOmB+nlKwx0hFYZyDueuGEXLzQHAnqXC40jnc8oa0mOyB5+e8huDdqfvSxzL5Nn+Hj7fG2pKL3UqOd4cxv1g84E8VqHYwQ5cEm6mifPapyXxSD1AGqW76DIkjAXIuwjPa+6ToJdq2o9Fo1KW5YCB9Bb+CTgOeu0V3Eq2iZO3jxGQlDgOpFx+PHjGOVRrUAYKI4srFnT7vGbi/pntOk14EbRm2G1V7jWaxxJfLy79occIpYTVf3I3VS6S/N0kR0Ngvkcm6ayKl4ZwgPkduEVMU7WHeSpDZjFq4sUmTRFCcaid/0nrn3M2a5d5aZzAg6yAlRGGeDoQ3p25x4eoQ+QePL0AHbW6OnjYHBCKqPb8YGOGwl6KTMzfu+xcS6OS6Ui0N78MkX+9cZCDeWPvc2/Ze0v4kfYUNpgy6TTIgBeajUC4+y/iAhucdYBY+relC4JRKiyiH3PYA13+fxWrQgl89FzQn8+5NEwcDO921+dedoMfRjVUdNxZKQuy5jL0uSOLCgNOPgSFnZp1+wgpHaGjuPbeY+RhV4fJ7+HpErFqg2iDDGYEr8= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CH2PR12MB3990.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(366016)(10070799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 2 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?YlIwbUM3R2JqTnZEOTZwNmZWNzlSLzI0TEhLSjQ1WnMrQm41bmZMNjIzNzFW?= =?utf-8?B?U08yeWM2ZEx5NmdtODRLZzE4dElrVUhOeDFYMk1oWFBSNDg0MDFzQ0xVS3VQ?= =?utf-8?B?THMxcGlacDVHTW5DdGR4djRxWDl6NEJna1BQLzZuZURLZ0UwZStEVGR3WXVw?= =?utf-8?B?eC83TFpDelZod2FLSUtEb21Mc3BJNWlVaUtmbFdWUUNwSHgvcUsrNXF5NlJq?= =?utf-8?B?bVRwbjh2djQvSjlsNCszZWJRV1BQemROTEtHZ0szMzlMMEI2UXhickpqYnNk?= =?utf-8?B?YjBBbUtXbGFSU2lqVXdJSWIzb255TE93YmJRQnIzRHdGeXRZRCtCdlRjbFFV?= =?utf-8?B?dFlOM09hbTF5U1VQOEx0UUhjQnF4L21wZnRSRFNDT3NmT2JmSWJ5aWQxN1h5?= =?utf-8?B?QmJZSUowNTM0blVXam9BQWR3UlduTFFsaUFQbkgvUkMrdW81dkZkZWFnZ2Jp?= =?utf-8?B?WWJDUjEyVnBteGI5OGF5K2gvNHBsRFRoeEpXTlI0ZG5XRGxiUkhtUWZmQjhY?= =?utf-8?B?Y2lOV01wSzlYNmhaM1lJanBTdTQ3cSs1S0t1NXZVZE1ya21KMnJvMFUyUk9K?= =?utf-8?B?b1B2UGJhbUxNbUg4V2FucXRnQUxtdHRnSEUrY09vdGdYSkhDVlNxVHRDZzJT?= =?utf-8?B?WmM3N3EzWDJIY1JsUyszWU1PTThvcEdOUkVpeFhlQWZTWTUzOHlIM2Zhd09q?= =?utf-8?B?a2E0blhYTWhyY1haWko1NFdFdjljR3NVSHR1N1pDSVE5NC9FaXpIdDdLRHRx?= =?utf-8?B?blBqUjFoZExSZmdoUThsT2MyTzZqL3hzMSthUGs5VjdTQ3JvTFJkNEtoTkV4?= =?utf-8?B?NEFLS0NHQ3JaNWUwMk5RTXBXM0FMMVNFc3FRR0tJbHJ5dGRscWtDRmpwaVNM?= =?utf-8?B?alpGMjFlbVBBeHZ5ZkZOL1JkUHJmeGhDZ0RyWWxTSGx5Wmk1T00rSy9vUXhM?= =?utf-8?B?N2tsVGR0aFI4czBLQnZBOERQMkxjb2Z2bjhPdDFQaGFuTTBrOEhsQ2J2Smk4?= =?utf-8?B?QXVXczQ3UG5rSlZFSVpNNEdMUTFCa3cxd1h3QS9yN0svQ0RCNFFVUHlTWTFY?= =?utf-8?B?d0RON3lxTmFyYkZmMkQ3eE9uWFNzM1QzaUdaMnBQU2RwRkR2K2dORGo4WFZQ?= =?utf-8?B?VkQ5WW56Q3dvL3lKSjd6dUhQalRzRCtzOFh0ZnprZElsWFNyYXpwSE5yT2pQ?= =?utf-8?B?NFlpRzRXTmdNaFc5VzFMMUdiWUZrbW1SNHBlVUtjWVk3cUMyOUIwTFp0TUlC?= =?utf-8?B?aytsclFLVy83VzdSVE5oUzVXZGFBai9HWTV1dDNwazM3THV6OUNZYjR5dU5U?= =?utf-8?B?Mm1YSzFzZ0tzY3RDQWlmc2F0WE1PYlltRmRNaVZUM1lxTXVZbU02YjVrQnVj?= =?utf-8?B?anBmK1BZbUhlMjJUenNpVmpsTGp6ZHhhZjRLeUxOcDJXcGM0cVphSW1mYkdS?= =?utf-8?B?eURoTzFybkcyc2RLaEg4a0E2c1FOWWxNVEp5UHIyOEN6cGtxa0hOQzFhY1RK?= =?utf-8?B?cEdqa2RwM0RlZ3JSRXViUXJidVpEQWxIbHROZGNWRjlkWVA5OHk5MGJUdk5i?= =?utf-8?B?bllqUW96aFJRN3FVZnFZdUN6NDRITzMxL2Q2QVR5OEYvd3pVUk5ldXJobjR2?= =?utf-8?B?Rkh6V0pkS2FzZUNrNHRMN1Q3MFpsb1NQRTBydmYvNjNTL3IzZFM3WHlUQmwv?= =?utf-8?B?dlZGTzhGK3UwRDdyUFZwVkxBYi9yQ3c4citFTUpCN2padlBOZEpxT0lwMDUw?= =?utf-8?B?czRVYjFWWG5XbjZYVzBadzZYek1ndW1mMmVkWC9jR3k1L1JPblhCS0VHeFVU?= =?utf-8?B?amhBV25NWU11S3hUc3MxaC85cVBEYkt0MEVreW5yRE9lZTJ2SWcyOVAraEIw?= =?utf-8?B?MVRyR2NKUDdka0xLSFRIMDNyS1crUnRSWHRZTUJySTBPZlJ4RllyanYweFo2?= =?utf-8?B?ekVQMDdKTHpkVDd4ajRoYWptdG42RVV1dm1NQXhjeVlxNXBoYXlKZHdCWUNE?= =?utf-8?B?UXNRd1ZoV0ZxcXo3ZWQ5ZkJ6dWwvWnFEbVFTUUJIU0pHVWZCMy81czhVWjZh?= =?utf-8?B?WDVGKzBITlNHY210ckVkcVY1dGYrck5TMzhMdUdKZDNZOGx3N0N6bUpOTG1o?= =?utf-8?B?YmdWQzBOT3hqRUtRc1FwQUtxRUNaYXVicUJxYXUzS0dydWpyMjJwdEI0Qi9K?= =?utf-8?B?akc0ZGNBRWovd2lic1NiRXhJVVptaU9XMkhYLzFWRG5EOWZMcS9CUUNLbXpT?= =?utf-8?B?bmtWRjdXUUYyR0x4TC9nc1BXK1hSZzNFSFRNeEpXUEJTaW9hdnlyWWFKRTN6?= =?utf-8?B?Zkw4VUZrUE94RXc5aWJDbmJsd3k4aWdIZkVLYklVVkFROWtvVzBKaDk3MjZi?= =?utf-8?Q?IimBwLo4v75S3A6zn7Qqh5GPAbTkHIzxmuEUHLZr9Q3ZF?= X-MS-Exchange-AntiSpam-MessageData-1: y9g2xlPO2nMqXg== X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: f06ccc66-3bca-4402-063c-08de779b791b X-MS-Exchange-CrossTenant-AuthSource: CH2PR12MB3990.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2026 14:04:37.0038 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: jGOoe68OhlnfOG4iSIbSqSbEegnFsB9bpE5NtsUkFJvXK/tzd/Tzo/tXGmf02s97Fuwz8uQBGPpg8kWrvC7ZXg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6632 Turing GPUs need an additional firmware file (the FWSEC generic bootloader) in order to initialize. Add it to `ModInfoBuilder`. Signed-off-by: Alexandre Courbot Acked-by: Danilo Krummrich Reviewed-by: Eliot Courtney --- drivers/gpu/nova-core/firmware.rs | 21 +++++++++++++++------ drivers/gpu/nova-core/gpu.rs | 7 +++++++ 2 files changed, 22 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index 6d47a6364c79..6d97fecefa74 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -415,11 +415,20 @@ const fn make_entry_file(self, chipset: &str, fw: &st= r) -> Self { ) } =20 - const fn make_entry_chipset(self, chipset: &str) -> Self { - self.make_entry_file(chipset, "booter_load") - .make_entry_file(chipset, "booter_unload") - .make_entry_file(chipset, "bootloader") - .make_entry_file(chipset, "gsp") + const fn make_entry_chipset(self, chipset: gpu::Chipset) -> Self { + let name =3D chipset.name(); + + let this =3D self + .make_entry_file(name, "booter_load") + .make_entry_file(name, "booter_unload") + .make_entry_file(name, "bootloader") + .make_entry_file(name, "gsp"); + + if chipset.needs_fwsec_bootloader() { + this.make_entry_file(name, "gen_bootloader") + } else { + this + } } =20 pub(crate) const fn create( @@ -429,7 +438,7 @@ pub(crate) const fn create( let mut i =3D 0; =20 while i < gpu::Chipset::ALL.len() { - this =3D this.make_entry_chipset(gpu::Chipset::ALL[i].name()); + this =3D this.make_entry_chipset(gpu::Chipset::ALL[i]); i +=3D 1; } =20 diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index c14d411c6759..8579d632e717 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -105,6 +105,13 @@ pub(crate) const fn arch(self) -> Architecture { } } } + + /// Returns `true` if this chipset requires the PIO-loaded bootloader = in order to boot FWSEC. + /// + /// This includes all chipsets < GA102. + pub(crate) const fn needs_fwsec_bootloader(self) -> bool { + matches!(self.arch(), Architecture::Turing) || matches!(self, Self= ::GA100) + } } =20 // TODO --=20 2.53.0