From nobody Thu Apr 9 15:57:22 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6E2C15539A; Sun, 1 Mar 2026 00:51:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772326283; cv=none; b=rTk0AM8C8ZT73kb6QriyEGo109ZjGFhHZFz7O+46oJtIBrjR1nmo+MBwmz3ebo6eFS1SXu+g1pnL/S6T2WVM/ZgXwIo4c/+RkQykmGoM5w+blFfEcdEn7zITeAggmjVrDRbjHLCfu04g+KakRRA9+VI8P1QuQcaIdxfJvHoBGzQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772326283; c=relaxed/simple; bh=fegcXTqMjiIV206X2z+HxUY2Ah8PqoEDD+xs2idN8pw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=B6AMh1SIXhN8UBqsE9jRcboMuvx0FUbunuwkdkpNUyi22ARIGx9rIpAkvwEBP+jgBHM++RyfMyOkWY99UXCnYP4yWKWag+Jn0Yg84vYVIeU/p7MXAeO7oweW6atZ2eo2iY6/eBZdR28S9hZRJrj3i/jH2Rk6cSlXDzZgtbk/7Qo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=pTr/hWS1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pTr/hWS1" Received: by smtp.kernel.org (Postfix) with ESMTPS id 76D7AC2BCB2; Sun, 1 Mar 2026 00:51:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772326283; bh=fegcXTqMjiIV206X2z+HxUY2Ah8PqoEDD+xs2idN8pw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=pTr/hWS1hYZQr+rVY4dv0x56mYnsmxj3P6uADyZ0g6nXfkjFH8wWxxRHzthYXB8jy /OUxN01UItLcIbNoR4+A9xAHPl2zUWBc1R8VJef5lYpXIsA6zZxvZbE9un1q/AjAQ/ fMBiqK3jQ+DS+zhyI+F7iwYYAcYm7u+BiioeEyqCEGLtGCOc9OcbLhnqWSSE6nVCIk KlHn+zo3eJC8JUB0rFIylSIxkmt/hiESHyuVJ0kMcjDHNsUxHQTUAHdKG/Wc23dTBq 8wu70v2NueUZe5nlPCbiNRLiq7i0kxlWbOuACBzzkbmxHQMXGUqB/QJrvDQ2Pngvk+ QE0DxQlbPk0cQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69030FD004A; Sun, 1 Mar 2026 00:51:23 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Sun, 01 Mar 2026 01:51:23 +0100 Subject: [PATCH WIP v4 4/9] media: qcom: camss: Initialize lanes after lane configuration is available Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260301-qcom-cphy-v4-4-e53316d2cc65@ixit.cz> References: <20260301-qcom-cphy-v4-0-e53316d2cc65@ixit.cz> In-Reply-To: <20260301-qcom-cphy-v4-0-e53316d2cc65@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , Casey Connolly , "Dr. Git" Cc: Konrad Dybcio , Joel Selvaraj , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3845; i=david@ixit.cz; h=from:subject:message-id; bh=POblRjXDkh18ym7OpzBorCGs1kZvG0b381or0ZV6l/s=; b=kA0DAAgBYAI/xNNJIHIByyZiAGmjjYig5aDT7OYPjWMZPx9Az51jCHsFYOQU3Ep85A3kPuij2 okCMwQAAQgAHRYhBNd6Cc/u3Cu9U6cEdGACP8TTSSByBQJpo42IAAoJEGACP8TTSSBylZcP/11N xDps7Ztfm/Cxri/RxCzyQ3rkhcHTZjnWYm5dWSztfHEHWnPcE2WjlqGr1SOrt5aDcfCwa63XEwH QwlC24fs7silhmNbm1rEXWZV66/89QcJi7JncZY+ZxcP1tXjWgIFvbdF62y3YGYNasZ7KQMjp3/ G6A7M0CacaWFXEHIVWCIH7KhLxsOHzKYaRxSFk3tO1KJz0z0OuZNTzls2gOYRTN+i1pip37qgk/ zxtq/Pv1uCLsiVa9DHuktSD6JuTM3ZItUzkJsNXszZ70Ph8epeMSoaW6qBeg2BleqYOyM/sGlQf CY7Ox4LVPiytahyaASG31BfmBuAiCJe6CDYvBo+7IuwoV1b0fz/HaMZui6KD7dQb1w6tZq4QYvB 0K7lNVWhbMHLjTAKDzIUhTtX2L8oyqkUdKfwwTeY52MAk9aQv1umhrxFkVNxEbRiY635P2ATgRZ 3IoOa2iat7OroWbT/A1CFpCa9erjHc7k8ZdIGy0HoedyrLtAEBMPj2sO5ovw1lCBUJH1owE7xy7 vSzJzYxhXELw5pNOC2rSTX3azgnBUMlch6PcJ/TypdrBD9y/HHxAMVbcubrZR7hPkKdSlQln3Hd /y/zjeWeJYh9R0yR4J8ew8qYIxsn/WpFEgmngi5DuXFAtVyTrw2RYydjSvZColpluU6JYxbHxvJ vFC7i X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: Petr Hodina The lanes must not be initialized before the driver has access to the lane configuration, as it depends on whether D-PHY or C-PHY mode is in use. Move the lane initialization to a later stage where the configuration structures are available. Signed-off-by: Petr Hodina Signed-off-by: David Heidelberg Reviewed-by: Bryan O'Donoghue --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 91 ++++++++++++++----= ---- 1 file changed, 57 insertions(+), 34 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index cf83c9e062b81..9748208107222 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -1048,6 +1048,62 @@ static int csiphy_lanes_enable(struct csiphy_device = *csiphy, u8 val; int i; =20 + switch (csiphy->camss->res->version) { + case CAMSS_845: + { + regs->lane_regs =3D &lane_regs_sdm845[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sdm845); + } + break; + case CAMSS_2290: + case CAMSS_6150: + { + regs->lane_regs =3D &lane_regs_qcm2290[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_qcm2290); + } + break; + case CAMSS_7280: + case CAMSS_8250: + { + regs->lane_regs =3D &lane_regs_sm8250[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8250); + } + break; + case CAMSS_8280XP: + { + regs->lane_regs =3D &lane_regs_sc8280xp[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sc8280xp); + } + break; + case CAMSS_X1E80100: + { + regs->lane_regs =3D &lane_regs_x1e80100[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_x1e80100); + } + break; + case CAMSS_8550: + { + regs->lane_regs =3D &lane_regs_sm8550[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8550); + } + break; + case CAMSS_8650: + { + regs->lane_regs =3D &lane_regs_sm8650[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8650); + } + break; + case CAMSS_8300: + case CAMSS_8775P: + { + regs->lane_regs =3D &lane_regs_sa8775p[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sa8775p); + } + break; + default: + break; + } + settle_cnt =3D csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate); =20 val =3D 0; @@ -1119,49 +1175,16 @@ static int csiphy_init(struct csiphy_device *csiphy) return -ENOMEM; =20 csiphy->regs =3D regs; - regs->offset =3D 0x800; regs->common_status_offset =3D 0xb0; =20 switch (csiphy->camss->res->version) { - case CAMSS_845: - regs->lane_regs =3D &lane_regs_sdm845[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sdm845); - break; - case CAMSS_2290: - case CAMSS_6150: - regs->lane_regs =3D &lane_regs_qcm2290[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_qcm2290); - break; - case CAMSS_7280: - case CAMSS_8250: - regs->lane_regs =3D &lane_regs_sm8250[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8250); - break; - case CAMSS_8280XP: - regs->lane_regs =3D &lane_regs_sc8280xp[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sc8280xp); - break; case CAMSS_X1E80100: - regs->lane_regs =3D &lane_regs_x1e80100[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_x1e80100); - regs->offset =3D 0x1000; - break; case CAMSS_8550: - regs->lane_regs =3D &lane_regs_sm8550[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8550); - regs->offset =3D 0x1000; - break; case CAMSS_8650: - regs->lane_regs =3D &lane_regs_sm8650[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8650); regs->offset =3D 0x1000; break; - case CAMSS_8300: - case CAMSS_8775P: - regs->lane_regs =3D &lane_regs_sa8775p[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sa8775p); - break; default: + regs->offset =3D 0x800; break; } =20 --=20 2.51.0