From nobody Thu Apr 9 15:50:06 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97EAA3C465; Sun, 1 Mar 2026 00:51:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772326283; cv=none; b=eSHsr7p/4UtchXj6NRhB6uTGg5V5HBJXO02uHZNu9P1euv+r4IVn/cu+WyCZco4Blv6+I62oRxRvAv/z7DJFxYXwz7MDefBGoKBMSUUzgIJur5vrepWkhbzFYpoKMqlQKvvpa9wNoSbDgBsR9RjK3LVlE5529Haism1lYZ85S88= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772326283; c=relaxed/simple; bh=Uz6QZP7yrFfNujd7Te8dRhcRZJAQIGe3Dv8OgOy8FUo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UVvZmz49yhROOw1jfRjqnhFnC7w7mbdIe6/ipw0e/5dobjxrFdm47EImLhE9hmpXdp1M4k7ZTk7UuXuzkLBondA/ZgdZO9hEFFI0mwgAa+bbqU+QuFTMWc7MnSbeqeLeqoyUxQL9Voeg55e9KICrRP703RTcgwltZ8c6RE8wmY4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=u6M9lW+z; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="u6M9lW+z" Received: by smtp.kernel.org (Postfix) with ESMTPS id 53477C2BC86; Sun, 1 Mar 2026 00:51:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772326283; bh=Uz6QZP7yrFfNujd7Te8dRhcRZJAQIGe3Dv8OgOy8FUo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=u6M9lW+z0FR4CJhJ34Gzt4XAUz6+FLeViVzQVcqFjsklvtXY6gcOxVq9iqDoeWXzN nuqVUMO8PzocbYfbvKF1egsE70y3X+XIw7whJHtSzmaEl7cX1/gtgefy35dyGvZsoq Y9KgqG0gpUs/ehucHC9NuYBxy2ah/RmqDI+egFodU6AYTuUChRGIvdz7bJaoCzUfxj vw+IqYrN53bWJ9eU33rxGl4hw6I6jPmntz4jf/V4Gc0Hj7ki24+PNbOkw+r4RdsrWC uY+qo0MwIC0gffNeZ6aRRpIJJj5vBMANY5Cwqdh+cREJpAhHd60ZogNhz167vrGxC6 Ryew3pDPnNQYA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45EFBFD0040; Sun, 1 Mar 2026 00:51:23 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Sun, 01 Mar 2026 01:51:21 +0100 Subject: [PATCH WIP v4 2/9] media: qcom: camss: csiphy-3ph: Use odd bits for configuring C-PHY lanes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260301-qcom-cphy-v4-2-e53316d2cc65@ixit.cz> References: <20260301-qcom-cphy-v4-0-e53316d2cc65@ixit.cz> In-Reply-To: <20260301-qcom-cphy-v4-0-e53316d2cc65@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , Casey Connolly , "Dr. Git" Cc: Konrad Dybcio , Joel Selvaraj , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=6462; i=david@ixit.cz; h=from:subject:message-id; bh=rTZ6J47ECLprwfYBbP1bL6C5zsfu9IOrZXbtNtbAtRE=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBpo42Ia0lUzfipazsv1Oav0fS036ikiRXyb0U8Y a45SqFWpZqJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaaONiAAKCRBgAj/E00kg cnKyD/kBcPvEkQr9EKloaXvPwIsl0uMcHp6YzzE1Ck34Q0csuq02ujan3aNTR8YbK7ArMz2wE2k 80IBOAHRwejUoGfEiYxDRMhR+Wmxs3t96mDYkxcD1CSr0cKA4SZPdceK5Ik0fXqhGHdWmsFjvtM 04Fq5A5+Oam7oV7lgmejAwf6MhStkZ2leBAWdFa81BBlIulej/cBNwqCoPf+T64QSrkF237rXJx yj1Fi1j6qcaThqd/6uj5W0WNdFemRueiHPUkRs3Iaf+H6nBQIlSJB02CjIXkCjIMnhw5ekt57lN 1TRnCa+Vl84ZMfzHysDdDnTL6nSmG2IiYwbdQ025LmjW48PYty9XNBcDAOHudB9MausQ6QiuJ6K i5WUstgD/Zrgx/kR2lh8PYu8VsyKELuaBcvTditWk50JqTXZ7oZVhS/KYxMvUJ9LQnLw00hBeGn EwVnH+U321xcHj1ZtY2M1dY5IOYlamruykDRkJIuruptTACYeQTyk6gLVyN3wcqycTOWkpCU/IN sXhX+aKKP3B/+N5Z22A1szFhcJZNuek0nkECTuB/TjBEXV1lRwPCN2MnvpLCTbTOIuSkEWiTCfX l4HAEOqOIRhX29PkL5F9j1zZcuftrd6YV4ATfrbn14lVyXAowSJ6qKaY52RO33lh+FY5KGrLoXx xmRrXZRfIzK74Ug== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg So far, only D-PHY mode was supported, which uses even bits when enabling or masking lanes. For C-PHY configuration, the hardware instead requires using the odd bits. Since there can be unrecognized configuration allow returning failure. Signed-off-by: David Heidelberg Reviewed-by: Bryan O'Donoghue --- .../platform/qcom/camss/camss-csiphy-2ph-1-0.c | 8 ++-- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 49 +++++++++++++++++-= ---- drivers/media/platform/qcom/camss/camss-csiphy.c | 5 +-- drivers/media/platform/qcom/camss/camss-csiphy.h | 6 +-- 4 files changed, 48 insertions(+), 20 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c index 9d67e7fa6366a..bb4b91f69616b 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c @@ -94,9 +94,9 @@ static u8 csiphy_settle_cnt_calc(s64 link_freq, u32 timer= _clk_rate) return settle_cnt; } =20 -static void csiphy_lanes_enable(struct csiphy_device *csiphy, - struct csiphy_config *cfg, - s64 link_freq, u8 lane_mask) +static int csiphy_lanes_enable(struct csiphy_device *csiphy, + struct csiphy_config *cfg, + s64 link_freq, u8 lane_mask) { struct csiphy_lanes_cfg *c =3D &cfg->csi2->lane_cfg; u8 settle_cnt; @@ -132,6 +132,8 @@ static void csiphy_lanes_enable(struct csiphy_device *c= siphy, writel_relaxed(0x3f, csiphy->base + CAMSS_CSI_PHY_INTERRUPT_CLEARn(l)); } + + return 0; } =20 static void csiphy_lanes_disable(struct csiphy_device *csiphy, diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index 4154832745525..cf83c9e062b81 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -14,6 +14,7 @@ #include #include #include +#include =20 #define CSIPHY_3PH_LNn_CFG1(n) (0x000 + 0x100 * (n)) #define CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG (BIT(7) | BIT(6)) @@ -993,13 +994,22 @@ static void csiphy_gen2_config_lanes(struct csiphy_de= vice *csiphy, =20 static u8 csiphy_get_lane_mask(struct csiphy_lanes_cfg *lane_cfg) { - u8 lane_mask; - int i; + u8 lane_mask =3D 0; =20 - lane_mask =3D CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; + switch (lane_cfg->phy_cfg) { + case V4L2_MBUS_CSI2_CPHY: + for (int i =3D 0; i < lane_cfg->num_data; i++) + lane_mask |=3D BIT(lane_cfg->data[i].pos + 1); + break; + case V4L2_MBUS_CSI2_DPHY: + lane_mask =3D CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; =20 - for (i =3D 0; i < lane_cfg->num_data; i++) - lane_mask |=3D 1 << lane_cfg->data[i].pos; + for (int i =3D 0; i < lane_cfg->num_data; i++) + lane_mask |=3D BIT(lane_cfg->data[i].pos); + break; + default: + break; + } =20 return lane_mask; } @@ -1027,10 +1037,11 @@ static bool csiphy_is_gen2(u32 version) return ret; } =20 -static void csiphy_lanes_enable(struct csiphy_device *csiphy, - struct csiphy_config *cfg, - s64 link_freq, u8 lane_mask) +static int csiphy_lanes_enable(struct csiphy_device *csiphy, + struct csiphy_config *cfg, + s64 link_freq, u8 lane_mask) { + struct device *dev =3D csiphy->camss->dev; struct csiphy_lanes_cfg *c =3D &cfg->csi2->lane_cfg; struct csiphy_device_regs *regs =3D csiphy->regs; u8 settle_cnt; @@ -1039,9 +1050,23 @@ static void csiphy_lanes_enable(struct csiphy_device= *csiphy, =20 settle_cnt =3D csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate); =20 - val =3D CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; - for (i =3D 0; i < c->num_data; i++) - val |=3D BIT(c->data[i].pos * 2); + val =3D 0; + + switch (c->phy_cfg) { + case V4L2_MBUS_CSI2_CPHY: + for (i =3D 0; i < c->num_data; i++) + val |=3D BIT((c->data[i].pos * 2) + 1); + break; + case V4L2_MBUS_CSI2_DPHY: + val =3D CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; + + for (i =3D 0; i < c->num_data; i++) + val |=3D BIT(c->data[i].pos * 2); + break; + default: + dev_err(dev, "Unsupported bus type %d\n", c->phy_cfg); + return -EINVAL; + } =20 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 5)); @@ -1068,6 +1093,8 @@ static void csiphy_lanes_enable(struct csiphy_device = *csiphy, writel_relaxed(0, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, i)); } + + return 0; } =20 static void csiphy_lanes_disable(struct csiphy_device *csiphy, diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/med= ia/platform/qcom/camss/camss-csiphy.c index 62623393f4144..938600f3defe1 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c @@ -265,6 +265,7 @@ static int csiphy_set_power(struct v4l2_subdev *sd, int= on) static int csiphy_stream_on(struct csiphy_device *csiphy) { struct csiphy_config *cfg =3D &csiphy->cfg; + const struct csiphy_hw_ops *ops =3D csiphy->res->hw_ops; s64 link_freq; u8 lane_mask =3D csiphy->res->hw_ops->get_lane_mask(&cfg->csi2->lane_cfg); u8 bpp =3D csiphy_get_bpp(csiphy->res->formats->formats, csiphy->res->for= mats->nformats, @@ -295,9 +296,7 @@ static int csiphy_stream_on(struct csiphy_device *csiph= y) wmb(); } =20 - csiphy->res->hw_ops->lanes_enable(csiphy, cfg, link_freq, lane_mask); - - return 0; + return ops->lanes_enable(csiphy, cfg, link_freq, lane_mask); } =20 /* diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/med= ia/platform/qcom/camss/camss-csiphy.h index d198171700e73..21cf2ce931c1d 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.h +++ b/drivers/media/platform/qcom/camss/camss-csiphy.h @@ -73,9 +73,9 @@ struct csiphy_hw_ops { void (*hw_version_read)(struct csiphy_device *csiphy, struct device *dev); void (*reset)(struct csiphy_device *csiphy); - void (*lanes_enable)(struct csiphy_device *csiphy, - struct csiphy_config *cfg, - s64 link_freq, u8 lane_mask); + int (*lanes_enable)(struct csiphy_device *csiphy, + struct csiphy_config *cfg, + s64 link_freq, u8 lane_mask); void (*lanes_disable)(struct csiphy_device *csiphy, struct csiphy_config *cfg); irqreturn_t (*isr)(int irq, void *dev); --=20 2.51.0