From nobody Tue Apr 7 18:51:21 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0ED0421772A; Fri, 27 Feb 2026 12:37:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772195821; cv=none; b=VOG6h75MwKYY3u/+cLEkOvxYeML5tb0DJ9nwPcUx685Upn7v/lon1924yshW2wrR2AETUebdpIQQcZ8yizjjpXB0SY0cbgB9/M9aRl6yuicP81JJVKGJspNQolDpIIEmb9yrE2Hs9wNNzGWa2nvzjM4V3dcrC+J3s9SEwFtyu1U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772195821; c=relaxed/simple; bh=dsee9eRlHaKPY3/htEY7eYUTcjs6v6upQYrzS0dDUus=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=VVOQ56pKxflEQxoHZbRqHhFwX893zsapKg7g5ku1SV99YBMJ5uexdgWVL28imuuRP6Lq8MGFSdB1NT//4uoruS4zVRIrl/XFhCWZPC+D4BSIL3lR95rnpkGzUwwqUH1stA5qZ4YRpJDp+X+BxvCx3v7hb+6QAOpImeMW8tYXUNs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WGETGO3J; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WGETGO3J" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 83EA7C116C6; Fri, 27 Feb 2026 12:37:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772195820; bh=dsee9eRlHaKPY3/htEY7eYUTcjs6v6upQYrzS0dDUus=; h=From:To:Cc:Subject:Date:From; b=WGETGO3JBTefW1vOvnYv3JF00EwegeaUPWNDmob4fWwcFSDNAfhxVGEydPYrZh2yW WWrCdZco5wY/d8fVQnf0eO21CXZPwm7l25FBxG3LfAQNBBHe5jX3MWB+XqZGNMOseH xClpJrMMUdjHK3Uk9Yj5yF3upd4nUHZCR20LEZWsIHcvC1AbSZDbNHTlfggFRUJBdx jMADBpStQytFhRd8qwINWIbuVfgYHWWL9i7SVnNQ0G2jyZ2Komg0P/lP76FHGO6oj/ WWQBTPuEUfNPhTggHUaQY5qTc+hR5rdQCS9DZ/8BlK/kX1dN1ZhFwv4lcuknKvS3M9 DpQasjwlrFFgQ== From: Bjorn Helgaas To: linux-pci@vger.kernel.org, David Woodhouse , Alex Williamson Cc: Baruch Siach , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Bjorn Helgaas Subject: [PATCH] PCI: Correct PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 value Date: Fri, 27 Feb 2026 06:36:53 -0600 Message-ID: <20260227123653.3891008-1-bhelgaas@google.com> X-Mailer: git-send-email 2.51.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" fb82437fdd8c ("PCI: Change capability register offsets to hex") incorrectly converted the PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 value from decimal 52 to hex 0x32: -#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link= end here */ +#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 0x32 /* end of v2 EPs w/ link = */ Change PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 to the correct value of 0x34. fb82437fdd8c was from Baruch Siach , but this was not Baruch's fault; it's a mistake I made when applying the patch. Fixes: fb82437fdd8c ("PCI: Change capability register offsets to hex") Reported-by: David Woodhouse Closes: https://lore.kernel.org/all/3ae392a0158e9d9ab09a1d42150429dd8ca4279= 1.camel@infradead.org Signed-off-by: Bjorn Helgaas Reviewed-by: Krzysztof Wilczy=C5=84ski --- include/uapi/linux/pci_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index ec1c54b5a310..14f634ab9350 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -712,7 +712,7 @@ #define PCI_EXP_LNKCTL2_HASD 0x0020 /* HW Autonomous Speed Disable */ #define PCI_EXP_LNKSTA2 0x32 /* Link Status 2 */ #define PCI_EXP_LNKSTA2_FLIT 0x0400 /* Flit Mode Status */ -#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 0x32 /* end of v2 EPs w/ link */ +#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 0x34 /* end of v2 EPs w/ link */ #define PCI_EXP_SLTCAP2 0x34 /* Slot Capabilities 2 */ #define PCI_EXP_SLTCAP2_IBPD 0x00000001 /* In-band PD Disable Supported */ #define PCI_EXP_SLTCTL2 0x38 /* Slot Control 2 */ --=20 2.51.0