From nobody Thu Apr 9 12:06:46 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5191430596F; Fri, 27 Feb 2026 07:31:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772177509; cv=none; b=MiFdWoXMeXO26YmUjD7nj7mhK/A2QnudkPSewUYxBB3jOujJBo3LN+7A3KSK0cW80ajXjipg4HYQ57VMUsxw1r8hHeRIALrfKFM3ILAzFOYp85egwjLlVFbUI9JZyDUBF4y59/W3/XsNcYahkDlLX3It9i1ZWdYFERjI6BAs6Hg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772177509; c=relaxed/simple; bh=8+V5iNchIOiwDg9bEpu4sW6lSMdgs6cI02ZreEZunDc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qQ8JDx2sfvZQcmRaepJtzWDgWuasKb4kqohcIiG47+PE/LvtNtRGC6Hr2ZSGI5gjqRfuKPjmH3AZGdVg0sVssPZWKgPIFnvsFottoY4amFspLN9fFQ3UOGlOsDio6C8RJF2RFMydw0Kd14grO8AS/HTAdS65cSujqw7JJTaPbSg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Nkx7+v2y; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Nkx7+v2y" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1772177508; x=1803713508; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8+V5iNchIOiwDg9bEpu4sW6lSMdgs6cI02ZreEZunDc=; b=Nkx7+v2yLfa2Q9xjlChnMGJtLA3I1tHuIJYwIdvgvc+KW+yayJRY7cqs pqh1jjycy4Svlw+wOFvmhGEDcBrp5ZOzj59fYSxfiN1Zrj835ivE+FgkR 3zA1UFCMoxaIIOXB5VEPMLZRvkhIXC5lTVczvZfmWkztSphLfywg0+UAV 8cW1Wpb/KK9LGB9FWjh2fs0Y9f69oMKx4Fs9BH4EcQOOUicAxeJQOyIRg PU3MeJJ+432AcnGoH1/S4LHModVLzv3fURKNT5ARqCExQp+Uqcme2xn7x 9K45ZQV72QQBb+7C50xPpfwV5WluJPMxioGIkCHZx5pFuhwpdraq92ypQ Q==; X-CSE-ConnectionGUID: /AVa6bwHSqe24h8Jh3J90Q== X-CSE-MsgGUID: rzaaIrPIRAWfh/6g1hOVTQ== X-IronPort-AV: E=Sophos;i="6.21,313,1763449200"; d="scan'208";a="54383808" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Feb 2026 00:31:47 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.87.71) by chn-vm-ex1.mchp-main.com (10.10.87.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.35; Fri, 27 Feb 2026 00:31:25 -0700 Received: from che-ll-i71840.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 27 Feb 2026 00:31:21 -0700 From: Balakrishnan Sambath To: , CC: , , , , , , Andrei Simion , Balakrishnan Sambath Subject: [PATCH 1/3] watchdog: at91sam9_wdt.h: Cleanup the header file Date: Fri, 27 Feb 2026 13:01:14 +0530 Message-ID: <20260227073116.30447-2-balakrishnan.s@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260227073116.30447-1-balakrishnan.s@microchip.com> References: <20260227073116.30447-1-balakrishnan.s@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Andrei Simion This patch reorganizes the header file by renaming the registers using a general pattern also this patch simplifies the watchdog disable logic in the at91sam9_wdt.h header by differentiating between modern (SAM9X60, SAMA7G5, SAM9X7) and legacy (SAMA5, AT91SAM9261) chips based on the watchdog disable bit. For modern chips, the disable bit is at bit 12, while for legacy chips it is at bit 15. Signed-off-by: Andrei Simion [Remove Kconfig-based WDDIS selection and define explicit legacy and modern masks] Signed-off-by: Balakrishnan Sambath --- drivers/watchdog/at91sam9_wdt.h | 65 ++++++++++++++++----------------- 1 file changed, 32 insertions(+), 33 deletions(-) diff --git a/drivers/watchdog/at91sam9_wdt.h b/drivers/watchdog/at91sam9_wd= t.h index 298d545df1a1..1e0aeecb489f 100644 --- a/drivers/watchdog/at91sam9_wdt.h +++ b/drivers/watchdog/at91sam9_wdt.h @@ -3,59 +3,58 @@ * drivers/watchdog/at91sam9_wdt.h * * Copyright (C) 2007 Andrew Victor * Copyright (C) 2007 Atmel Corporation. * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries * * Watchdog Timer (WDT) - System peripherals regsters. * Based on AT91SAM9261 datasheet revision D. * Based on SAM9X60 datasheet. + * Based on SAMA7G5 datasheet. + * Based on SAM9X75 datasheet. * */ =20 #ifndef AT91_WDT_H #define AT91_WDT_H =20 #include =20 -#define AT91_WDT_CR 0x00 /* Watchdog Control Register */ -#define AT91_WDT_WDRSTT BIT(0) /* Restart */ -#define AT91_WDT_KEY (0xa5UL << 24) /* KEY Password */ - -#define AT91_WDT_MR 0x04 /* Watchdog Mode Register */ -#define AT91_WDT_WDV (0xfffUL << 0) /* Counter Value */ -#define AT91_WDT_SET_WDV(x) ((x) & AT91_WDT_WDV) -#define AT91_SAM9X60_PERIODRST BIT(4) /* Period Reset */ -#define AT91_SAM9X60_RPTHRST BIT(5) /* Minimum Restart Period */ +#define AT91_WDT_CR 0x00 /* Watchdog Control Register */ +#define AT91_WDT_WDRSTT BIT(0) /* Restart */ +#define AT91_WDT_KEY (0xa5UL << 24) /* KEY Password */ +#define AT91_WDT_MR 0x04 /* Watchdog Mode Register */ +#define AT91_WDT_WDV (0xfffUL << 0) /* Counter Value */ #define AT91_WDT_WDFIEN BIT(12) /* Fault Interrupt Enable */ -#define AT91_SAM9X60_WDDIS BIT(12) /* Watchdog Disable */ -#define AT91_WDT_WDRSTEN BIT(13) /* Reset Processor */ -#define AT91_WDT_WDRPROC BIT(14) /* Timer Restart */ -#define AT91_WDT_WDDIS BIT(15) /* Watchdog Disable */ -#define AT91_WDT_WDD (0xfffUL << 16) /* Delta Value */ -#define AT91_WDT_SET_WDD(x) (((x) << 16) & AT91_WDT_WDD) -#define AT91_WDT_WDDBGHLT BIT(28) /* Debug Halt */ -#define AT91_WDT_WDIDLEHLT BIT(29) /* Idle Halt */ - +#define AT91_WDT_WDRSTEN BIT(13) +#define AT91_WDT_WDRPROC BIT(14) +#define AT91_WDT_WDD (0xfffUL << 16) +#define AT91_WDT_WDDBGHLT BIT(28) +#define AT91_WDT_WDIDLEHLT BIT(29) #define AT91_WDT_SR 0x08 /* Watchdog Status Register */ #define AT91_WDT_WDUNF BIT(0) /* Watchdog Underflow */ #define AT91_WDT_WDERR BIT(1) /* Watchdog Error */ =20 -/* Watchdog Timer Value Register */ -#define AT91_SAM9X60_VR 0x08 +#define AT91_WDT_SET_WDV(x) ((x) & AT91_WDT_WDV) +#define AT91_WDT_SET_WDD(x) (((x) << 16) & AT91_WDT_WDD) =20 -/* Watchdog Window Level Register */ -#define AT91_SAM9X60_WLR 0x0c -/* Watchdog Period Value */ -#define AT91_SAM9X60_COUNTER (0xfffUL << 0) -#define AT91_SAM9X60_SET_COUNTER(x) ((x) & AT91_SAM9X60_COUNTER) +#define AT91_WDT_VR 0x08 /* Watchdog Timer Value Register */ +#define AT91_WDT_ISR 0x1c /* Interrupt Status Register */ +#define AT91_WDT_IER 0x14 /* Interrupt Enable Register */ +#define AT91_WDT_IDR 0x18 /* Interrupt Disable Register */ +#define AT91_WDT_WLR 0x0c /* Watchdog Window Level Register */ +#define AT91_WDT_PERIODRST BIT(4) /* Period Reset */ +#define AT91_WDT_RPTHRST BIT(5) /* Minimum Restart Period */ +#define AT91_WDT_PERINT BIT(0) /* Period Interrupt Enable */ +#define AT91_WDT_COUNTER (0xfffUL << 0) /* Watchdog Period Value */ +#define AT91_WDT_SET_COUNTER(x) ((x) & AT91_WDT_COUNTER) =20 -/* Interrupt Enable Register */ -#define AT91_SAM9X60_IER 0x14 -/* Period Interrupt Enable */ -#define AT91_SAM9X60_PERINT BIT(0) -/* Interrupt Disable Register */ -#define AT91_SAM9X60_IDR 0x18 -/* Interrupt Status Register */ -#define AT91_SAM9X60_ISR 0x1c +/* + * WDDIS bit differs by SoC: + * - SAMA5, AT91SAM9261: bit 15 + * - SAM9X60, SAMA7G5, SAM9X75: bit 12 + * Select at runtime via compatible string. + */ +#define AT91_WDT_WDDIS_LEGACY BIT(15) +#define AT91_WDT_WDDIS_MODERN BIT(12) =20 #endif --=20 2.34.1 From nobody Thu Apr 9 12:06:46 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62F58345CB2; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Andrei Simion This patch cleans up and refactors the Atmel SAMA5D4 Watchdog Driver to be more readable and to fixup Reset issue introduced by commit 266da53c35fc ("watchdog: sama5d4: readout initial state"). Signed-off-by: Andrei Simion [Use per-device WDDIS mask and sync MR shadow WDDIS state] Signed-off-by: Balakrishnan Sambath --- drivers/watchdog/sama5d4_wdt.c | 156 ++++++++++++++++----------------- 1 file changed, 77 insertions(+), 79 deletions(-) diff --git a/drivers/watchdog/sama5d4_wdt.c b/drivers/watchdog/sama5d4_wdt.c index 13e72918338a..b422d0bd75f9 100644 --- a/drivers/watchdog/sama5d4_wdt.c +++ b/drivers/watchdog/sama5d4_wdt.c @@ -24,44 +24,58 @@ #define WDT_DEFAULT_TIMEOUT MAX_WDT_TIMEOUT =20 #define WDT_SEC2TICKS(s) ((s) ? (((s) << 8) - 1) : 0) =20 struct sama5d4_wdt { struct watchdog_device wdd; void __iomem *reg_base; u32 mr; u32 ir; + u32 wddis_mask; unsigned long last_ping; bool need_irq; - bool sam9x60_support; + bool is_modern_chip; }; =20 +static inline bool wdt_enabled(struct sama5d4_wdt *wdt, u32 mr) +{ + return !(mr & wdt->wddis_mask); +} + static int wdt_timeout; static bool nowayout =3D WATCHDOG_NOWAYOUT; =20 module_param(wdt_timeout, int, 0); MODULE_PARM_DESC(wdt_timeout, "Watchdog timeout in seconds. (default =3D " __MODULE_STRING(WDT_DEFAULT_TIMEOUT) ")"); =20 module_param(nowayout, bool, 0); MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=3D" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); =20 -#define wdt_enabled (!(wdt->mr & AT91_WDT_WDDIS)) =20 #define wdt_read(wdt, field) \ readl_relaxed((wdt)->reg_base + (field)) =20 /* 4 slow clock periods is 4/32768 =3D 122.07=C2=B5s*/ #define WDT_DELAY usecs_to_jiffies(123) =20 +static bool check_is_modern_chip_by_compatible(struct device *dev) +{ + if (of_device_is_compatible(dev->of_node, "microchip,sam9x60-wdt") || + of_device_is_compatible(dev->of_node, "microchip,sama7g5-wdt")) + return true; + + return false; +} + static void wdt_write(struct sama5d4_wdt *wdt, u32 field, u32 val) { /* * WDT_CR and WDT_MR must not be modified within three slow clock * periods following a restart of the watchdog performed by a write * access in WDT_CR. */ while (time_before(jiffies, wdt->last_ping + WDT_DELAY)) usleep_range(30, 125); @@ -71,322 +85,306 @@ static void wdt_write(struct sama5d4_wdt *wdt, u32 fi= eld, u32 val) =20 static void wdt_write_nosleep(struct sama5d4_wdt *wdt, u32 field, u32 val) { if (time_before(jiffies, wdt->last_ping + WDT_DELAY)) udelay(123); writel_relaxed(val, wdt->reg_base + field); wdt->last_ping =3D jiffies; } =20 -static int sama5d4_wdt_start(struct watchdog_device *wdd) +static int wdt_start(struct watchdog_device *wdd) { struct sama5d4_wdt *wdt =3D watchdog_get_drvdata(wdd); =20 - if (wdt->sam9x60_support) { - writel_relaxed(wdt->ir, wdt->reg_base + AT91_SAM9X60_IER); - wdt->mr &=3D ~AT91_SAM9X60_WDDIS; - } else { - wdt->mr &=3D ~AT91_WDT_WDDIS; - } + if (wdt->is_modern_chip) + writel_relaxed(wdt->ir, wdt->reg_base + AT91_WDT_IER); + wdt->mr &=3D ~wdt->wddis_mask; wdt_write(wdt, AT91_WDT_MR, wdt->mr); =20 return 0; } =20 -static int sama5d4_wdt_stop(struct watchdog_device *wdd) +static int wdt_stop(struct watchdog_device *wdd) { struct sama5d4_wdt *wdt =3D watchdog_get_drvdata(wdd); =20 - if (wdt->sam9x60_support) { - writel_relaxed(wdt->ir, wdt->reg_base + AT91_SAM9X60_IDR); - wdt->mr |=3D AT91_SAM9X60_WDDIS; - } else { - wdt->mr |=3D AT91_WDT_WDDIS; - } + if (wdt->is_modern_chip) + writel_relaxed(wdt->ir, wdt->reg_base + AT91_WDT_IDR); + wdt->mr |=3D wdt->wddis_mask; wdt_write(wdt, AT91_WDT_MR, wdt->mr); =20 return 0; } =20 -static int sama5d4_wdt_ping(struct watchdog_device *wdd) +static int wdt_ping(struct watchdog_device *wdd) { struct sama5d4_wdt *wdt =3D watchdog_get_drvdata(wdd); =20 wdt_write(wdt, AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT); =20 return 0; } =20 -static int sama5d4_wdt_set_timeout(struct watchdog_device *wdd, - unsigned int timeout) +static int wdt_set_timeout(struct watchdog_device *wdd, + unsigned int timeout) { struct sama5d4_wdt *wdt =3D watchdog_get_drvdata(wdd); u32 value =3D WDT_SEC2TICKS(timeout); =20 - if (wdt->sam9x60_support) { - wdt_write(wdt, AT91_SAM9X60_WLR, - AT91_SAM9X60_SET_COUNTER(value)); + if (wdt->is_modern_chip) { + wdt_write(wdt, AT91_WDT_WLR, + AT91_WDT_SET_COUNTER(value)); =20 wdd->timeout =3D timeout; return 0; } =20 wdt->mr &=3D ~AT91_WDT_WDV; wdt->mr |=3D AT91_WDT_SET_WDV(value); =20 /* * WDDIS has to be 0 when updating WDD/WDV. The datasheet states: When * setting the WDDIS bit, and while it is set, the fields WDV and WDD * must not be modified. * If the watchdog is enabled, then the timeout can be updated. Else, * wait that the user enables it. */ - if (wdt_enabled) - wdt_write(wdt, AT91_WDT_MR, wdt->mr & ~AT91_WDT_WDDIS); + if (wdt_enabled(wdt, wdt->mr)) + wdt_write(wdt, AT91_WDT_MR, wdt->mr & ~wdt->wddis_mask); =20 wdd->timeout =3D timeout; =20 return 0; } =20 static const struct watchdog_info sama5d4_wdt_info =3D { .options =3D WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, .identity =3D "Atmel SAMA5D4 Watchdog", }; =20 static const struct watchdog_ops sama5d4_wdt_ops =3D { .owner =3D THIS_MODULE, - .start =3D sama5d4_wdt_start, - .stop =3D sama5d4_wdt_stop, - .ping =3D sama5d4_wdt_ping, - .set_timeout =3D sama5d4_wdt_set_timeout, + .start =3D wdt_start, + .stop =3D wdt_stop, + .ping =3D wdt_ping, + .set_timeout =3D wdt_set_timeout, }; =20 -static irqreturn_t sama5d4_wdt_irq_handler(int irq, void *dev_id) +static irqreturn_t wdt_irq_handler(int irq, void *dev_id) { struct sama5d4_wdt *wdt =3D platform_get_drvdata(dev_id); u32 reg; =20 - if (wdt->sam9x60_support) - reg =3D wdt_read(wdt, AT91_SAM9X60_ISR); + if (wdt->is_modern_chip) + reg =3D wdt_read(wdt, AT91_WDT_ISR); else reg =3D wdt_read(wdt, AT91_WDT_SR); =20 if (reg) { pr_crit("Atmel Watchdog Software Reset\n"); emergency_restart(); pr_crit("Reboot didn't succeed\n"); } =20 return IRQ_HANDLED; } =20 -static int of_sama5d4_wdt_init(struct device_node *np, struct sama5d4_wdt = *wdt) +static int of_wdt_init(struct device_node *np, struct sama5d4_wdt *wdt) { const char *tmp; =20 - if (wdt->sam9x60_support) - wdt->mr =3D AT91_SAM9X60_WDDIS; - else - wdt->mr =3D AT91_WDT_WDDIS; + wdt->mr =3D wdt->wddis_mask; =20 if (!of_property_read_string(np, "atmel,watchdog-type", &tmp) && !strcmp(tmp, "software")) wdt->need_irq =3D true; =20 if (of_property_read_bool(np, "atmel,idle-halt")) wdt->mr |=3D AT91_WDT_WDIDLEHLT; =20 if (of_property_read_bool(np, "atmel,dbg-halt")) wdt->mr |=3D AT91_WDT_WDDBGHLT; =20 return 0; } =20 -static int sama5d4_wdt_init(struct sama5d4_wdt *wdt) +static int wdt_init(struct sama5d4_wdt *wdt) { + struct watchdog_device *wdd =3D &wdt->wdd; u32 reg, val; =20 val =3D WDT_SEC2TICKS(WDT_DEFAULT_TIMEOUT); + /* * When booting and resuming, the bootloader may have changed the * watchdog configuration. - * If the watchdog is already running, we can safely update it. - * Else, we have to disable it properly. + * If the watchdog is not running, we need to disable it properly. + * Otherwise, we can safely update it. */ - if (!wdt_enabled) { - reg =3D wdt_read(wdt, AT91_WDT_MR); - if (wdt->sam9x60_support && (!(reg & AT91_SAM9X60_WDDIS))) - wdt_write_nosleep(wdt, AT91_WDT_MR, - reg | AT91_SAM9X60_WDDIS); - else if (!wdt->sam9x60_support && - (!(reg & AT91_WDT_WDDIS))) - wdt_write_nosleep(wdt, AT91_WDT_MR, - reg | AT91_WDT_WDDIS); + reg =3D wdt_read(wdt, AT91_WDT_MR); + if (wdt_enabled(wdt, reg)) { + wdt->mr &=3D ~wdt->wddis_mask; + set_bit(WDOG_HW_RUNNING, &wdd->status); + } else { + wdt->mr |=3D wdt->wddis_mask; } =20 - if (wdt->sam9x60_support) { + if (wdt->is_modern_chip) { if (wdt->need_irq) - wdt->ir =3D AT91_SAM9X60_PERINT; + wdt->ir =3D AT91_WDT_PERINT; else - wdt->mr |=3D AT91_SAM9X60_PERIODRST; + wdt->mr |=3D AT91_WDT_PERIODRST; =20 - wdt_write(wdt, AT91_SAM9X60_IER, wdt->ir); - wdt_write(wdt, AT91_SAM9X60_WLR, AT91_SAM9X60_SET_COUNTER(val)); + wdt_write(wdt, AT91_WDT_IER, wdt->ir); + wdt_write(wdt, AT91_WDT_WLR, AT91_WDT_SET_COUNTER(val)); } else { wdt->mr |=3D AT91_WDT_SET_WDD(WDT_SEC2TICKS(MAX_WDT_TIMEOUT)); wdt->mr |=3D AT91_WDT_SET_WDV(val); =20 if (wdt->need_irq) wdt->mr |=3D AT91_WDT_WDFIEN; else wdt->mr |=3D AT91_WDT_WDRSTEN; } =20 wdt_write_nosleep(wdt, AT91_WDT_MR, wdt->mr); =20 return 0; } =20 -static int sama5d4_wdt_probe(struct platform_device *pdev) +static int wdt_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; struct watchdog_device *wdd; struct sama5d4_wdt *wdt; void __iomem *regs; u32 irq =3D 0; - u32 reg; int ret; =20 wdt =3D devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); if (!wdt) return -ENOMEM; =20 wdd =3D &wdt->wdd; wdd->timeout =3D WDT_DEFAULT_TIMEOUT; wdd->info =3D &sama5d4_wdt_info; wdd->ops =3D &sama5d4_wdt_ops; wdd->min_timeout =3D MIN_WDT_TIMEOUT; wdd->max_timeout =3D MAX_WDT_TIMEOUT; wdt->last_ping =3D jiffies; - - if (of_device_is_compatible(dev->of_node, "microchip,sam9x60-wdt") || - of_device_is_compatible(dev->of_node, "microchip,sama7g5-wdt")) - wdt->sam9x60_support =3D true; + wdt->is_modern_chip =3D check_is_modern_chip_by_compatible(dev); + if (wdt->is_modern_chip) + wdt->wddis_mask =3D AT91_WDT_WDDIS_MODERN; + else + wdt->wddis_mask =3D AT91_WDT_WDDIS_LEGACY; =20 watchdog_set_drvdata(wdd, wdt); =20 regs =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(regs)) return PTR_ERR(regs); =20 wdt->reg_base =3D regs; =20 - ret =3D of_sama5d4_wdt_init(dev->of_node, wdt); + ret =3D of_wdt_init(dev->of_node, wdt); if (ret) return ret; =20 if (wdt->need_irq) { irq =3D irq_of_parse_and_map(dev->of_node, 0); if (!irq) { dev_warn(dev, "failed to get IRQ from DT\n"); wdt->need_irq =3D false; } } =20 if (wdt->need_irq) { - ret =3D devm_request_irq(dev, irq, sama5d4_wdt_irq_handler, + ret =3D devm_request_irq(dev, irq, wdt_irq_handler, IRQF_SHARED | IRQF_IRQPOLL | IRQF_NO_SUSPEND, pdev->name, pdev); if (ret) { dev_err(dev, "cannot register interrupt handler\n"); return ret; } } =20 watchdog_init_timeout(wdd, wdt_timeout, dev); =20 - reg =3D wdt_read(wdt, AT91_WDT_MR); - if (!(reg & AT91_WDT_WDDIS)) { - wdt->mr &=3D ~AT91_WDT_WDDIS; - set_bit(WDOG_HW_RUNNING, &wdd->status); - } - - ret =3D sama5d4_wdt_init(wdt); + ret =3D wdt_init(wdt); if (ret) return ret; =20 watchdog_set_nowayout(wdd, nowayout); =20 watchdog_stop_on_unregister(wdd); ret =3D devm_watchdog_register_device(dev, wdd); if (ret) return ret; =20 platform_set_drvdata(pdev, wdt); =20 dev_info(dev, "initialized (timeout =3D %d sec, nowayout =3D %d)\n", wdd->timeout, nowayout); =20 return 0; } =20 -static const struct of_device_id sama5d4_wdt_of_match[] =3D { +static const struct of_device_id wdt_of_match[] =3D { { .compatible =3D "atmel,sama5d4-wdt", }, { .compatible =3D "microchip,sam9x60-wdt", }, { .compatible =3D "microchip,sama7g5-wdt", }, =20 { } }; -MODULE_DEVICE_TABLE(of, sama5d4_wdt_of_match); +MODULE_DEVICE_TABLE(of, wdt_of_match); =20 -static int sama5d4_wdt_suspend_late(struct device *dev) +static int wdt_suspend_late(struct device *dev) { struct sama5d4_wdt *wdt =3D dev_get_drvdata(dev); =20 if (watchdog_active(&wdt->wdd)) - sama5d4_wdt_stop(&wdt->wdd); + wdt_stop(&wdt->wdd); =20 return 0; } =20 -static int sama5d4_wdt_resume_early(struct device *dev) +static int wdt_resume_early(struct device *dev) { struct sama5d4_wdt *wdt =3D dev_get_drvdata(dev); =20 /* * FIXME: writing MR also pings the watchdog which may not be desired. * This should only be done when the registers are lost on suspend but * there is no way to get this information right now. */ - sama5d4_wdt_init(wdt); + wdt_init(wdt); =20 if (watchdog_active(&wdt->wdd)) - sama5d4_wdt_start(&wdt->wdd); + wdt_start(&wdt->wdd); =20 return 0; } =20 static const struct dev_pm_ops sama5d4_wdt_pm_ops =3D { - LATE_SYSTEM_SLEEP_PM_OPS(sama5d4_wdt_suspend_late, - sama5d4_wdt_resume_early) + LATE_SYSTEM_SLEEP_PM_OPS(wdt_suspend_late, + wdt_resume_early) }; =20 static struct platform_driver sama5d4_wdt_driver =3D { - .probe =3D sama5d4_wdt_probe, + .probe =3D wdt_probe, .driver =3D { .name =3D "sama5d4_wdt", .pm =3D pm_sleep_ptr(&sama5d4_wdt_pm_ops), - .of_match_table =3D sama5d4_wdt_of_match, + .of_match_table =3D wdt_of_match, } }; module_platform_driver(sama5d4_wdt_driver); =20 MODULE_AUTHOR("Atmel Corporation"); MODULE_DESCRIPTION("Atmel SAMA5D4 Watchdog Timer driver"); MODULE_LICENSE("GPL v2"); --=20 2.34.1 From nobody Thu Apr 9 12:06:46 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1FDD4224AF1; Fri, 27 Feb 2026 07:31:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772177517; cv=none; b=TzmI8HWaRcs88Ef1EUA1yEbP+9qc3g0kn8DiqSVA5QLNOWUoGaay4Be15/KrfufEMeRoqg6kAiNTTrS2zQ4eYYDIfKFCOkLYnZUFpjuRh9ihpqhK9z6mdBQtUoSHs320Bm0+XcxeeITDMLzmbmXZfCeSJM5vRMOCW1tcy7zBZEU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772177517; c=relaxed/simple; bh=Uw38JxW9SQFg5yvRQWMgdAVRw8MAPa94R0JCVi5ZRg4=; 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Fri, 27 Feb 2026 00:31:35 -0700 Received: from che-ll-i71840.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 27 Feb 2026 00:31:31 -0700 From: Balakrishnan Sambath To: , CC: , , , , , , Balakrishnan Sambath Subject: [PATCH 3/3] watchdog: at91sam9_wdt: Rename AT91_WDT_WDDIS to AT91_WDT_WDDIS_LEGACY Date: Fri, 27 Feb 2026 13:01:16 +0530 Message-ID: <20260227073116.30447-4-balakrishnan.s@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260227073116.30447-1-balakrishnan.s@microchip.com> References: <20260227073116.30447-1-balakrishnan.s@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace AT91_WDT_WDDIS with AT91_WDT_WDDIS_LEGACY to match the updated bit definition naming. Signed-off-by: Balakrishnan Sambath --- drivers/watchdog/at91sam9_wdt.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wd= t.c index aba66b8e9d03..88a4c1ec99bd 100644 --- a/drivers/watchdog/at91sam9_wdt.c +++ b/drivers/watchdog/at91sam9_wdt.c @@ -162,20 +162,20 @@ static int at91_wdt_init(struct platform_device *pdev= , struct at91wdt *wdt) =20 tmp =3D wdt_read(wdt, AT91_WDT_MR); if ((tmp & mask) !=3D (wdt->mr & mask)) { if (tmp =3D=3D WDT_MR_RESET) { wdt_write(wdt, AT91_WDT_MR, wdt->mr); tmp =3D wdt_read(wdt, AT91_WDT_MR); } } =20 - if (tmp & AT91_WDT_WDDIS) { - if (wdt->mr & AT91_WDT_WDDIS) + if (tmp & AT91_WDT_WDDIS_LEGACY) { + if (wdt->mr & AT91_WDT_WDDIS_LEGACY) return 0; dev_err(dev, "watchdog is disabled\n"); return -EINVAL; } =20 value =3D tmp & AT91_WDT_WDV; delta =3D (tmp & AT91_WDT_WDD) >> 16; =20 if (delta < value) @@ -297,20 +297,20 @@ static int of_at91wdt_init(struct device_node *np, st= ruct at91wdt *wdt) } else { wdt->mr |=3D AT91_WDT_WDRSTEN; } =20 if (!of_property_read_string(np, "atmel,reset-type", &tmp) && !strcmp(tmp, "proc")) wdt->mr |=3D AT91_WDT_WDRPROC; =20 if (of_property_read_bool(np, "atmel,disable")) { - wdt->mr |=3D AT91_WDT_WDDIS; - wdt->mr_mask &=3D AT91_WDT_WDDIS; + wdt->mr |=3D AT91_WDT_WDDIS_LEGACY; + wdt->mr_mask &=3D AT91_WDT_WDDIS_LEGACY; } =20 if (of_property_read_bool(np, "atmel,idle-halt")) wdt->mr |=3D AT91_WDT_WDIDLEHLT; =20 if (of_property_read_bool(np, "atmel,dbg-halt")) wdt->mr |=3D AT91_WDT_WDDBGHLT; =20 wdt->mr |=3D max | ((max - min) << 16); --=20 2.34.1