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a=ed25519-sha256; t=1772201499; l=9412; i=vikash.garodia@oss.qualcomm.com; s=20241104; h=from:subject:message-id; bh=dZJYP9WEQ15bASoAnqkMaYb7rJt/AK30AeIqIM/eNVY=; b=xABsSQZWHEFHXdnSjRmkICWSQY7FUatxKvuZR32t4ZpkcfBOUX7LP45A0GQ2X+1cJPPYWL7mD AGFLY8E0VgTDZasy1iltednXZg9uE4yd9nwYEgMuduYncfcYOLmsqbh X-Developer-Key: i=vikash.garodia@oss.qualcomm.com; a=ed25519; pk=LY9Eqp4KiHWxzGNKGHbwRFEJOfRCSzG/rxQNmvZvaKE= X-Authority-Analysis: v=2.4 cv=IZWKmGqa c=1 sm=1 tr=0 ts=69a1a631 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=gUug7MfHRhSEeGGeBFwA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: sQKXOav82M1R3sh3cLsJnYOi0ckFvBQw X-Proofpoint-ORIG-GUID: sQKXOav82M1R3sh3cLsJnYOi0ckFvBQw X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjI3MDEyNSBTYWx0ZWRfX7xA0uFdj3xSs +MPsLrVZyJA4+VE1N9YjM1fTtGqVMHgSzMN8mMN58uo6oieWnV9t17PQb+D5UYbY/6O9iah7HuU v5yVYAX1ePqInEro8XfxIo9YXgjCBHOsYKzh1a1U+3Y5PxyV4AJP8wBIgy3svhwaty1LZDoPphu LquXgb23dqbA8W7hkJ1S0XGfEys96RoabHLOki1WMbf2TeIxcj7FCDsli4/+mC5sNjMFgcsj4bm xB0lEGK6v1emcFPVVVRNyyTI7wSQ8dV44lTxsjLWunt7WmZKJL298/91mn1k/eQaSYSG+pvt6wH ZzA4QnxKB12LP+f28pJo96R3XZVIL/bgYOH3EPnDs5EGYW+2J4tQPynjl4RPAJLDnLo1S90Sl1S Exlgs9BCuOjY1e005GlsIJN4VULcKU8UJNN5HgXzvk8PtsdZh6zbO7Lp48lo0T1TeOs/FsoUNzy nx9f7NEZ6Gy7OBCRJXQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-27_02,2026-02-27_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 spamscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602270125 Currently the driver switches the vcodec GDSC to hardware (HW) mode before firmware load and boot sequence. GDSC can be powered off, keeping in hw mode, thereby the vcodec registers programmed in TrustZone (TZ) carry default (reset) values. Move the transition to HW mode after firmware load and boot sequence. The bug was exposed with driver configuring different stream ids to different devices via iommu-map. With registers carrying reset values, VPU would not generate desired stream-id, thereby leading to SMMU fault. For vpu4, when GDSC is switched to HW mode, there is a need to perform the reset operation. Without reset, there are occassional issues of register corruption observed. Hence the vpu GDSC switch also involves the reset. Fixes: dde659d37036 ("media: iris: Introduce vpu ops for vpu4 with necessar= y hooks") Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia --- drivers/media/platform/qcom/iris/iris_core.c | 4 ++++ drivers/media/platform/qcom/iris/iris_hfi_common.c | 4 ++++ drivers/media/platform/qcom/iris/iris_vpu2.c | 1 + drivers/media/platform/qcom/iris/iris_vpu3x.c | 9 +++----- drivers/media/platform/qcom/iris/iris_vpu4x.c | 24 ++++++++++++------= ---- drivers/media/platform/qcom/iris/iris_vpu_common.c | 16 +++++++++------ drivers/media/platform/qcom/iris/iris_vpu_common.h | 3 +++ 7 files changed, 38 insertions(+), 23 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_core.c b/drivers/media/p= latform/qcom/iris/iris_core.c index 8406c48d635b6eba0879396ce9f9ae2292743f09..dbaac01eb15a0e622e85635fddd= 29c1f7fc18662 100644 --- a/drivers/media/platform/qcom/iris/iris_core.c +++ b/drivers/media/platform/qcom/iris/iris_core.c @@ -75,6 +75,10 @@ int iris_core_init(struct iris_core *core) if (ret) goto error_unload_fw; =20 + ret =3D iris_vpu_switch_to_hwmode(core); + if (ret) + goto error_unload_fw; + ret =3D iris_hfi_core_init(core); if (ret) goto error_unload_fw; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.c b/drivers/m= edia/platform/qcom/iris/iris_hfi_common.c index 92112eb16c11048e28230a2926dfb46e3163aada..621c66593d88d47ef3438c98a07= cb29421c4e375 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.c @@ -159,6 +159,10 @@ int iris_hfi_pm_resume(struct iris_core *core) if (ret) goto err_suspend_hw; =20 + ret =3D iris_vpu_switch_to_hwmode(core); + if (ret) + goto err_suspend_hw; + ret =3D ops->sys_interframe_powercollapse(core); if (ret) goto err_suspend_hw; diff --git a/drivers/media/platform/qcom/iris/iris_vpu2.c b/drivers/media/p= latform/qcom/iris/iris_vpu2.c index 9c103a2e4e4eafee101a8a9b168fdc8ca76e277d..01ef40f3895743b3784464e2d5b= a2de1aeca5a4a 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_vpu2.c @@ -44,4 +44,5 @@ const struct vpu_ops iris_vpu2_ops =3D { .power_off_controller =3D iris_vpu_power_off_controller, .power_on_controller =3D iris_vpu_power_on_controller, .calc_freq =3D iris_vpu2_calc_freq, + .set_hwmode =3D iris_vpu_set_hwmode, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/= platform/qcom/iris/iris_vpu3x.c index fe4423b951b1e9e31d06dffc69d18071cc985731..3dad47be78b58f6cd5ed6f333b3= 376571a04dbf0 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -234,14 +234,8 @@ static int iris_vpu35_power_on_hw(struct iris_core *co= re) if (ret) goto err_disable_hw_free_clk; =20 - ret =3D dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER= _DOMAIN], true); - if (ret) - goto err_disable_hw_clk; - return 0; =20 -err_disable_hw_clk: - iris_disable_unprepare_clock(core, IRIS_HW_CLK); err_disable_hw_free_clk: iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); err_disable_axi_clk: @@ -266,6 +260,7 @@ const struct vpu_ops iris_vpu3_ops =3D { .power_off_controller =3D iris_vpu_power_off_controller, .power_on_controller =3D iris_vpu_power_on_controller, .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, + .set_hwmode =3D iris_vpu_set_hwmode, }; =20 const struct vpu_ops iris_vpu33_ops =3D { @@ -274,6 +269,7 @@ const struct vpu_ops iris_vpu33_ops =3D { .power_off_controller =3D iris_vpu33_power_off_controller, .power_on_controller =3D iris_vpu_power_on_controller, .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, + .set_hwmode =3D iris_vpu_set_hwmode, }; =20 const struct vpu_ops iris_vpu35_ops =3D { @@ -283,4 +279,5 @@ const struct vpu_ops iris_vpu35_ops =3D { .power_on_controller =3D iris_vpu35_vpu4x_power_on_controller, .program_bootup_registers =3D iris_vpu35_vpu4x_program_bootup_registers, .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, + .set_hwmode =3D iris_vpu_set_hwmode, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu4x.c b/drivers/media/= platform/qcom/iris/iris_vpu4x.c index a8db02ce5c5ec583c4027166b34ce51d3d683b4e..02e100a4045fced33d7a3545b63= 2cc5f0955233f 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu4x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu4x.c @@ -252,21 +252,10 @@ static int iris_vpu4x_power_on_hardware(struct iris_c= ore *core) ret =3D iris_vpu4x_power_on_apv(core); if (ret) goto disable_hw_clocks; - - iris_vpu4x_ahb_sync_reset_apv(core); } =20 - iris_vpu4x_ahb_sync_reset_hardware(core); - - ret =3D iris_vpu4x_genpd_set_hwmode(core, true, efuse_value); - if (ret) - goto disable_apv_power_domain; - return 0; =20 -disable_apv_power_domain: - if (!(efuse_value & DISABLE_VIDEO_APV_BIT)) - iris_vpu4x_power_off_apv(core); disable_hw_clocks: iris_vpu4x_disable_hardware_clocks(core, efuse_value); disable_vpp1_power_domain: @@ -359,6 +348,18 @@ static void iris_vpu4x_power_off_hardware(struct iris_= core *core) iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); } =20 +static int iris_vpu4x_set_hwmode(struct iris_core *core) +{ + u32 efuse_value =3D readl(core->reg_base + WRAPPER_EFUSE_MONITOR); + + if (!(efuse_value & DISABLE_VIDEO_APV_BIT)) + iris_vpu4x_ahb_sync_reset_apv(core); + + iris_vpu4x_ahb_sync_reset_hardware(core); + + return iris_vpu4x_genpd_set_hwmode(core, true, efuse_value); +} + const struct vpu_ops iris_vpu4x_ops =3D { .power_off_hw =3D iris_vpu4x_power_off_hardware, .power_on_hw =3D iris_vpu4x_power_on_hardware, @@ -366,4 +367,5 @@ const struct vpu_ops iris_vpu4x_ops =3D { .power_on_controller =3D iris_vpu35_vpu4x_power_on_controller, .program_bootup_registers =3D iris_vpu35_vpu4x_program_bootup_registers, .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, + .set_hwmode =3D iris_vpu4x_set_hwmode, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c index 548e5f1727fdb7543f76a1871f17257fa2360733..69e6126dc4d95ed9e5fccf59620= 5e84ec0bfc82d 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -292,14 +292,8 @@ int iris_vpu_power_on_hw(struct iris_core *core) if (ret && ret !=3D -ENOENT) goto err_disable_hw_clock; =20 - ret =3D dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER= _DOMAIN], true); - if (ret) - goto err_disable_hw_ahb_clock; - return 0; =20 -err_disable_hw_ahb_clock: - iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK); err_disable_hw_clock: iris_disable_unprepare_clock(core, IRIS_HW_CLK); err_disable_power: @@ -308,6 +302,16 @@ int iris_vpu_power_on_hw(struct iris_core *core) return ret; } =20 +int iris_vpu_set_hwmode(struct iris_core *core) +{ + return dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_= DOMAIN], true); +} + +int iris_vpu_switch_to_hwmode(struct iris_core *core) +{ + return core->iris_platform_data->vpu_ops->set_hwmode(core); +} + int iris_vpu35_vpu4x_power_off_controller(struct iris_core *core) { u32 clk_rst_tbl_size =3D core->iris_platform_data->clk_rst_tbl_size; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.h index f6dffc613b822341fb21e12de6b1395202f62cde..dee3b1349c5e869619c7f7c294d= d711f9ff72b92 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -21,6 +21,7 @@ struct vpu_ops { int (*power_on_controller)(struct iris_core *core); void (*program_bootup_registers)(struct iris_core *core); u64 (*calc_freq)(struct iris_inst *inst, size_t data_size); + int (*set_hwmode)(struct iris_core *core); }; =20 int iris_vpu_boot_firmware(struct iris_core *core); @@ -30,6 +31,8 @@ int iris_vpu_watchdog(struct iris_core *core, u32 intr_st= atus); int iris_vpu_prepare_pc(struct iris_core *core); int iris_vpu_power_on_controller(struct iris_core *core); int iris_vpu_power_on_hw(struct iris_core *core); +int iris_vpu_set_hwmode(struct iris_core *core); +int iris_vpu_switch_to_hwmode(struct iris_core *core); int iris_vpu_power_on(struct iris_core *core); int iris_vpu_power_off_controller(struct iris_core *core); void iris_vpu_power_off_hw(struct iris_core *core); --=20 2.34.1