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Fri, 27 Feb 2026 06:11:53 -0800 (PST) Received: from hu-vgarodia-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2adfb5c183bsm60960865ad.24.2026.02.27.06.11.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Feb 2026 06:11:52 -0800 (PST) From: Vikash Garodia Date: Fri, 27 Feb 2026 19:41:17 +0530 Subject: [PATCH v2 1/7] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260227-kaanapali-iris-v2-1-850043ac3933@oss.qualcomm.com> References: <20260227-kaanapali-iris-v2-0-850043ac3933@oss.qualcomm.com> In-Reply-To: <20260227-kaanapali-iris-v2-0-850043ac3933@oss.qualcomm.com> To: Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Saravana Kannan , Joerg Roedel , Will Deacon , Robin Murphy , Stefan Schmidt , Hans Verkuil , Krzysztof Kozlowski , Vishnu Reddy , Hans Verkuil Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, Bryan O'Donoghue , Vikash Garodia X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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When compared to previous generation, iris3x, it has, - separate power domains for stream and pixel processing hardware blocks (bse and vpp). - additional power domain for apv codec. - power domains for individual pipes (VPPx). - different clocks and reset lines. iommu-map include all the different stream-ids which can be possibly generated by vpu4 hardware as below, bitstream stream from vcodec non-pixel stream from vcodec non-pixel stream from tensilica pixel stream from vcodec secure bitstream stream from vcodec secure non-pixel stream from vcodec secure non-pixel stream from tensilica secure pixel stream from vcodec firmware stream from tensilica (might be handled by the TZ / hyp) This patch is depend on the below dt-schema patch. Link: https://github.com/devicetree-org/dt-schema/pull/184/changes/d341298d= 62805bc972dfba691da6b3b62aa3ff15 Signed-off-by: Vikash Garodia --- .../bindings/media/qcom,kaanapali-iris.yaml | 261 +++++++++++++++++= ++++ include/dt-bindings/media/qcom,iris.h | 18 ++ 2 files changed, 279 insertions(+) diff --git a/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.ya= ml b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml new file mode 100644 index 0000000000000000000000000000000000000000..db734c664a0417d8f5ea55b066f= 63f42583b1c14 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml @@ -0,0 +1,261 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,kaanapali-iris.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Kaanapali Iris video encoder and decoder + +maintainers: + - Vikash Garodia + - Dikshita Agarwal + +description: + The iris video processing unit is a video encode and decode accelerator + present on Qualcomm Kaanapali SoC. + +definitions: + iommu-types: + items: + - description: Function ID + - description: Phandle to IOMMU + - description: IOMMU stream ID base + - description: IOMMU stream ID mask + - description: Number of stream IDs + +properties: + compatible: + const: qcom,kaanapali-iris + + reg: + maxItems: 1 + + clocks: + maxItems: 10 + + clock-names: + items: + - const: iface + - const: core + - const: vcodec0_core + - const: iface1 + - const: core_freerun + - const: vcodec0_core_freerun + - const: vcodec_bse + - const: vcodec_vpp0 + - const: vcodec_vpp1 + - const: vcodec_apv + + dma-coherent: true + + firmware-name: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: cpu-cfg + - const: video-mem + + interrupts: + maxItems: 1 + + iommu-map: + description: | + - bitstream stream from vcodec + - non-pixel stream from vcodec + - non-pixel stream from tensilica + - pixel stream from vcodec + - secure bitstream stream from vcodec + - secure non-pixel stream from vcodec + - secure non-pixel stream from tensilica + - secure pixel stream from vcodec + # firmware might be handled by the TZ / hyp + - firmware stream from tensilica + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + $ref: '#/definitions/iommu-types' + minItems: 5 + minItems: 8 + maxItems: 9 + + memory-region: + maxItems: 1 + + operating-points-v2: true + opp-table: + type: object + + power-domains: + maxItems: 7 + + power-domain-names: + items: + - const: venus + - const: vcodec0 + - const: mxc + - const: mmcx + - const: vpp0 + - const: vpp1 + - const: apv + + resets: + maxItems: 4 + + reset-names: + items: + - const: bus0 + - const: bus1 + - const: core + - const: vcodec0_core + +required: + - compatible + - reg + - clocks + - clock-names + - dma-coherent + - interconnects + - interconnect-names + - interrupts + - iommu-map + - memory-region + - power-domains + - power-domain-names + - resets + - reset-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + video-codec@2000000 { + compatible =3D "qcom,kaanapali-iris"; + reg =3D <0x02000000 0xf0000>; + + clocks =3D <&gcc_video_axi0_clk>, + <&video_cc_mvs0c_clk>, + <&video_cc_mvs0_clk>, + <&gcc_video_axi1_clk>, + <&video_cc_mvs0c_freerun_clk>, + <&video_cc_mvs0_freerun_clk>, + <&video_cc_mvs0b_clk>, + <&video_cc_mvs0_vpp0_clk>, + <&video_cc_mvs0_vpp1_clk>, + <&video_cc_mvs0a_clk>; + clock-names =3D "iface", + "core", + "vcodec0_core", + "iface1", + "core_freerun", + "vcodec0_core_freerun", + "vcodec_bse", + "vcodec_vpp0", + "vcodec_vpp1", + "vcodec_apv"; + + dma-coherent; + + interconnects =3D <&gem_noc_master_appss_proc &config_noc_slave_ve= nus_cfg>, + <&mmss_noc_master_video_mvp &mc_virt_slave_ebi1>; + interconnect-names =3D "cpu-cfg", + "video-mem"; + + interrupts =3D ; + + iommu-map =3D , + , + , + , + , + , + , + , + ; + + memory-region =3D <&video_mem>; + + operating-points-v2 =3D <&iris_opp_table>; + + power-domains =3D <&video_cc_mvs0c_gdsc>, + <&video_cc_mvs0_gdsc>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>, + <&video_cc_mvs0_vpp0_gdsc>, + <&video_cc_mvs0_vpp1_gdsc>, + <&video_cc_mvs0a_gdsc>; + power-domain-names =3D "venus", + "vcodec0", + "mxc", + "mmcx", + "vpp0", + "vpp1", + "apv"; + + resets =3D <&gcc_video_axi0_clk_ares>, + <&gcc_video_axi1_clk_ares>, + <&video_cc_mvs0c_freerun_clk_ares>, + <&video_cc_mvs0_freerun_clk_ares>; + reset-names =3D "bus0", + "bus1", + "core", + "vcodec0_core"; + + iris_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-240000000 { + opp-hz =3D /bits/ 64 <240000000 240000000 240000000 360000= 000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>, + <&rpmhpd_opp_low_svs_d1>; + }; + + opp-338000000 { + opp-hz =3D /bits/ 64 <338000000 338000000 338000000 507000= 000>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-420000000 { + opp-hz =3D /bits/ 64 <420000000 420000000 420000000 630000= 000>; + required-opps =3D <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-444000000 { + opp-hz =3D /bits/ 64 <444000000 444000000 444000000 666000= 000>; + required-opps =3D <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-533000000 { + opp-hz =3D /bits/ 64 <533000000 533000000 533000000 800000= 000>; + required-opps =3D <&rpmhpd_opp_nom>, + <&rpmhpd_opp_nom>; + }; + + opp-630000000 { + opp-hz =3D /bits/ 64 <630000000 630000000 630000000 110400= 0000>; + required-opps =3D <&rpmhpd_opp_turbo>, + <&rpmhpd_opp_turbo>; + }; + + opp-800000000 { + opp-hz =3D /bits/ 64 <800000000 630000000 630000000 126000= 0000>; + required-opps =3D <&rpmhpd_opp_turbo_l0>, + <&rpmhpd_opp_turbo_l0>; + }; + + opp-1000000000 { + opp-hz =3D /bits/ 64 <1000000000 630000000 850000000 12600= 00000>; + required-opps =3D <&rpmhpd_opp_turbo_l1>, + <&rpmhpd_opp_turbo_l1>; + }; + }; + }; diff --git a/include/dt-bindings/media/qcom,iris.h b/include/dt-bindings/me= dia/qcom,iris.h new file mode 100644 index 0000000000000000000000000000000000000000..beb244289466ca938c7e5fe5cf1= 5526f606a3a6c --- /dev/null +++ b/include/dt-bindings/media/qcom,iris.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_MEDIA_QCOM_IRIS_H +#define _DT_BINDINGS_MEDIA_QCOM_IRIS_H + +/* Function identifiers for iommu-map to attach for the context bank devic= es */ +#define IRIS_BITSTREAM 0x100 +#define IRIS_NON_PIXEL 0x101 +#define IRIS_PIXEL 0x102 +#define IRIS_SECURE_BITSTREAM 0x200 +#define IRIS_SECURE_NON_PIXEL 0x201 +#define IRIS_SECURE_PIXEL 0x202 +#define IRIS_FIRMWARE 0x300 + +#endif --=20 2.34.1 From nobody Tue Apr 7 18:48:08 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1DBB6421899 for ; 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GDSC can be powered off, keeping in hw mode, thereby the vcodec registers programmed in TrustZone (TZ) carry default (reset) values. Move the transition to HW mode after firmware load and boot sequence. The bug was exposed with driver configuring different stream ids to different devices via iommu-map. With registers carrying reset values, VPU would not generate desired stream-id, thereby leading to SMMU fault. For vpu4, when GDSC is switched to HW mode, there is a need to perform the reset operation. Without reset, there are occassional issues of register corruption observed. Hence the vpu GDSC switch also involves the reset. Fixes: dde659d37036 ("media: iris: Introduce vpu ops for vpu4 with necessar= y hooks") Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia --- drivers/media/platform/qcom/iris/iris_core.c | 4 ++++ drivers/media/platform/qcom/iris/iris_hfi_common.c | 4 ++++ drivers/media/platform/qcom/iris/iris_vpu2.c | 1 + drivers/media/platform/qcom/iris/iris_vpu3x.c | 9 +++----- drivers/media/platform/qcom/iris/iris_vpu4x.c | 24 ++++++++++++------= ---- drivers/media/platform/qcom/iris/iris_vpu_common.c | 16 +++++++++------ drivers/media/platform/qcom/iris/iris_vpu_common.h | 3 +++ 7 files changed, 38 insertions(+), 23 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_core.c b/drivers/media/p= latform/qcom/iris/iris_core.c index 8406c48d635b6eba0879396ce9f9ae2292743f09..dbaac01eb15a0e622e85635fddd= 29c1f7fc18662 100644 --- a/drivers/media/platform/qcom/iris/iris_core.c +++ b/drivers/media/platform/qcom/iris/iris_core.c @@ -75,6 +75,10 @@ int iris_core_init(struct iris_core *core) if (ret) goto error_unload_fw; =20 + ret =3D iris_vpu_switch_to_hwmode(core); + if (ret) + goto error_unload_fw; + ret =3D iris_hfi_core_init(core); if (ret) goto error_unload_fw; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.c b/drivers/m= edia/platform/qcom/iris/iris_hfi_common.c index 92112eb16c11048e28230a2926dfb46e3163aada..621c66593d88d47ef3438c98a07= cb29421c4e375 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.c @@ -159,6 +159,10 @@ int iris_hfi_pm_resume(struct iris_core *core) if (ret) goto err_suspend_hw; =20 + ret =3D iris_vpu_switch_to_hwmode(core); + if (ret) + goto err_suspend_hw; + ret =3D ops->sys_interframe_powercollapse(core); if (ret) goto err_suspend_hw; diff --git a/drivers/media/platform/qcom/iris/iris_vpu2.c b/drivers/media/p= latform/qcom/iris/iris_vpu2.c index 9c103a2e4e4eafee101a8a9b168fdc8ca76e277d..01ef40f3895743b3784464e2d5b= a2de1aeca5a4a 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_vpu2.c @@ -44,4 +44,5 @@ const struct vpu_ops iris_vpu2_ops =3D { .power_off_controller =3D iris_vpu_power_off_controller, .power_on_controller =3D iris_vpu_power_on_controller, .calc_freq =3D iris_vpu2_calc_freq, + .set_hwmode =3D iris_vpu_set_hwmode, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/= platform/qcom/iris/iris_vpu3x.c index fe4423b951b1e9e31d06dffc69d18071cc985731..3dad47be78b58f6cd5ed6f333b3= 376571a04dbf0 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -234,14 +234,8 @@ static int iris_vpu35_power_on_hw(struct iris_core *co= re) if (ret) goto err_disable_hw_free_clk; =20 - ret =3D dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER= _DOMAIN], true); - if (ret) - goto err_disable_hw_clk; - return 0; =20 -err_disable_hw_clk: - iris_disable_unprepare_clock(core, IRIS_HW_CLK); err_disable_hw_free_clk: iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); err_disable_axi_clk: @@ -266,6 +260,7 @@ const struct vpu_ops iris_vpu3_ops =3D { .power_off_controller =3D iris_vpu_power_off_controller, .power_on_controller =3D iris_vpu_power_on_controller, .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, + .set_hwmode =3D iris_vpu_set_hwmode, }; =20 const struct vpu_ops iris_vpu33_ops =3D { @@ -274,6 +269,7 @@ const struct vpu_ops iris_vpu33_ops =3D { .power_off_controller =3D iris_vpu33_power_off_controller, .power_on_controller =3D iris_vpu_power_on_controller, .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, + .set_hwmode =3D iris_vpu_set_hwmode, }; =20 const struct vpu_ops iris_vpu35_ops =3D { @@ -283,4 +279,5 @@ const struct vpu_ops iris_vpu35_ops =3D { .power_on_controller =3D iris_vpu35_vpu4x_power_on_controller, .program_bootup_registers =3D iris_vpu35_vpu4x_program_bootup_registers, .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, + .set_hwmode =3D iris_vpu_set_hwmode, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu4x.c b/drivers/media/= platform/qcom/iris/iris_vpu4x.c index a8db02ce5c5ec583c4027166b34ce51d3d683b4e..02e100a4045fced33d7a3545b63= 2cc5f0955233f 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu4x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu4x.c @@ -252,21 +252,10 @@ static int iris_vpu4x_power_on_hardware(struct iris_c= ore *core) ret =3D iris_vpu4x_power_on_apv(core); if (ret) goto disable_hw_clocks; - - iris_vpu4x_ahb_sync_reset_apv(core); } =20 - iris_vpu4x_ahb_sync_reset_hardware(core); - - ret =3D iris_vpu4x_genpd_set_hwmode(core, true, efuse_value); - if (ret) - goto disable_apv_power_domain; - return 0; =20 -disable_apv_power_domain: - if (!(efuse_value & DISABLE_VIDEO_APV_BIT)) - iris_vpu4x_power_off_apv(core); disable_hw_clocks: iris_vpu4x_disable_hardware_clocks(core, efuse_value); disable_vpp1_power_domain: @@ -359,6 +348,18 @@ static void iris_vpu4x_power_off_hardware(struct iris_= core *core) iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); } =20 +static int iris_vpu4x_set_hwmode(struct iris_core *core) +{ + u32 efuse_value =3D readl(core->reg_base + WRAPPER_EFUSE_MONITOR); + + if (!(efuse_value & DISABLE_VIDEO_APV_BIT)) + iris_vpu4x_ahb_sync_reset_apv(core); + + iris_vpu4x_ahb_sync_reset_hardware(core); + + return iris_vpu4x_genpd_set_hwmode(core, true, efuse_value); +} + const struct vpu_ops iris_vpu4x_ops =3D { .power_off_hw =3D iris_vpu4x_power_off_hardware, .power_on_hw =3D iris_vpu4x_power_on_hardware, @@ -366,4 +367,5 @@ const struct vpu_ops iris_vpu4x_ops =3D { .power_on_controller =3D iris_vpu35_vpu4x_power_on_controller, .program_bootup_registers =3D iris_vpu35_vpu4x_program_bootup_registers, .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, + .set_hwmode =3D iris_vpu4x_set_hwmode, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c index 548e5f1727fdb7543f76a1871f17257fa2360733..69e6126dc4d95ed9e5fccf59620= 5e84ec0bfc82d 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -292,14 +292,8 @@ int iris_vpu_power_on_hw(struct iris_core *core) if (ret && ret !=3D -ENOENT) goto err_disable_hw_clock; =20 - ret =3D dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER= _DOMAIN], true); - if (ret) - goto err_disable_hw_ahb_clock; - return 0; =20 -err_disable_hw_ahb_clock: - iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK); err_disable_hw_clock: iris_disable_unprepare_clock(core, IRIS_HW_CLK); err_disable_power: @@ -308,6 +302,16 @@ int iris_vpu_power_on_hw(struct iris_core *core) return ret; } =20 +int iris_vpu_set_hwmode(struct iris_core *core) +{ + return dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_= DOMAIN], true); +} + +int iris_vpu_switch_to_hwmode(struct iris_core *core) +{ + return core->iris_platform_data->vpu_ops->set_hwmode(core); +} + int iris_vpu35_vpu4x_power_off_controller(struct iris_core *core) { u32 clk_rst_tbl_size =3D core->iris_platform_data->clk_rst_tbl_size; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.h index f6dffc613b822341fb21e12de6b1395202f62cde..dee3b1349c5e869619c7f7c294d= d711f9ff72b92 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -21,6 +21,7 @@ struct vpu_ops { int (*power_on_controller)(struct iris_core *core); void (*program_bootup_registers)(struct iris_core *core); u64 (*calc_freq)(struct iris_inst *inst, size_t data_size); + int (*set_hwmode)(struct iris_core *core); }; =20 int iris_vpu_boot_firmware(struct iris_core *core); @@ -30,6 +31,8 @@ int iris_vpu_watchdog(struct iris_core *core, u32 intr_st= atus); int iris_vpu_prepare_pc(struct iris_core *core); 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Iris devices need their own bus so that each iris device can run its own dma_configure() logic. Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia --- drivers/iommu/iommu.c | 4 ++++ drivers/media/platform/qcom/iris/Makefile | 4 ++++ drivers/media/platform/qcom/iris/iris_vpu_bus.c | 32 +++++++++++++++++++++= ++++ include/linux/iris_vpu_bus.h | 13 ++++++++++ 4 files changed, 53 insertions(+) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 35db5178095404fec87cd0f18e44ea97cf354e78..fd5fb7c10da22ab548d359ca1f4= 4504acc3d646c 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -178,6 +179,9 @@ static const struct bus_type * const iommu_buses[] =3D { #ifdef CONFIG_CDX_BUS &cdx_bus_type, #endif +#if IS_ENABLED(CONFIG_VIDEO_QCOM_IRIS) + &iris_vpu_bus_type, +#endif }; =20 /* diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/plat= form/qcom/iris/Makefile index 2abbd3aeb4af07e52bf372a4b2f352463529c92c..6f4052b98491aeddc299669334d= 4c93e9a3420e4 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -31,3 +31,7 @@ qcom-iris-objs +=3D iris_platform_gen1.o endif =20 obj-$(CONFIG_VIDEO_QCOM_IRIS) +=3D qcom-iris.o + +ifdef CONFIG_VIDEO_QCOM_IRIS +obj-y +=3D iris_vpu_bus.o +endif diff --git a/drivers/media/platform/qcom/iris/iris_vpu_bus.c b/drivers/medi= a/platform/qcom/iris/iris_vpu_bus.c new file mode 100644 index 0000000000000000000000000000000000000000..34ce78d9b0ff1feda15ba4f060a= 56d02749a0858 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_vpu_bus.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +#include "iris_platform_common.h" + +static int iris_vpu_bus_dma_configure(struct device *dev) +{ + struct iris_context_bank *cb =3D dev_get_drvdata(dev); + + if (!cb) + return -ENODEV; + + return of_dma_configure_id(dev, dev->parent->of_node, true, &cb->f_id); +} + +const struct bus_type iris_vpu_bus_type =3D { + .name =3D "iris-bus", + .dma_configure =3D iris_vpu_bus_dma_configure, +}; +EXPORT_SYMBOL_GPL(iris_vpu_bus_type); + +static int __init iris_vpu_bus_init(void) +{ + return bus_register(&iris_vpu_bus_type); +} + +postcore_initcall(iris_vpu_bus_init); diff --git a/include/linux/iris_vpu_bus.h b/include/linux/iris_vpu_bus.h new file mode 100644 index 0000000000000000000000000000000000000000..8aba472fcadd269e196b7243da5= 660deaff31abb --- /dev/null +++ b/include/linux/iris_vpu_bus.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2026 Qualcomm Innovation Center, Inc. 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Different stream IDs from VPU would be associated to one of these CB. Multiple CBs are needed to increase the IOVA for the video usecases like higher concurrent sessions. Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia --- .../platform/qcom/iris/iris_platform_common.h | 18 +++++++ drivers/media/platform/qcom/iris/iris_probe.c | 60 ++++++++++++++++++= ++-- drivers/media/platform/qcom/iris/iris_resources.c | 36 +++++++++++++ drivers/media/platform/qcom/iris/iris_resources.h | 1 + 4 files changed, 111 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 5a489917580eb10022fdcb52f7321a915e8b239d..03c50d6e54853fca34d7d32f65d= 09eb80945fcdd 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -204,6 +204,22 @@ struct icc_vote_data { u32 fps; }; =20 +enum iris_buffer_region { + IRIS_BITSTREAM_REGION =3D BIT(0), + IRIS_NON_PIXEL_REGION =3D BIT(1), + IRIS_PIXEL_REGION =3D BIT(2), + IRIS_SECURE_BITSTREAM_REGION =3D BIT(3), + IRIS_SECURE_NON_PIXEL_REGION =3D BIT(4), + IRIS_SECURE_PIXEL_REGION =3D BIT(5), +}; + +struct iris_context_bank { + struct device *dev; + const char *name; + const u32 f_id; + const enum iris_buffer_region region; +}; + enum platform_pm_domain_type { IRIS_CTRL_POWER_DOMAIN, IRIS_HW_POWER_DOMAIN, @@ -246,6 +262,8 @@ struct iris_platform_data { u32 inst_fw_caps_enc_size; const struct tz_cp_config *tz_cp_config_data; u32 tz_cp_config_data_size; + struct iris_context_bank *cb_data; + u32 cb_data_size; u32 core_arch; u32 hw_response_timeout; struct ubwc_config_data *ubwc_config; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index ddaacda523ecb9990af0dd0640196223fbcc2cab..557adb038328a75510591d91569= 819abc0b7b1c9 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -123,6 +123,49 @@ static int iris_init_resets(struct iris_core *core) core->iris_platform_data->controller_rst_tbl_size); } =20 +static void iris_destroy_child_device(struct iris_context_bank *cb) +{ + struct device *dev =3D cb->dev; + + if (dev) + device_unregister(dev); + + cb->dev =3D NULL; +} + +static void iris_deinit_context_bank_devices(struct iris_core *core) +{ + struct iris_context_bank *cb; + int i; + + for (i =3D 0; i < core->iris_platform_data->cb_data_size; i++) { + cb =3D &core->iris_platform_data->cb_data[i]; + iris_destroy_child_device(cb); + } +} + +static int iris_init_context_bank_devices(struct iris_core *core) +{ + struct iris_context_bank *cb; + int ret, i; + + for (i =3D 0; i < core->iris_platform_data->cb_data_size; i++) { + cb =3D &core->iris_platform_data->cb_data[i]; + + ret =3D iris_create_child_device_and_map(core, cb); + if (ret) + goto err_deinit_cb; + } + + return 0; + +err_deinit_cb: + while (i-- > 0) + iris_destroy_child_device(&core->iris_platform_data->cb_data[i]); + + return ret; +} + static int iris_init_resources(struct iris_core *core) { int ret; @@ -193,6 +236,7 @@ static void iris_remove(struct platform_device *pdev) return; =20 iris_core_deinit(core); + iris_deinit_context_bank_devices(core); =20 video_unregister_device(core->vdev_dec); video_unregister_device(core->vdev_enc); @@ -275,12 +319,18 @@ static int iris_probe(struct platform_device *pdev) =20 platform_set_drvdata(pdev, core); =20 - dma_mask =3D core->iris_platform_data->dma_mask; - - ret =3D dma_set_mask_and_coherent(dev, dma_mask); + ret =3D iris_init_context_bank_devices(core); if (ret) goto err_vdev_unreg_enc; =20 + dma_mask =3D core->iris_platform_data->dma_mask; + + if (device_iommu_mapped(core->dev)) { + ret =3D dma_set_mask_and_coherent(core->dev, dma_mask); + if (ret) + goto err_deinit_cb; + } + dma_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32)); dma_set_seg_boundary(&pdev->dev, DMA_BIT_MASK(32)); =20 @@ -288,10 +338,12 @@ static int iris_probe(struct platform_device *pdev) pm_runtime_use_autosuspend(core->dev); ret =3D devm_pm_runtime_enable(core->dev); if (ret) - goto err_vdev_unreg_enc; + goto err_deinit_cb; =20 return 0; =20 +err_deinit_cb: + iris_deinit_context_bank_devices(core); err_vdev_unreg_enc: video_unregister_device(core->vdev_enc); err_vdev_unreg_dec: diff --git a/drivers/media/platform/qcom/iris/iris_resources.c b/drivers/me= dia/platform/qcom/iris/iris_resources.c index 773f6548370a257b8ae7332242544266cbbd61a9..be58e8620086d0f82c2c2bda292= 47483f5c56d79 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.c +++ b/drivers/media/platform/qcom/iris/iris_resources.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -141,3 +142,38 @@ int iris_disable_unprepare_clock(struct iris_core *cor= e, enum platform_clk_type =20 return 0; } + +static void iris_device_release(struct device *dev) +{ + dev_set_drvdata(dev, NULL); + kfree(dev); +} + +int iris_create_child_device_and_map(struct iris_core *core, struct iris_c= ontext_bank *cb) +{ + struct device *dev; + int ret; + + dev =3D kzalloc_obj(*dev); + if (!dev) + return -ENOMEM; + + dev->release =3D iris_device_release; + dev->bus =3D &iris_vpu_bus_type; + dev->parent =3D core->dev; + dev->coherent_dma_mask =3D core->iris_platform_data->dma_mask; + dev->dma_mask =3D &dev->coherent_dma_mask; + + dev_set_name(dev, "%s", cb->name); + dev_set_drvdata(dev, cb); + + ret =3D device_register(dev); + if (ret) { + put_device(dev); + return ret; + } + + cb->dev =3D dev; + + return 0; +} diff --git a/drivers/media/platform/qcom/iris/iris_resources.h b/drivers/me= dia/platform/qcom/iris/iris_resources.h index 6bfbd2dc6db095ec05e53c894e048285f82446c6..b7efe15facb203eea9ae13d5f0a= bdcc2ea718b4d 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.h +++ b/drivers/media/platform/qcom/iris/iris_resources.h @@ -15,5 +15,6 @@ int iris_unset_icc_bw(struct iris_core *core); int iris_set_icc_bw(struct iris_core *core, unsigned long icc_bw); int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk= _type clk_type); int iris_prepare_enable_clock(struct iris_core *core, enum platform_clk_ty= pe clk_type); +int iris_create_child_device_and_map(struct iris_core *core, struct iris_c= ontext_bank *cb); =20 #endif --=20 2.34.1 From nobody Tue Apr 7 18:48:08 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D7C13A9629 for ; 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Fallback to parent device for backward compatibility. Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia --- drivers/media/platform/qcom/iris/iris_buffer.c | 7 +-- drivers/media/platform/qcom/iris/iris_buffer.h | 2 + drivers/media/platform/qcom/iris/iris_hfi_queue.c | 16 +++--- drivers/media/platform/qcom/iris/iris_resources.c | 60 +++++++++++++++++++= ++++ drivers/media/platform/qcom/iris/iris_resources.h | 2 + drivers/media/platform/qcom/iris/iris_vidc.c | 4 +- 6 files changed, 79 insertions(+), 12 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media= /platform/qcom/iris/iris_buffer.c index 9151f43bc6b9c2c34c803de4231d1e6de0bec6c4..95962c19c334f08a74c5b7e8ba9= 78ab631a65e9c 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -335,8 +335,8 @@ void iris_get_internal_buffers(struct iris_inst *inst, = u32 plane) static int iris_create_internal_buffer(struct iris_inst *inst, enum iris_buffer_type buffer_type, u32 index) { + struct device *dev =3D iris_get_cb_dev(inst->core, inst, buffer_type); struct iris_buffers *buffers =3D &inst->buffers[buffer_type]; - struct iris_core *core =3D inst->core; struct iris_buffer *buffer; =20 if (!buffers->size) @@ -352,7 +352,7 @@ static int iris_create_internal_buffer(struct iris_inst= *inst, buffer->buffer_size =3D buffers->size; buffer->dma_attrs =3D DMA_ATTR_WRITE_COMBINE | DMA_ATTR_NO_KERNEL_MAPPING; =20 - buffer->kvaddr =3D dma_alloc_attrs(core->dev, buffer->buffer_size, + buffer->kvaddr =3D dma_alloc_attrs(dev, buffer->buffer_size, &buffer->device_addr, GFP_KERNEL, buffer->dma_attrs); if (!buffer->kvaddr) { kfree(buffer); @@ -490,9 +490,10 @@ int iris_queue_internal_buffers(struct iris_inst *inst= , u32 plane) int iris_destroy_internal_buffer(struct iris_inst *inst, struct iris_buffe= r *buffer) { struct iris_core *core =3D inst->core; + struct device *dev =3D iris_get_cb_dev(core, inst, buffer->type); =20 list_del(&buffer->list); - dma_free_attrs(core->dev, buffer->buffer_size, buffer->kvaddr, + dma_free_attrs(dev, buffer->buffer_size, buffer->kvaddr, buffer->device_addr, buffer->dma_attrs); kfree(buffer); =20 diff --git a/drivers/media/platform/qcom/iris/iris_buffer.h b/drivers/media= /platform/qcom/iris/iris_buffer.h index 75bb767761824c4c02e0df9b765896cc093be333..9520aa290b44f06ed2004ad8994= 0c19d1c08a3d2 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.h +++ b/drivers/media/platform/qcom/iris/iris_buffer.h @@ -28,6 +28,7 @@ struct iris_inst; * @BUF_SCRATCH_2: buffer to store encoding context data for HW * @BUF_VPSS: buffer to store VPSS context data for HW * @BUF_PARTIAL: buffer for AV1 IBC data + * @BUF_HFI_QUEUE: buffer for hardware firmware interface queue * @BUF_TYPE_MAX: max buffer types */ enum iris_buffer_type { @@ -44,6 +45,7 @@ enum iris_buffer_type { BUF_SCRATCH_2, BUF_VPSS, BUF_PARTIAL, + BUF_HFI_QUEUE, BUF_TYPE_MAX, }; =20 diff --git a/drivers/media/platform/qcom/iris/iris_hfi_queue.c b/drivers/me= dia/platform/qcom/iris/iris_hfi_queue.c index b3ed06297953b902d5ea6c452385a88d5431ac66..c1241fb8dc6519020a063cbba87= aed665701d7ae 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_queue.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_queue.c @@ -245,25 +245,26 @@ static void iris_hfi_queue_deinit(struct iris_iface_q= _info *iface_q) =20 int iris_hfi_queues_init(struct iris_core *core) { + struct device *dev =3D iris_get_cb_dev(core, NULL, BUF_HFI_QUEUE); struct iris_hfi_queue_table_header *q_tbl_hdr; u32 queue_size; =20 /* Iris hardware requires 4K queue alignment */ queue_size =3D ALIGN((sizeof(*q_tbl_hdr) + (IFACEQ_QUEUE_SIZE * IFACEQ_NU= MQ)), SZ_4K); - core->iface_q_table_vaddr =3D dma_alloc_attrs(core->dev, queue_size, + core->iface_q_table_vaddr =3D dma_alloc_attrs(dev, queue_size, &core->iface_q_table_daddr, GFP_KERNEL, DMA_ATTR_WRITE_COMBINE); if (!core->iface_q_table_vaddr) { - dev_err(core->dev, "queues alloc and map failed\n"); + dev_err(dev, "queues alloc and map failed\n"); return -ENOMEM; } =20 - core->sfr_vaddr =3D dma_alloc_attrs(core->dev, SFR_SIZE, + core->sfr_vaddr =3D dma_alloc_attrs(dev, SFR_SIZE, &core->sfr_daddr, GFP_KERNEL, DMA_ATTR_WRITE_COMBINE); if (!core->sfr_vaddr) { - dev_err(core->dev, "sfr alloc and map failed\n"); - dma_free_attrs(core->dev, sizeof(*q_tbl_hdr), core->iface_q_table_vaddr, + dev_err(dev, "sfr alloc and map failed\n"); + dma_free_attrs(dev, sizeof(*q_tbl_hdr), core->iface_q_table_vaddr, core->iface_q_table_daddr, DMA_ATTR_WRITE_COMBINE); return -ENOMEM; } @@ -291,6 +292,7 @@ int iris_hfi_queues_init(struct iris_core *core) =20 void iris_hfi_queues_deinit(struct iris_core *core) { + struct device *dev =3D iris_get_cb_dev(core, NULL, BUF_HFI_QUEUE); u32 queue_size; =20 if (!core->iface_q_table_vaddr) @@ -300,7 +302,7 @@ void iris_hfi_queues_deinit(struct iris_core *core) iris_hfi_queue_deinit(&core->message_queue); iris_hfi_queue_deinit(&core->command_queue); =20 - dma_free_attrs(core->dev, SFR_SIZE, core->sfr_vaddr, + dma_free_attrs(dev, SFR_SIZE, core->sfr_vaddr, core->sfr_daddr, DMA_ATTR_WRITE_COMBINE); =20 core->sfr_vaddr =3D NULL; @@ -309,7 +311,7 @@ void iris_hfi_queues_deinit(struct iris_core *core) queue_size =3D ALIGN(sizeof(struct iris_hfi_queue_table_header) + (IFACEQ_QUEUE_SIZE * IFACEQ_NUMQ), SZ_4K); =20 - dma_free_attrs(core->dev, queue_size, core->iface_q_table_vaddr, + dma_free_attrs(dev, queue_size, core->iface_q_table_vaddr, core->iface_q_table_daddr, DMA_ATTR_WRITE_COMBINE); =20 core->iface_q_table_vaddr =3D NULL; diff --git a/drivers/media/platform/qcom/iris/iris_resources.c b/drivers/me= dia/platform/qcom/iris/iris_resources.c index be58e8620086d0f82c2c2bda29247483f5c56d79..65544cb0fa8fc4b250b0a0be1bb= 900d74b999d35 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.c +++ b/drivers/media/platform/qcom/iris/iris_resources.c @@ -13,6 +13,7 @@ #include =20 #include "iris_core.h" +#include "iris_instance.h" #include "iris_resources.h" =20 #define BW_THRESHOLD 50000 @@ -177,3 +178,62 @@ int iris_create_child_device_and_map(struct iris_core = *core, struct iris_context =20 return 0; } + +static enum iris_buffer_region iris_get_region(struct iris_inst *inst, + enum iris_buffer_type buffer_type) +{ + switch (buffer_type) { + case BUF_INPUT: + if (inst && inst->domain =3D=3D ENCODER) + return IRIS_PIXEL_REGION; + else if (inst && inst->domain =3D=3D DECODER) + return IRIS_BITSTREAM_REGION; + break; + case BUF_OUTPUT: + if (inst && inst->domain =3D=3D ENCODER) + return IRIS_BITSTREAM_REGION; + else if (inst && inst->domain =3D=3D DECODER) + return IRIS_PIXEL_REGION; + break; + case BUF_BIN: + return IRIS_BITSTREAM_REGION; + case BUF_DPB: + case BUF_PARTIAL: + case BUF_SCRATCH_2: + case BUF_VPSS: + return IRIS_PIXEL_REGION; + case BUF_ARP: + case BUF_COMV: + case BUF_HFI_QUEUE: + case BUF_LINE: + case BUF_NON_COMV: + case BUF_PERSIST: + return IRIS_NON_PIXEL_REGION; + default: + return 0; + } + + return 0; +} + +struct device *iris_get_cb_dev(struct iris_core *core, struct iris_inst *i= nst, + enum iris_buffer_type buffer_type) +{ + enum iris_buffer_region region; + struct device *dev =3D NULL; + int i; + + region =3D iris_get_region(inst, buffer_type); + + for (i =3D 0; i < core->iris_platform_data->cb_data_size; i++) { + if (core->iris_platform_data->cb_data[i].region & region) { + dev =3D core->iris_platform_data->cb_data[i].dev; + break; + } + } + + if (!dev) + dev =3D core->dev; + + return dev; +} diff --git a/drivers/media/platform/qcom/iris/iris_resources.h b/drivers/me= dia/platform/qcom/iris/iris_resources.h index b7efe15facb203eea9ae13d5f0abdcc2ea718b4d..ea31726f1789130fccf6b24540a= 62b86cb3c36ac 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.h +++ b/drivers/media/platform/qcom/iris/iris_resources.h @@ -16,5 +16,7 @@ int iris_set_icc_bw(struct iris_core *core, unsigned long= icc_bw); int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk= _type clk_type); int iris_prepare_enable_clock(struct iris_core *core, enum platform_clk_ty= pe clk_type); int iris_create_child_device_and_map(struct iris_core *core, struct iris_c= ontext_bank *cb); +struct device *iris_get_cb_dev(struct iris_core *core, struct iris_inst *i= nst, + enum iris_buffer_type buffer_type); =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/p= latform/qcom/iris/iris_vidc.c index bd38d84c9cc79d15585ed5dd5f905a37521cb6dc..b61d7941d88662f34a9d2ab3b6c= 5bd9acf4b5df5 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -107,7 +107,7 @@ iris_m2m_queue_init(void *priv, struct vb2_queue *src_v= q, struct vb2_queue *dst_ src_vq->drv_priv =3D inst; src_vq->buf_struct_size =3D sizeof(struct iris_buffer); src_vq->min_reqbufs_allocation =3D MIN_BUFFERS; - src_vq->dev =3D inst->core->dev; + src_vq->dev =3D iris_get_cb_dev(inst->core, inst, BUF_INPUT); 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a=ed25519-sha256; t=1772201499; l=4313; i=vikash.garodia@oss.qualcomm.com; s=20241104; h=from:subject:message-id; bh=4cpK+rYSKMeDiyBq3UdtWW7Lob7DBlHMDZuSeWAVS50=; b=BUknAXG+k+86NFxEHwE9YE7QULGUx4cd71iL+7BDqbDgKfbc2uMwUqNcyto4ytlqfXZ6fLPuK Gw/mcauF2+yBXckzNPGrhfLNxiqFNOwzbiyamBwOk4QW+IJ4rbpEeam X-Developer-Key: i=vikash.garodia@oss.qualcomm.com; a=ed25519; pk=LY9Eqp4KiHWxzGNKGHbwRFEJOfRCSzG/rxQNmvZvaKE= X-Proofpoint-ORIG-GUID: 2-1vPxlZgi8aqQ_a1F7FSfrOk-Fh9zyn X-Proofpoint-GUID: 2-1vPxlZgi8aqQ_a1F7FSfrOk-Fh9zyn X-Authority-Analysis: v=2.4 cv=DOqCIiNb c=1 sm=1 tr=0 ts=69a1a64b cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=MVHsPVnmqsIq8L41Ef0A:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjI3MDEyNSBTYWx0ZWRfXz9w4gKIDFjnF 2CvShhghDtBtLZh3+g6otQrC83cQnkUMfAr08PeFNE1KjmB+mkn/iqQQduxjWUolQO0m61gstmF tGVtKHMlxb2apvLkAIEa1UkSGtSrbMk7jyUWV4CwQlDNXO1usYfNiZ1YVF/c5nMP55YsNAbypbi 8xl7yRak7pfRf/YVWzzjz0E6x9WFtUdalPf5FDlDvQ+irVsTrJqXVd8eSJpEjNUIGhNf4CQKmNh SFgD8Eb0hZiYXZfHE4xFY6Q3RhbAn6ERJcDW7hsM22qfbFllnkTlIE2EyNf7x1MEQ4Jbnulaj8O z4sqeKyS5HjFb9ySLnjLH9CPsceSwnBUTQ7VLzQ/sZANbVUzenbo+WqU5uXDTP9ImiD0qJ4GnBP acVCQitYNbpKOJ4BvcyXxNhVc5seTVMhH/BawYTi4eUdzc+jVpamkwsRo5hLH+SYTpDdUPCxpnj qHmy5paN3iqwNs4xP3A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-27_02,2026-02-27_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 malwarescore=0 adultscore=0 priorityscore=1501 clxscore=1015 suspectscore=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602270125 The H265 decoder line buffer size calculation for iris4 (VPU4) was previously reusing the iris3 formula. While this works for most resolutions, certain configurations require a larger buffer size on iris4, causing firmware errors during decode. This resolves firmware failures seen with specific test vectors on kaanapali (iris4), and fixes the following failing fluster tests - PICSIZE_C_Bossen_1 - WPP_E_ericsson_MAIN_2 Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia --- drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 51 ++++++++++++++++++= +++- 1 file changed, 50 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_buffer.c index 9270422c16019ba658ee8813940cb9110ad030a1..a4d599c49ce9052b609b9cedf65= f669ba78b5407 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c @@ -1755,6 +1755,55 @@ static u32 hfi_vpu4x_buffer_line_vp9d(u32 frame_widt= h, u32 frame_height, u32 _yu return lb_size + dpb_obp_size; } =20 +static u32 hfi_vpu4x_buffer_line_h265d(u32 frame_width, u32 frame_height, = bool is_opb, + u32 num_vpp_pipes) +{ + u32 num_lcu_per_pipe, fe_left_lb, se_left_lb, vsp_left_lb, top_lb, qp_siz= e, + dpb_obp =3D 0, lcu_size =3D 16; + + num_lcu_per_pipe =3D (DIV_ROUND_UP(frame_height, lcu_size) / num_vpp_pipe= s) + + (DIV_ROUND_UP(frame_height, lcu_size) % num_vpp_pipes); + + fe_left_lb =3D ALIGN((DMA_ALIGNMENT * num_lcu_per_pipe), DMA_ALIGNMENT) * + FE_LFT_CTRL_LINE_NUMBERS; + fe_left_lb +=3D ALIGN((DMA_ALIGNMENT * 2 * num_lcu_per_pipe), DMA_ALIGNME= NT) * + FE_LFT_DB_DATA_LINE_NUMBERS; + fe_left_lb +=3D ALIGN((DMA_ALIGNMENT * num_lcu_per_pipe), DMA_ALIGNMENT); + fe_left_lb +=3D ALIGN((DMA_ALIGNMENT * 2 * num_lcu_per_pipe), DMA_ALIGNME= NT); + fe_left_lb +=3D ALIGN((DMA_ALIGNMENT * 8 * num_lcu_per_pipe), DMA_ALIGNME= NT) * + FE_LFT_LR_DATA_LINE_NUMBERS; + + if (is_opb) + dpb_obp =3D size_dpb_opb(frame_height, lcu_size) * num_vpp_pipes; + + se_left_lb =3D max_t(u32, (ALIGN(frame_height, BUFFER_ALIGNMENT_16_BYTES)= >> 3) * + MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE, + max_t(u32, (ALIGN(frame_height, BUFFER_ALIGNMENT_32_BYTES) >> 3) * + MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE, + (ALIGN(frame_height, BUFFER_ALIGNMENT_64_BYTES) >> 3) * + MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE)); + + vsp_left_lb =3D ALIGN(DIV_ROUND_UP(frame_height, BUFFER_ALIGNMENT_64_BYTE= S) * + H265_NUM_TILE_ROW, DMA_ALIGNMENT); + + top_lb =3D ALIGN((DMA_ALIGNMENT * DIV_ROUND_UP(frame_width, lcu_size)), D= MA_ALIGNMENT) * + FE_TOP_CTRL_LINE_NUMBERS; + top_lb +=3D ALIGN(DMA_ALIGNMENT * 2 * DIV_ROUND_UP(frame_width, lcu_size)= , DMA_ALIGNMENT) * + FE_TOP_DATA_LUMA_LINE_NUMBERS; + top_lb +=3D ALIGN(DMA_ALIGNMENT * 2 * (DIV_ROUND_UP(frame_width, lcu_size= ) + 1), + DMA_ALIGNMENT) * FE_TOP_DATA_CHROMA_LINE_NUMBERS; + top_lb +=3D ALIGN(ALIGN(frame_width, BUFFER_ALIGNMENT_64_BYTES) * 2, DMA_= ALIGNMENT); + top_lb +=3D ALIGN(ALIGN(frame_width, BUFFER_ALIGNMENT_64_BYTES) * 6, DMA_= ALIGNMENT); + top_lb +=3D size_h265d_lb_vsp_top(frame_width, frame_height); + + qp_size =3D size_h265d_qp(frame_width, frame_height); + + return ((ALIGN(dpb_obp, DMA_ALIGNMENT) + ALIGN(se_left_lb, DMA_ALIGNMENT)= + + ALIGN(vsp_left_lb, DMA_ALIGNMENT)) * num_vpp_pipes) + + ALIGN(fe_left_lb, DMA_ALIGNMENT) + ALIGN(top_lb, DMA_ALIGNMENT) + + ALIGN(qp_size, DMA_ALIGNMENT); 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Fri, 27 Feb 2026 06:12:34 -0800 (PST) X-Received: by 2002:a17:902:d4cb:b0:2a0:d629:9035 with SMTP id d9443c01a7336-2ae2e3cca53mr37300015ad.3.1772201554106; Fri, 27 Feb 2026 06:12:34 -0800 (PST) Received: from hu-vgarodia-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2adfb5c183bsm60960865ad.24.2026.02.27.06.12.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Feb 2026 06:12:32 -0800 (PST) From: Vikash Garodia Date: Fri, 27 Feb 2026 19:41:23 +0530 Subject: [PATCH v2 7/7] media: iris: add platform data for kaanapali Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260227-kaanapali-iris-v2-7-850043ac3933@oss.qualcomm.com> References: <20260227-kaanapali-iris-v2-0-850043ac3933@oss.qualcomm.com> In-Reply-To: <20260227-kaanapali-iris-v2-0-850043ac3933@oss.qualcomm.com> To: Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Saravana Kannan , Joerg Roedel , Will Deacon , Robin Murphy , Stefan Schmidt , Hans Verkuil , Krzysztof Kozlowski , Vishnu Reddy , Hans Verkuil Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, Bryan O'Donoghue , Vikash Garodia X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Move the configurations that differs in a per-SoC platform header, that will contain SoC specific data. Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia --- .../platform/qcom/iris/iris_platform_common.h | 1 + .../media/platform/qcom/iris/iris_platform_gen2.c | 90 ++++++++++++++++++= ++++ .../platform/qcom/iris/iris_platform_kaanapali.h | 86 ++++++++++++++++++= +++ drivers/media/platform/qcom/iris/iris_probe.c | 4 + 4 files changed, 181 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 03c50d6e54853fca34d7d32f65d09eb80945fcdd..34c8ae7f9f957936b6219d8557f= f3d86d309cb2a 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -41,6 +41,7 @@ enum pipe_type { PIPE_4 =3D 4, }; =20 +extern const struct iris_platform_data kaanapali_data; extern const struct iris_platform_data qcs8300_data; extern const struct iris_platform_data sc7280_data; extern const struct iris_platform_data sm8250_data; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index 5da90d47f9c6eab4a7e6b17841fdc0e599397bf7..df906f6b9fcd80100872a128150= 36a3aad9e925b 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -12,6 +12,7 @@ #include "iris_vpu_buffer.h" #include "iris_vpu_common.h" =20 +#include "iris_platform_kaanapali.h" #include "iris_platform_qcs8300.h" #include "iris_platform_sm8650.h" #include "iris_platform_sm8750.h" @@ -921,6 +922,95 @@ static const u32 sm8550_enc_op_int_buf_tbl[] =3D { BUF_SCRATCH_2, }; =20 +const struct iris_platform_data kaanapali_data =3D { + .get_instance =3D iris_hfi_gen2_get_instance, + .init_hfi_command_ops =3D iris_hfi_gen2_command_ops_init, + .init_hfi_response_ops =3D iris_hfi_gen2_response_ops_init, + .get_vpu_buffer_size =3D iris_vpu4x_buf_size, + .vpu_ops =3D &iris_vpu4x_ops, + .set_preset_registers =3D iris_set_sm8550_preset_registers, + .icc_tbl =3D sm8550_icc_table, + .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl =3D kaanapali_clk_reset_table, + .clk_rst_tbl_size =3D ARRAY_SIZE(kaanapali_clk_reset_table), + .bw_tbl_dec =3D sm8550_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl =3D kaanapali_pmdomain_table, + .pmdomain_tbl_size =3D ARRAY_SIZE(kaanapali_pmdomain_table), + .opp_pd_tbl =3D sm8550_opp_pd_table, + .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl =3D kaanapali_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(kaanapali_clk_table), + .opp_clk_tbl =3D kaanapali_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask =3D 0xffc00000 - 1, + .fwname =3D "qcom/vpu/vpu40_p2_s7.mbn", + .pas_id =3D IRIS_PAS_ID, + .inst_iris_fmts =3D platform_fmts_sm8550_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), + .inst_caps =3D &platform_inst_cap_sm8550, + .inst_fw_caps_dec =3D inst_fw_cap_sm8550_dec, + .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_dec), + .inst_fw_caps_enc =3D inst_fw_cap_sm8550_enc, + .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_enc), + .tz_cp_config_data =3D tz_cp_config_kaanapali, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_kaanapali), + .cb_data =3D kaanapali_cb_data, + .cb_data_size =3D ARRAY_SIZE(kaanapali_cb_data), + .core_arch =3D VIDEO_ARCH_LX, + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .ubwc_config =3D &ubwc_config_sm8550, + .num_vpp_pipe =3D 2, + .max_session_count =3D 16, + .max_core_mbpf =3D NUM_MBS_8K * 2, + .max_core_mbps =3D ((8192 * 4320) / 256) * 60, + .dec_input_config_params_default =3D + sm8550_vdec_input_config_params_default, + .dec_input_config_params_default_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_params_default), + .dec_input_config_params_hevc =3D + sm8550_vdec_input_config_param_hevc, + .dec_input_config_params_hevc_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), + .dec_input_config_params_vp9 =3D + sm8550_vdec_input_config_param_vp9, + .dec_input_config_params_vp9_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), + .dec_output_config_params =3D + sm8550_vdec_output_config_params, + .dec_output_config_params_size =3D + ARRAY_SIZE(sm8550_vdec_output_config_params), + + .enc_input_config_params =3D + sm8550_venc_input_config_params, + .enc_input_config_params_size =3D + ARRAY_SIZE(sm8550_venc_input_config_params), + .enc_output_config_params =3D + sm8550_venc_output_config_params, + .enc_output_config_params_size =3D + ARRAY_SIZE(sm8550_venc_output_config_params), + + .dec_input_prop =3D sm8550_vdec_subscribe_input_properties, + .dec_input_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_input_propertie= s), + .dec_output_prop_avc =3D sm8550_vdec_subscribe_output_properties_avc, + .dec_output_prop_avc_size =3D + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), + .dec_output_prop_hevc =3D sm8550_vdec_subscribe_output_properties_hevc, + .dec_output_prop_hevc_size =3D + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), + .dec_output_prop_vp9 =3D sm8550_vdec_subscribe_output_properties_vp9, + .dec_output_prop_vp9_size =3D + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), + + .dec_ip_int_buf_tbl =3D sm8550_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), + .dec_op_int_buf_tbl =3D sm8550_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), + + .enc_op_int_buf_tbl =3D sm8550_enc_op_int_buf_tbl, + .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), +}; + const struct iris_platform_data sm8550_data =3D { .get_instance =3D iris_hfi_gen2_get_instance, .init_hfi_command_ops =3D iris_hfi_gen2_command_ops_init, diff --git a/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h b/d= rivers/media/platform/qcom/iris/iris_platform_kaanapali.h new file mode 100644 index 0000000000000000000000000000000000000000..ecfebc898e727ccadd2ea5d7d2d= 43fcba476b779 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __IRIS_PLATFORM_KAANAPALI_H__ +#define __IRIS_PLATFORM_KAANAPALI_H__ + +#include + +#define VIDEO_REGION_VM0_SECURE_NP_ID 1 +#define VIDEO_REGION_VM0_NONSECURE_NP_ID 5 + +static const char *const kaanapali_clk_reset_table[] =3D { + "bus0", + "bus1", + "core", + "vcodec0_core", +}; + +static const char *const kaanapali_pmdomain_table[] =3D { + "venus", + "vcodec0", + "vpp0", + "vpp1", + "apv", +}; + +static const struct platform_clk_data kaanapali_clk_table[] =3D { + { IRIS_AXI_CLK, "iface" }, + { IRIS_CTRL_CLK, "core" }, + { IRIS_HW_CLK, "vcodec0_core" }, + { IRIS_AXI1_CLK, "iface1" }, + { IRIS_CTRL_FREERUN_CLK, "core_freerun" }, + { IRIS_HW_FREERUN_CLK, "vcodec0_core_freerun" }, + { IRIS_BSE_HW_CLK, "vcodec_bse" }, + { IRIS_VPP0_HW_CLK, "vcodec_vpp0" }, + { IRIS_VPP1_HW_CLK, "vcodec_vpp1" }, + { IRIS_APV_HW_CLK, "vcodec_apv" }, +}; + +static const char *const kaanapali_opp_clk_table[] =3D { + "vcodec0_core", + "vcodec_apv", + "vcodec_bse", + "core", + NULL, +}; + +static struct tz_cp_config tz_cp_config_kaanapali[] =3D { + { + .cp_start =3D VIDEO_REGION_VM0_SECURE_NP_ID, + .cp_size =3D 0, + .cp_nonpixel_start =3D 0x01000000, + .cp_nonpixel_size =3D 0x24800000, + }, + { + .cp_start =3D VIDEO_REGION_VM0_NONSECURE_NP_ID, + .cp_size =3D 0, + .cp_nonpixel_start =3D 0x25800000, + .cp_nonpixel_size =3D 0xda400000, + }, +}; + +static struct iris_context_bank kaanapali_cb_data[] =3D { + { + .dev =3D NULL, + .name =3D "iris_bitstream", + .f_id =3D IRIS_BITSTREAM, + .region =3D IRIS_BITSTREAM_REGION, + }, + { + .dev =3D NULL, + .name =3D "iris_non_pixel", + .f_id =3D IRIS_NON_PIXEL, + .region =3D IRIS_NON_PIXEL_REGION, + }, + { + .dev =3D NULL, + .name =3D "iris_pixel", + .f_id =3D IRIS_PIXEL, + .region =3D IRIS_PIXEL_REGION, + }, +}; + +#endif /* __IRIS_PLATFORM_KAANAPALI_H__ */ diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index 557adb038328a75510591d91569819abc0b7b1c9..e30b159b42c75b288ef02624480= cd733f9cf6f50 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -400,6 +400,10 @@ static const struct dev_pm_ops iris_pm_ops =3D { }; =20 static const struct of_device_id iris_dt_match[] =3D { + { + .compatible =3D "qcom,kaanapali-iris", + .data =3D &kaanapali_data, + }, { .compatible =3D "qcom,qcs8300-iris", .data =3D &qcs8300_data, --=20 2.34.1