From nobody Sun Apr 5 13:12:03 2026 Received: from mail-pg1-f169.google.com (mail-pg1-f169.google.com [209.85.215.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C350643900F for ; Fri, 27 Feb 2026 15:14:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772205297; cv=none; b=rrvMh++AmtQXxbKWUv3zBYr9+ynlU0ABAfuPNdDP+BWV17ceUwTKi/oXi5ckvRl+ZXbB4XwMDhYGJ/IrJFLclqxfLeTVFonyePhHDbpefu9qs9NJXUPgTH1RcJd8bpjCHWBLOhfn+9TC0rjgDjklXS/eLN5TDNwpgFnViJs5AVM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772205297; c=relaxed/simple; bh=Tnr5MVM54yT5olpBGIRL9iYHBO46LGWJbdN2YfWRz0g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=G8b1utGnRSANErx8yI/88n47qB06ruCwofJrarnlnsCN8jZJoCqaIMedSDZ+4jhUqke2O9SrKBHf3alwwStBRKvLauTjXR5LFKfS/jC1Cj5a/6iYeQn/eypp57gMsA4IgsDkLmnFOfxRVKCEzoBNcYXnseic07+LbEsZ5w1qUjM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=fl+wSgRl; arc=none smtp.client-ip=209.85.215.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="fl+wSgRl" Received: by mail-pg1-f169.google.com with SMTP id 41be03b00d2f7-c70f91776fcso851719a12.0 for ; Fri, 27 Feb 2026 07:14:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1772205296; x=1772810096; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=f4E6HXkvhuNIpYntCK6bZF0992wJwuTJEJOmXq3XUUw=; b=fl+wSgRlI0fvKz/CbOFyIR7tcLronpU3C8hiUCvddIpJkTWKqGVw9VOA8WBFMONZyO IqFUWiE3ZWhtsK74WZU2DAwcG2aes93jrMfVZsLvHEt3dg5q6SmOUJLhoLnekECrG1Pn JGjCyRHAJFbXcCMvO9DWi18yUGjDOX/iY+TmN6hrytSN0JVaZuGCsuYACPqItQFe8FVo h03CVUFALpsYS1FuIjBVt/2x6WIDjmKs8oNWtplX2hI66JBTG/IQagbUwbutJoCj+7xT 6DKXw5dsp9k3YLcj02YCSrxagHK3upjuIdafARacrw61QXYVjBd5MIla/K5q7Uh7Z2h/ XJuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772205296; x=1772810096; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=f4E6HXkvhuNIpYntCK6bZF0992wJwuTJEJOmXq3XUUw=; b=deocVJl5GyWaGgBQDi7G7y0/7MVKmGCJhWZfJCVSE8rPXJ/WkaK7cXuTMzZppjB3DH s+HZaCZJJS6BXqbVt54iwIjaRWpBen0qD1v+WXkXUbBy7N7Rusr8cVWtFfDQ43TdltbX jYYBgH8Fp4IDIFT0ScSqKFsPNK+ymiWHwtp0veZXxF4xOMYrLe6prgL7N0Z5mvq08JRl NEkByKf/03C5cCEljJsQKP8FqPIpC6EYZt43zqK+GnNiilkU2vu7U4DOLL/V6xXseYbo guJQKqETn4UKnLbm13anbhbLBRX2L9M0f2ZGFBX9au+wwhMdCgQ2xQ6kkxCnCFDXkgX9 qyBA== X-Forwarded-Encrypted: i=1; AJvYcCVM4yx+624W42k4u6/Ifoz5alxSFOba55CD4k2mC6BtuKIcgp5+K/51lIl17cOFft1WsOSGVs925tks5Sw=@vger.kernel.org X-Gm-Message-State: AOJu0YyU7/qiMR8y5/BGhLl/KMwp4/TAF+4VUO8U3lldAmnRRYcAu7G3 4oidvojYklaj0z6CEyFXufyUVi/L8FM1kyTH0GoVh4PVQ20TfhK8XleB X-Gm-Gg: ATEYQzzhI0/606zOTOnlug86Ebh/fnDabRCgwXFHHtOzuelBY+BwVm2g3D8H/gNH95X UplDpzA243Y+PzA3xZMiQ+/1i53l2j3YZfU1fxW9hYYwFI2In10j8WNYWZgamGjEWraTXD0oqVt BcKV5gsxbHCbKeLEyHRcwx2moICZeCJNjVFcl/HvgnqwTI/rrAxOOtVMYV0Ch+aInXKlEb7UzHs PJ4ur6WlVW6w/3U2B85pgdZLpkoSa1+crvfa4Cs3Kltt/G7/fLEH6CaB2/7ISzRKoBCfJ4Nx7WS HvQZNF3yWlfFf2W5+xmSAxy5Z4qEPrnnp3ha1NrU9z0OjvqmyeMDEO1ild+G6FRr3DgPmZGlykM U4R8YyNDrvG1WH5mClesOTihbi4YfGidJktiRMn6cIBAMcZNAt+R3bn3ntD4wMkjEqrXBdyhJWf 3qzwndng/58wH7OKF50dbfBECLgskodKOOHRtWm1WvbliptLFQqMS0NyJmtg8= X-Received: by 2002:a17:90a:da85:b0:32e:3829:a71c with SMTP id 98e67ed59e1d1-35965c93b31mr3629448a91.16.1772205295979; Fri, 27 Feb 2026 07:14:55 -0800 (PST) Received: from LAPTOP-872M7T80.localdomain ([122.168.69.160]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-3593dcc9c37sm5485848a91.8.2026.02.27.07.14.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Feb 2026 07:14:55 -0800 (PST) From: Akhila YS Date: Fri, 27 Feb 2026 15:14:33 +0000 Subject: [PATCH v4 3/5] dt-bindings: arm: microchip,sam9x60-pit64b : convert to DT schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260227-arm-microchip-v4-3-7e2ae1c5b5d6@gmail.com> References: <20260227-arm-microchip-v4-0-7e2ae1c5b5d6@gmail.com> In-Reply-To: <20260227-arm-microchip-v4-0-7e2ae1c5b5d6@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Alexandre Belloni Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Akhila YS , Conor Dooley X-Mailer: b4 0.14.3 Convert Atmel Periodic interval timer of 64bit (PIT64b) binding to YAML format. Changes during conversion: - Add missing compatible "microchip,sama7g5-pit64b" along with a fallback compatible "microchip,sam9x60-pit64b". Acked-by: Conor Dooley Signed-off-by: Akhila YS Reviewed-by: Claudiu Beznea --- .../devicetree/bindings/arm/atmel-sysregs.txt | 8 --- .../bindings/arm/microchip,sam9x60-pit64b.yaml | 68 ++++++++++++++++++= ++++ 2 files changed, 68 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Docu= mentation/devicetree/bindings/arm/atmel-sysregs.txt index 70059f66f2b4..d0561f7f465c 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -1,13 +1,5 @@ Atmel system registers =20 -PIT64B Timer required properties: -- compatible: Should be "microchip,sam9x60-pit64b" or - "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b" - "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt for PIT64B timer -- clocks: Should contain the available clock sources for PIT64B timer. - System Timer (ST) required properties: - compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd" - reg: Should contain registers location and length diff --git a/Documentation/devicetree/bindings/arm/microchip,sam9x60-pit64b= .yaml b/Documentation/devicetree/bindings/arm/microchip,sam9x60-pit64b.yaml new file mode 100644 index 000000000000..f00ac7e858d9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/microchip,sam9x60-pit64b.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/microchip,sam9x60-pit64b.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIT64B 64-bit Periodic Interval Timer + +maintainers: + - Nicolas Ferre + - Claudiu Beznea + +description: + The Microchip PIT64B is a 64-bit periodic interval timer used in + several modern Microchip ARM SoCs including SAM9X60, SAM9X7 and + SAMA7D65 families. It provides extended timing range, flexible + clock selection and supports both periodic and one-shot interrupt + generation modes. + +properties: + compatible: + oneOf: + - const: microchip,sam9x60-pit64b + - items: + - enum: + - microchip,sama7d65-pit64b + - microchip,sama7g5-pit64b + - microchip,sam9x7-pit64b + - const: microchip,sam9x60-pit64b + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + items: + enum: + - pclk + - gclk + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + #include + timer@f0028000 { + compatible =3D "microchip,sama7g5-pit64b", "microchip,sam9x60-pit6= 4b"; + reg =3D <0xf0028000 0x100>; + interrupts =3D <37 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; + clock-names =3D "pclk", "gclk"; + }; +... --=20 2.43.0