From nobody Tue Apr 7 18:45:27 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6FF0466B51; Thu, 26 Feb 2026 23:14:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772147683; cv=none; b=MvAVL8bMcGzfeHzClXwSgVMkv3Ws7DDUhFcavxCbUSZU52Dc/pC1XXiYqaEg1LD89wEv3EZqQdSGWCn5dyrklpfnnCkwD9/lohfgF2CHg4xOPnzDGUzxo7JCJBTMQpHOCxJ8QXA/OugCMygAc+4WRsMqVqk8AZRzhI+pFEpxrwc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772147683; c=relaxed/simple; bh=0wccGccUIHlMOJan6W01TS0bcwTgP8WDIqAfLIWzko4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=S/l3fRa4mKB0FdZeuUOAeSGC9t7QgmsveP/68HUyIbP7VQHU8N1lOyVVRjokoEHag2lWDsXcYjDkKZpZqUhunXTZoF5kjVDb/U2DFEWUbSKQ8q3vDNrA3RzPNcNRD422gtN2EiwkToUkGQpopy3eCqyzt3i2WV1N/o9QIotce70= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=dJt26D0k; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="dJt26D0k" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1772147680; x=1803683680; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0wccGccUIHlMOJan6W01TS0bcwTgP8WDIqAfLIWzko4=; b=dJt26D0kbQbXgrX12+vXbTRinQ1Gvy2yAiDKQ+BFMGSFpui3DZ42oRom p9H7Epx438BuP3UzPuGHfcX24KOyU7/JXuNsKOgQDruLStoxTt/btY1CY vT9TR4Yky4o5kJqJThSR05lf6eXFZcHddfP94BRbY0FoKVE7oyCmY/M6k H4mnbZtnEOW7dsyu8Qh7AewKD5rJErMG0G45FpFKz2Ruce38QNFkm0LMQ Y8MHzmn8F9P/Th9MkInIliHKeXLVv49Mc13jikww1xoRHziHv0VHqCGTJ QUVHgLqRQiwoQJIfx4mmgaXbCupJGvKfLJmOrreKO+AKnXDqglzwxAmiZ w==; X-CSE-ConnectionGUID: ijHUrhh4Qcafi2zynApBLA== X-CSE-MsgGUID: sKeW6b0rT9SFL3Czlew+7A== X-IronPort-AV: E=McAfee;i="6800,10657,11713"; a="72928315" X-IronPort-AV: E=Sophos;i="6.21,313,1763452800"; d="scan'208";a="72928315" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Feb 2026 15:14:38 -0800 X-CSE-ConnectionGUID: vMow1kGeQyiVykSh2ppfjw== X-CSE-MsgGUID: J6gFeWN8TKeYWCyG6HHVVQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,313,1763452800"; d="scan'208";a="221340139" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.43]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Feb 2026 15:14:38 -0800 From: Zide Chen To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Dapeng Mi , Falcon Thomas , Xudong Hao Subject: [PATCH 2/3] KVM: x86/pmu: Support Intel fixed counter 3 on mediated vPMU Date: Thu, 26 Feb 2026 15:06:05 -0800 Message-ID: <20260226230606.146532-3-zide.chen@intel.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260226230606.146532-1-zide.chen@intel.com> References: <20260226230606.146532-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Dapeng Mi Starting with Ice Lake, Intel introduces fixed counter 3, which counts TOPDOWN.SLOTS - the number of available slots for an unhalted logical processor. It serves as the denominator for top-level metrics in the Top-down Microarchitecture Analysis method. Emulating this counter on legacy vPMU would require introducing a new generic perf encoding for the Intel-specific TOPDOWN.SLOTS event in order to call perf_get_hw_event_config(). This is undesirable as it would pollute the generic perf event encoding. Moreover, KVM does not intend to emulate IA32_PERF_METRICS in the legacy vPMU model, and without IA32_PERF_METRICS, emulating this counter has little practical value. Therefore, expose fixed counter 3 to guests only when mediated vPMU is enabled. Signed-off-by: Dapeng Mi Co-developed-by: Zide Chen Signed-off-by: Zide Chen --- arch/x86/include/asm/kvm_host.h | 2 +- arch/x86/kvm/pmu.c | 4 ++++ arch/x86/kvm/x86.c | 4 ++-- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index ff07c45e3c73..4666b2c7988f 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -555,7 +555,7 @@ struct kvm_pmc { #define KVM_MAX_NR_GP_COUNTERS KVM_MAX(KVM_MAX_NR_INTEL_GP_COUNTERS, \ KVM_MAX_NR_AMD_GP_COUNTERS) =20 -#define KVM_MAX_NR_INTEL_FIXED_COUNTERS 3 +#define KVM_MAX_NR_INTEL_FIXED_COUNTERS 4 #define KVM_MAX_NR_AMD_FIXED_COUNTERS 0 #define KVM_MAX_NR_FIXED_COUNTERS KVM_MAX(KVM_MAX_NR_INTEL_FIXED_COUNTERS,= \ KVM_MAX_NR_AMD_FIXED_COUNTERS) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index bd6b785cf261..ee49395bfb82 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -148,6 +148,10 @@ void kvm_init_pmu_capability(struct kvm_pmu_ops *pmu_o= ps) } =20 memcpy(&kvm_pmu_cap, &kvm_host_pmu, sizeof(kvm_host_pmu)); + + if (!enable_mediated_pmu && kvm_pmu_cap.num_counters_fixed > 3) + kvm_pmu_cap.num_counters_fixed =3D 3; + kvm_pmu_cap.version =3D min(kvm_pmu_cap.version, 2); kvm_pmu_cap.num_counters_gp =3D min(kvm_pmu_cap.num_counters_gp, pmu_ops->MAX_NR_GP_COUNTERS); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 3fb64905d190..2ab7a4958620 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -355,7 +355,7 @@ static const u32 msrs_to_save_base[] =3D { =20 static const u32 msrs_to_save_pmu[] =3D { MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, - MSR_ARCH_PERFMON_FIXED_CTR0 + 2, + MSR_ARCH_PERFMON_FIXED_CTR2, MSR_ARCH_PERFMON_FIXED_CTR3, MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, MSR_CORE_PERF_GLOBAL_CTRL, MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG, @@ -7738,7 +7738,7 @@ static void kvm_init_msr_lists(void) { unsigned i; =20 - BUILD_BUG_ON_MSG(KVM_MAX_NR_FIXED_COUNTERS !=3D 3, + BUILD_BUG_ON_MSG(KVM_MAX_NR_FIXED_COUNTERS !=3D 4, "Please update the fixed PMCs in msrs_to_save_pmu[]"); =20 num_msrs_to_save =3D 0; --=20 2.53.0