From nobody Tue Apr 7 17:13:27 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80770399029; Thu, 26 Feb 2026 23:14:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772147682; cv=none; b=PjecIDOGwdY7xgyptcmJR6IVICZHSyxuQPjEejacCamzzhFCesuJPCG93An844Y6yGi63TZyuVtS7y6fzARX1yCvAVYeG3kp1xhGwjtia2KHp0ddmrDeNL42NqmuOlvjzUYvUvHlqnZ36zb7PTObuJy3Yh83rx7tniI3OCfD6KQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772147682; c=relaxed/simple; bh=PrNmpgIk9ri24U7Dkk7eSCxhGilPGCS5C5ipQizqCuE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Lb8zddP0J9DduD+LeSKDe6cOzCyZRGLl8f3DN7a1VKtF58PfUU6Dv3+NbqLd1HV7nS8b2pnVKpjyaK2nu6LY7wSNYYSq3Uaq9jaiKHksGaJR3ajgEnuovj9TIU2qhahwFLjKTb9EFve2MdVbf9wSU2TRWyi2uFn/zhaw8vEXiZg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Ig4AWrdN; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Ig4AWrdN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1772147680; x=1803683680; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PrNmpgIk9ri24U7Dkk7eSCxhGilPGCS5C5ipQizqCuE=; b=Ig4AWrdNi1RZroAY0QrVBCiwgkPyFgfahXofBkYrTJcsTnv+3niW8MKp WzTYcmKfVvyTMZ7iUbsx/kW1rYmnAbujsH/rUJCJ+wcQPD1Cd/cRfn8d1 iJWBm5uiHAdKHPIhUcav0LhzhuTd98H5h26H/+TWqFdBUKdFO+QZu1ESQ 78sRXYAxyNBHYtSm8ft1Eumx4MRm+6stO84h6ez3HOUirDehE5UUW4T4/ mnHIcE2+bKciNFQZV7i4zyDjKZRRhV13F0V5d7lkKfs1LvzyvAp1b9TFE osufVUkzsZswr/TI4OcApKsc2SwLd+9dGxQGt2mw2moYpk5uIwYVZsRsN Q==; X-CSE-ConnectionGUID: 82nz7HIhSRK5LWPtWUMgPw== X-CSE-MsgGUID: gUb8MpOXSa2tHtfOfeFmdQ== X-IronPort-AV: E=McAfee;i="6800,10657,11713"; a="72928310" X-IronPort-AV: E=Sophos;i="6.21,313,1763452800"; d="scan'208";a="72928310" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Feb 2026 15:14:38 -0800 X-CSE-ConnectionGUID: 819KQjRZTSW9ILNUUuWuEg== X-CSE-MsgGUID: pMkwzEE+RB29pn6fugnVcQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,313,1763452800"; d="scan'208";a="221340136" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.43]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Feb 2026 15:14:38 -0800 From: Zide Chen To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Dapeng Mi , Falcon Thomas , Xudong Hao Subject: [PATCH 1/3] KVM: x86/pmu: Do not map fixed counters >= 3 to generic perf events Date: Thu, 26 Feb 2026 15:06:04 -0800 Message-ID: <20260226230606.146532-2-zide.chen@intel.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260226230606.146532-1-zide.chen@intel.com> References: <20260226230606.146532-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Only fixed counters 0..2 have matching generic cross-platform hardware perf events (INSTRUCTIONS, CPU_CYCLES, REF_CPU_CYCLES). Therefore, perf_get_hw_event_config() is only applicable to these counters. KVM does not intend to emulate fixed counters >=3D 3 on legacy (non-mediated) vPMU, while for mediated vPMU, KVM does not care what the fixed counter event mappings are. Therefore, return 0 for their eventsel. Also remove __always_inline as BUILD_BUG_ON() is no longer needed. Signed-off-by: Zide Chen --- arch/x86/kvm/vmx/pmu_intel.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 27eb76e6b6a0..4bfd16a9e6c7 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -454,28 +454,30 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, s= truct msr_data *msr_info) * different perf_event is already utilizing the requested counter, but th= e end * result is the same (ignoring the fact that using a general purpose coun= ter * will likely exacerbate counter contention). - * - * Forcibly inlined to allow asserting on @index at build time, and there = should - * never be more than one user. */ -static __always_inline u64 intel_get_fixed_pmc_eventsel(unsigned int index) +static u64 intel_get_fixed_pmc_eventsel(unsigned int index) { const enum perf_hw_id fixed_pmc_perf_ids[] =3D { [0] =3D PERF_COUNT_HW_INSTRUCTIONS, [1] =3D PERF_COUNT_HW_CPU_CYCLES, [2] =3D PERF_COUNT_HW_REF_CPU_CYCLES, }; - u64 eventsel; - - BUILD_BUG_ON(ARRAY_SIZE(fixed_pmc_perf_ids) !=3D KVM_MAX_NR_INTEL_FIXED_C= OUNTERS); - BUILD_BUG_ON(index >=3D KVM_MAX_NR_INTEL_FIXED_COUNTERS); + u64 eventsel =3D 0; =20 /* - * Yell if perf reports support for a fixed counter but perf doesn't - * have a known encoding for the associated general purpose event. + * Fixed counters 3 and above don't have corresponding generic hardware + * perf event, and KVM does not intend to emulate them on non-mediated + * vPMU. */ - eventsel =3D perf_get_hw_event_config(fixed_pmc_perf_ids[index]); - WARN_ON_ONCE(!eventsel && index < kvm_pmu_cap.num_counters_fixed); + if (index < 3) { + /* + * Yell if perf reports support for a fixed counter but perf + * doesn't have a known encoding for the associated general + * purpose event. + */ + eventsel =3D perf_get_hw_event_config(fixed_pmc_perf_ids[index]); + WARN_ON_ONCE(!eventsel && index < kvm_pmu_cap.num_counters_fixed); + } return eventsel; } =20 --=20 2.53.0 From nobody Tue Apr 7 17:13:27 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6FF0466B51; Thu, 26 Feb 2026 23:14:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772147683; cv=none; b=MvAVL8bMcGzfeHzClXwSgVMkv3Ws7DDUhFcavxCbUSZU52Dc/pC1XXiYqaEg1LD89wEv3EZqQdSGWCn5dyrklpfnnCkwD9/lohfgF2CHg4xOPnzDGUzxo7JCJBTMQpHOCxJ8QXA/OugCMygAc+4WRsMqVqk8AZRzhI+pFEpxrwc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772147683; c=relaxed/simple; bh=0wccGccUIHlMOJan6W01TS0bcwTgP8WDIqAfLIWzko4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=S/l3fRa4mKB0FdZeuUOAeSGC9t7QgmsveP/68HUyIbP7VQHU8N1lOyVVRjokoEHag2lWDsXcYjDkKZpZqUhunXTZoF5kjVDb/U2DFEWUbSKQ8q3vDNrA3RzPNcNRD422gtN2EiwkToUkGQpopy3eCqyzt3i2WV1N/o9QIotce70= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=dJt26D0k; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="dJt26D0k" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1772147680; x=1803683680; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0wccGccUIHlMOJan6W01TS0bcwTgP8WDIqAfLIWzko4=; b=dJt26D0kbQbXgrX12+vXbTRinQ1Gvy2yAiDKQ+BFMGSFpui3DZ42oRom p9H7Epx438BuP3UzPuGHfcX24KOyU7/JXuNsKOgQDruLStoxTt/btY1CY vT9TR4Yky4o5kJqJThSR05lf6eXFZcHddfP94BRbY0FoKVE7oyCmY/M6k H4mnbZtnEOW7dsyu8Qh7AewKD5rJErMG0G45FpFKz2Ruce38QNFkm0LMQ Y8MHzmn8F9P/Th9MkInIliHKeXLVv49Mc13jikww1xoRHziHv0VHqCGTJ QUVHgLqRQiwoQJIfx4mmgaXbCupJGvKfLJmOrreKO+AKnXDqglzwxAmiZ w==; X-CSE-ConnectionGUID: ijHUrhh4Qcafi2zynApBLA== X-CSE-MsgGUID: sKeW6b0rT9SFL3Czlew+7A== X-IronPort-AV: E=McAfee;i="6800,10657,11713"; a="72928315" X-IronPort-AV: E=Sophos;i="6.21,313,1763452800"; d="scan'208";a="72928315" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Feb 2026 15:14:38 -0800 X-CSE-ConnectionGUID: vMow1kGeQyiVykSh2ppfjw== X-CSE-MsgGUID: J6gFeWN8TKeYWCyG6HHVVQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,313,1763452800"; d="scan'208";a="221340139" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.43]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Feb 2026 15:14:38 -0800 From: Zide Chen To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Dapeng Mi , Falcon Thomas , Xudong Hao Subject: [PATCH 2/3] KVM: x86/pmu: Support Intel fixed counter 3 on mediated vPMU Date: Thu, 26 Feb 2026 15:06:05 -0800 Message-ID: <20260226230606.146532-3-zide.chen@intel.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260226230606.146532-1-zide.chen@intel.com> References: <20260226230606.146532-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Dapeng Mi Starting with Ice Lake, Intel introduces fixed counter 3, which counts TOPDOWN.SLOTS - the number of available slots for an unhalted logical processor. It serves as the denominator for top-level metrics in the Top-down Microarchitecture Analysis method. Emulating this counter on legacy vPMU would require introducing a new generic perf encoding for the Intel-specific TOPDOWN.SLOTS event in order to call perf_get_hw_event_config(). This is undesirable as it would pollute the generic perf event encoding. Moreover, KVM does not intend to emulate IA32_PERF_METRICS in the legacy vPMU model, and without IA32_PERF_METRICS, emulating this counter has little practical value. Therefore, expose fixed counter 3 to guests only when mediated vPMU is enabled. Signed-off-by: Dapeng Mi Co-developed-by: Zide Chen Signed-off-by: Zide Chen --- arch/x86/include/asm/kvm_host.h | 2 +- arch/x86/kvm/pmu.c | 4 ++++ arch/x86/kvm/x86.c | 4 ++-- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index ff07c45e3c73..4666b2c7988f 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -555,7 +555,7 @@ struct kvm_pmc { #define KVM_MAX_NR_GP_COUNTERS KVM_MAX(KVM_MAX_NR_INTEL_GP_COUNTERS, \ KVM_MAX_NR_AMD_GP_COUNTERS) =20 -#define KVM_MAX_NR_INTEL_FIXED_COUNTERS 3 +#define KVM_MAX_NR_INTEL_FIXED_COUNTERS 4 #define KVM_MAX_NR_AMD_FIXED_COUNTERS 0 #define KVM_MAX_NR_FIXED_COUNTERS KVM_MAX(KVM_MAX_NR_INTEL_FIXED_COUNTERS,= \ KVM_MAX_NR_AMD_FIXED_COUNTERS) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index bd6b785cf261..ee49395bfb82 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -148,6 +148,10 @@ void kvm_init_pmu_capability(struct kvm_pmu_ops *pmu_o= ps) } =20 memcpy(&kvm_pmu_cap, &kvm_host_pmu, sizeof(kvm_host_pmu)); + + if (!enable_mediated_pmu && kvm_pmu_cap.num_counters_fixed > 3) + kvm_pmu_cap.num_counters_fixed =3D 3; + kvm_pmu_cap.version =3D min(kvm_pmu_cap.version, 2); kvm_pmu_cap.num_counters_gp =3D min(kvm_pmu_cap.num_counters_gp, pmu_ops->MAX_NR_GP_COUNTERS); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 3fb64905d190..2ab7a4958620 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -355,7 +355,7 @@ static const u32 msrs_to_save_base[] =3D { =20 static const u32 msrs_to_save_pmu[] =3D { MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, - MSR_ARCH_PERFMON_FIXED_CTR0 + 2, + MSR_ARCH_PERFMON_FIXED_CTR2, MSR_ARCH_PERFMON_FIXED_CTR3, MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, MSR_CORE_PERF_GLOBAL_CTRL, MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG, @@ -7738,7 +7738,7 @@ static void kvm_init_msr_lists(void) { unsigned i; =20 - BUILD_BUG_ON_MSG(KVM_MAX_NR_FIXED_COUNTERS !=3D 3, + BUILD_BUG_ON_MSG(KVM_MAX_NR_FIXED_COUNTERS !=3D 4, "Please update the fixed PMCs in msrs_to_save_pmu[]"); =20 num_msrs_to_save =3D 0; --=20 2.53.0 From nobody Tue Apr 7 17:13:27 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E73F47AF50; Thu, 26 Feb 2026 23:14:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772147683; cv=none; b=YTyUv75DiOUQC6Y9RKyz3ACsLsq2lQjNtCMR2ITeOPL2+QO0384s/MSykL2uGrraG/QI3pYCKDx4a4OZIjwfU4ss8M4r/9Yt4Quo/QOKXrhEddxKQa17EGrzNruT2bD6sU2dPDa3Jd0b8jfr8MRQWOAqJtchA3s1ofUb4cRP0ks= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772147683; c=relaxed/simple; bh=Bkf9lgivbj9yHO0jtGEtBziWCxVqJEo3GXtfNuN9svE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ExtiQrvI970V+tx3eZ5rqkvE0EVYM5Lu0gDUq0o6uCCW2sbSF2KgmyIlZrqltDc4r/60LMrql/vgfEWq9fKWrlD+x2cAClm9zIh6JOlEUl8QrliooAl8/SY9s6mJRDyDa9gRKMZgTJCGbWVa17Cc+5QAxI5skMx9x36wpt4817w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=SOnYCMV+; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="SOnYCMV+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1772147682; x=1803683682; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Bkf9lgivbj9yHO0jtGEtBziWCxVqJEo3GXtfNuN9svE=; b=SOnYCMV+P39/TWLN19ijHP40XzUGcFcI4n59/21SrwKAAEjhnvjfQt0C gdRHdFsauhzXyeIvULO4rU0E5AGYBiLE+5cBLi0VpeI3Kpl5IoY4qilwK Bc2+9eGKkG+w7++4Lo3gjWvCplEeUsjh49kBpy2Md21O9V9aU3zyaUJKf whuXN8uTosmmx/fxsqaZbBUJPPwk2jtW+6vHcDT3MXKbeNtmY3eMEVfGs 3qBYc/cU8gpcEeW0J8RyMq983jvc5UVSm54ZRLp8LpGmuhwgKqNth+8l4 Fbo85bolFMSVSSX0xEc/u4XfpE5UT1kHdusG9n+uCjeZCvI5Fuk+Rf/Rp w==; X-CSE-ConnectionGUID: 4zuWwssRRuCav7ZHo9zAeQ== X-CSE-MsgGUID: oT9biQg7Qr2sKei29md/lA== X-IronPort-AV: E=McAfee;i="6800,10657,11713"; a="72928319" X-IronPort-AV: E=Sophos;i="6.21,313,1763452800"; d="scan'208";a="72928319" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Feb 2026 15:14:38 -0800 X-CSE-ConnectionGUID: 5wazMpc4SvSR3Y6UGFQ23Q== X-CSE-MsgGUID: OcWac/PIQAyduagoO0/59w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,313,1763452800"; d="scan'208";a="221340142" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.43]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Feb 2026 15:14:38 -0800 From: Zide Chen To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Dapeng Mi , Falcon Thomas , Xudong Hao Subject: [PATCH 3/3] KVM: x86/pmu: Support PERF_METRICS MSR in mediated vPMU Date: Thu, 26 Feb 2026 15:06:06 -0800 Message-ID: <20260226230606.146532-4-zide.chen@intel.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260226230606.146532-1-zide.chen@intel.com> References: <20260226230606.146532-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Dapeng Mi Bit 15 in IA32_PERF_CAPABILITIES indicates that the CPU provides built-in support for Topdown Microarchitecture Analysis (TMA) L1 metrics via the IA32_PERF_METRICS MSR. Expose this capability only when mediated vPMU is enabled, as emulating IA32_PERF_METRICS in the legacy vPMU model is impractical. Pass IA32_PERF_METRICS through to the guest only when mediated vPMU is enabled and bit 15 is set in guest IA32_PERF_CAPABILITIES is. Allow kvm_pmu_{get,set}_msr() to handle this MSR for host accesses. Save and restore this MSR on host/guest PMU context switches so that host PMU activity does not clobber the guest value, and guest state is not leaked into the host. Signed-off-by: Dapeng Mi Signed-off-by: Zide Chen --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/include/asm/msr-index.h | 1 + arch/x86/include/asm/perf_event.h | 1 + arch/x86/kvm/vmx/pmu_intel.c | 31 +++++++++++++++++++++++++++++++ arch/x86/kvm/vmx/pmu_intel.h | 5 +++++ arch/x86/kvm/vmx/vmx.c | 6 ++++++ arch/x86/kvm/x86.c | 6 +++++- 7 files changed, 50 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index 4666b2c7988f..bf817c613451 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -575,6 +575,7 @@ struct kvm_pmu { u64 global_status_rsvd; u64 reserved_bits; u64 raw_event_mask; + u64 perf_metrics; struct kvm_pmc gp_counters[KVM_MAX_NR_GP_COUNTERS]; struct kvm_pmc fixed_counters[KVM_MAX_NR_FIXED_COUNTERS]; =20 diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index da5275d8eda6..337667a7ad1b 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -331,6 +331,7 @@ #define PERF_CAP_PEBS_FORMAT 0xf00 #define PERF_CAP_FW_WRITES BIT_ULL(13) #define PERF_CAP_PEBS_BASELINE BIT_ULL(14) +#define PERF_CAP_PERF_METRICS BIT_ULL(15) #define PERF_CAP_PEBS_TIMING_INFO BIT_ULL(17) #define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE | \ diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index ff5acb8b199b..dfead3a34b74 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -445,6 +445,7 @@ static inline bool is_topdown_idx(int idx) #define GLOBAL_STATUS_ARCH_PEBS_THRESHOLD_BIT 54 #define GLOBAL_STATUS_ARCH_PEBS_THRESHOLD BIT_ULL(GLOBAL_STATUS_ARCH_PEBS_= THRESHOLD_BIT) #define GLOBAL_STATUS_PERF_METRICS_OVF_BIT 48 +#define GLOBAL_STATUS_PERF_METRICS_OVF BIT_ULL(GLOBAL_STATUS_PERF_METRICS= _OVF_BIT) =20 #define GLOBAL_CTRL_EN_PERF_METRICS BIT_ULL(48) /* diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 9da47cf2af63..61bb2086f94a 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -180,6 +180,8 @@ static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u= 32 msr) switch (msr) { case MSR_CORE_PERF_FIXED_CTR_CTRL: return kvm_pmu_has_perf_global_ctrl(pmu); + case MSR_PERF_METRICS: + return vcpu_has_perf_metrics(vcpu); case MSR_IA32_PEBS_ENABLE: ret =3D vcpu_get_perf_capabilities(vcpu) & PERF_CAP_PEBS_FORMAT; break; @@ -335,6 +337,10 @@ static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, st= ruct msr_data *msr_info) case MSR_CORE_PERF_FIXED_CTR_CTRL: msr_info->data =3D pmu->fixed_ctr_ctrl; break; + case MSR_PERF_METRICS: + WARN_ON(!msr_info->host_initiated); + msr_info->data =3D pmu->perf_metrics; + break; case MSR_IA32_PEBS_ENABLE: msr_info->data =3D pmu->pebs_enable; break; @@ -384,6 +390,10 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, st= ruct msr_data *msr_info) if (pmu->fixed_ctr_ctrl !=3D data) reprogram_fixed_counters(pmu, data); break; + case MSR_PERF_METRICS: + WARN_ON(!msr_info->host_initiated); + pmu->perf_metrics =3D data; + break; case MSR_IA32_PEBS_ENABLE: if (data & pmu->pebs_enable_rsvd) return 1; @@ -579,6 +589,11 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) pmu->global_status_rsvd &=3D ~MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI; =20 + if (perf_capabilities & PERF_CAP_PERF_METRICS) { + pmu->global_ctrl_rsvd &=3D ~GLOBAL_CTRL_EN_PERF_METRICS; + pmu->global_status_rsvd &=3D ~GLOBAL_STATUS_PERF_METRICS_OVF; + } + if (perf_capabilities & PERF_CAP_PEBS_FORMAT) { if (perf_capabilities & PERF_CAP_PEBS_BASELINE) { pmu->pebs_enable_rsvd =3D counter_rsvd; @@ -622,6 +637,9 @@ static void intel_pmu_init(struct kvm_vcpu *vcpu) =20 static void intel_pmu_reset(struct kvm_vcpu *vcpu) { + struct kvm_pmu *pmu =3D vcpu_to_pmu(vcpu); + + pmu->perf_metrics =3D 0; intel_pmu_release_guest_lbr_event(vcpu); } =20 @@ -793,6 +811,13 @@ static void intel_mediated_pmu_load(struct kvm_vcpu *v= cpu) struct kvm_pmu *pmu =3D vcpu_to_pmu(vcpu); u64 global_status, toggle; =20 + /* + * PERF_METRICS MSR must be restored closely after fixed counter 3 + * (kvm_pmu_load_guest_pmcs()). + */ + if (vcpu_has_perf_metrics(vcpu)) + wrmsrq(MSR_PERF_METRICS, pmu->perf_metrics); + rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, global_status); toggle =3D pmu->global_status ^ global_status; if (global_status & toggle) @@ -821,6 +846,12 @@ static void intel_mediated_pmu_put(struct kvm_vcpu *vc= pu) */ if (pmu->fixed_ctr_ctrl_hw) wrmsrq(MSR_CORE_PERF_FIXED_CTR_CTRL, 0); + + if (vcpu_has_perf_metrics(vcpu)) { + pmu->perf_metrics =3D rdpmc(INTEL_PMC_FIXED_RDPMC_METRICS); + if (pmu->perf_metrics) + wrmsrq(MSR_PERF_METRICS, 0); + } } =20 struct kvm_pmu_ops intel_pmu_ops __initdata =3D { diff --git a/arch/x86/kvm/vmx/pmu_intel.h b/arch/x86/kvm/vmx/pmu_intel.h index 5d9357640aa1..2ec547223b09 100644 --- a/arch/x86/kvm/vmx/pmu_intel.h +++ b/arch/x86/kvm/vmx/pmu_intel.h @@ -40,4 +40,9 @@ struct lbr_desc { =20 extern struct x86_pmu_lbr vmx_lbr_caps; =20 +static inline bool vcpu_has_perf_metrics(struct kvm_vcpu *vcpu) +{ + return !!(vcpu_get_perf_capabilities(vcpu) & PERF_CAP_PERF_METRICS); +} + #endif /* __KVM_X86_VMX_PMU_INTEL_H */ diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 967b58a8ab9d..4ade1394460a 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -4338,6 +4338,9 @@ static void vmx_recalc_pmu_msr_intercepts(struct kvm_= vcpu *vcpu) MSR_TYPE_RW, intercept); vmx_set_intercept_for_msr(vcpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, MSR_TYPE_RW, intercept); + + vmx_set_intercept_for_msr(vcpu, MSR_PERF_METRICS, MSR_TYPE_RW, + !vcpu_has_perf_metrics(vcpu)); } =20 static void vmx_recalc_msr_intercepts(struct kvm_vcpu *vcpu) @@ -8183,6 +8186,9 @@ static __init u64 vmx_get_perf_capabilities(void) perf_cap &=3D ~PERF_CAP_PEBS_BASELINE; } =20 + if (enable_mediated_pmu) + perf_cap |=3D host_perf_cap & PERF_CAP_PERF_METRICS; + return perf_cap; } =20 diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 2ab7a4958620..4d0e38303aa5 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -357,7 +357,7 @@ static const u32 msrs_to_save_pmu[] =3D { MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, MSR_ARCH_PERFMON_FIXED_CTR2, MSR_ARCH_PERFMON_FIXED_CTR3, MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, - MSR_CORE_PERF_GLOBAL_CTRL, + MSR_CORE_PERF_GLOBAL_CTRL, MSR_PERF_METRICS, MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG, =20 /* This part of MSRs should match KVM_MAX_NR_INTEL_GP_COUNTERS. */ @@ -7675,6 +7675,10 @@ static void kvm_probe_msr_to_save(u32 msr_index) intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)) return; break; + case MSR_PERF_METRICS: + if (!(kvm_caps.supported_perf_cap & PERF_CAP_PERF_METRICS)) + return; + break; case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + KVM_MAX_NR_GP_COUNTERS - 1: if (msr_index - MSR_ARCH_PERFMON_PERFCTR0 >=3D --=20 2.53.0