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Miller" CC: Manorit Chawdhry , Kamlesh Gurudasani , Shiva Tripathi , Kavitha Malarvizhi , Vishal Mahaveer , Praneeth Bajjuri , , Subject: [PATCH v10 1/3] crypto: ti - Add support for AES-CTR in DTHEv2 driver Date: Thu, 26 Feb 2026 18:24:39 +0530 Message-ID: <20260226125441.3559664-2-t-pratham@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260226125441.3559664-1-t-pratham@ti.com> References: <20260226125441.3559664-1-t-pratham@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A102:EE_|DM4PR10MB7528:EE_ X-MS-Office365-Filtering-Correlation-Id: 3e573840-3b95-4443-11f0-08de75366562 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|34020700016|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: O+0xYEW/81NrnyGoB8mq8xIOAi7DPNQiKBQ1k11MOMJZ0EYZMkx/ephXGx2/58AfJqSr5MdK81/GwhYXZ0M2atjEifsmZIwSWj7/ilYdFhMsv9Dgkju3byMeQLKSKQPueNn0afdsppAWCII/hGscuwg6mUc33ySEN5Xnaqvi1V1UAsIK2rRzNTBs/Ys3nPIFeBeYRmS7xq/Vivad53fO3mEpa/L4yXYtz7jHnS0LfzDhKp+55wtTcHjGvMFD3NQF0/aQY7jA2gvppz3ZM4EA9ri2IzQFsvO3U3tF26INmlCYL6HLz3qBqVWhsi2NV6SthRiVhAw27cSehEeKG4ByHU0fQIvUx+UUihXuoEChk8XU4K1zNKQtj05pUTMJwShdZV4GsGITj5oL1S2NORHP12Ph7lNpqPWvKm1PRo2XjBYv/lVpHBwIzL6JQQUT7fgRXq+tn6fjsa9irACJpoeuDRTGBcACEGVxefsKsVbx/9SnITKd+3v8W3OuKRBIpY/7MXmhB1vNP3BxyeUqS+uypjFuKmunRuMTVcM2xLZq8qoseAnLptWc/4HzImmHzyCC8WtxKudzZN4oiM+2Ve9RwptE+x4MHRbBTpOaETyYQFwuIPsymNmEmJ7astrFuZ3LJYpVcuG92eaM8R65jGQsOV1yiIkoLXmZ71j29/a/3vCfM8MotEH9/w6m5jjdqLIGc7Qfe9SEyq2jz5MYSYVrymtNW/yMRluew5Tmn7IXsF7peDPXftaz7iQRIvUYB7ThYPXa4WkWQK2kr52IpTpIuEWGLmQ35mtdN/IA/2Yl8jYScfzzbVMJUWmeLOuBFmNYK+oSLw+zDtVJRImOKzJOVw== X-Forefront-Antispam-Report: CIP:198.47.21.195;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:flwvzet201.ext.ti.com;PTR:ErrorRetry;CAT:NONE;SFS:(13230040)(34020700016)(36860700013)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: PrtYcirwf0PXCsw28bmd8VDeLvqBnliN29NYZnbP5bOF8zeTyuNrSksh8+r6wDkplnuie0KekXsmhTO/LFnwJgsZOYkhSehF5E58BWc2Q4Ambqffg0S/cfvBbLqsClC03S5M8M4fVZBP3KYb6VaCEzgAYXsGey/lwFQIIyQXiqjq/B4BpCDcnDYMpA/ETrS6RdmVBvzWFPHmRXnpHzylGXvBAtJvh0ng2oExLeRye2vHyKz7mb5QFoGq8KEN38ip8m5s0xA7tIBvbmMEfY6bjtUMdNVB4J49pKVywTfVFAd5IYoF/xL0Gwgx7Tz4xFp730oYg5t6tN9eK7Oy6u80hIJ3/1QyvoONv5rvT4kf8AXlXTopZvd/Uv7IRlg4uRTltX3VhtP9OAPA5e02brRi3Yn8jkAwb9RhU/PGjF6nayiPO5AJdRFqpC8Znsh0S3wo X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 12:56:02.1581 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3e573840-3b95-4443-11f0-08de75366562 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.195];Helo=[flwvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A102.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR10MB7528 Content-Type: text/plain; charset="utf-8" Add support for CTR mode of operation for AES algorithm in the AES Engine of the DTHEv2 hardware cryptographic engine. Signed-off-by: T Pratham --- drivers/crypto/ti/Kconfig | 1 + drivers/crypto/ti/dthev2-aes.c | 173 ++++++++++++++++++++++++------ drivers/crypto/ti/dthev2-common.c | 19 ++++ drivers/crypto/ti/dthev2-common.h | 17 +++ 4 files changed, 180 insertions(+), 30 deletions(-) diff --git a/drivers/crypto/ti/Kconfig b/drivers/crypto/ti/Kconfig index a3692ceec49bc..6027e12de279d 100644 --- a/drivers/crypto/ti/Kconfig +++ b/drivers/crypto/ti/Kconfig @@ -6,6 +6,7 @@ config CRYPTO_DEV_TI_DTHEV2 select CRYPTO_SKCIPHER select CRYPTO_ECB select CRYPTO_CBC + select CRYPTO_CTR select CRYPTO_XTS help This enables support for the TI DTHE V2 hw cryptography engine diff --git a/drivers/crypto/ti/dthev2-aes.c b/drivers/crypto/ti/dthev2-aes.c index 156729ccc50ec..bf7d4dcb4cd7d 100644 --- a/drivers/crypto/ti/dthev2-aes.c +++ b/drivers/crypto/ti/dthev2-aes.c @@ -63,6 +63,7 @@ enum aes_ctrl_mode_masks { AES_CTRL_ECB_MASK =3D 0x00, AES_CTRL_CBC_MASK =3D BIT(5), + AES_CTRL_CTR_MASK =3D BIT(6), AES_CTRL_XTS_MASK =3D BIT(12) | BIT(11), }; =20 @@ -74,6 +75,8 @@ enum aes_ctrl_mode_masks { #define DTHE_AES_CTRL_KEYSIZE_24B BIT(4) #define DTHE_AES_CTRL_KEYSIZE_32B (BIT(3) | BIT(4)) =20 +#define DTHE_AES_CTRL_CTR_WIDTH_128B (BIT(7) | BIT(8)) + #define DTHE_AES_CTRL_SAVE_CTX_SET BIT(29) =20 #define DTHE_AES_CTRL_OUTPUT_READY BIT_MASK(0) @@ -100,25 +103,27 @@ static int dthe_cipher_init_tfm(struct crypto_skciphe= r *tfm) return 0; } =20 -static int dthe_cipher_xts_init_tfm(struct crypto_skcipher *tfm) +static int dthe_cipher_init_tfm_fallback(struct crypto_skcipher *tfm) { struct dthe_tfm_ctx *ctx =3D crypto_skcipher_ctx(tfm); struct dthe_data *dev_data =3D dthe_get_dev(ctx); + const char *alg_name =3D crypto_tfm_alg_name(crypto_skcipher_tfm(tfm)); =20 ctx->dev_data =3D dev_data; ctx->keylen =3D 0; =20 - ctx->skcipher_fb =3D crypto_alloc_sync_skcipher("xts(aes)", 0, + ctx->skcipher_fb =3D crypto_alloc_sync_skcipher(alg_name, 0, CRYPTO_ALG_NEED_FALLBACK); if (IS_ERR(ctx->skcipher_fb)) { - dev_err(dev_data->dev, "fallback driver xts(aes) couldn't be loaded\n"); + dev_err(dev_data->dev, "fallback driver %s couldn't be loaded\n", + alg_name); return PTR_ERR(ctx->skcipher_fb); } =20 return 0; } =20 -static void dthe_cipher_xts_exit_tfm(struct crypto_skcipher *tfm) +static void dthe_cipher_exit_tfm(struct crypto_skcipher *tfm) { struct dthe_tfm_ctx *ctx =3D crypto_skcipher_ctx(tfm); =20 @@ -156,6 +161,24 @@ static int dthe_aes_cbc_setkey(struct crypto_skcipher = *tfm, const u8 *key, unsig return dthe_aes_setkey(tfm, key, keylen); } =20 +static int dthe_aes_ctr_setkey(struct crypto_skcipher *tfm, const u8 *key,= unsigned int keylen) +{ + struct dthe_tfm_ctx *ctx =3D crypto_skcipher_ctx(tfm); + int ret =3D dthe_aes_setkey(tfm, key, keylen); + + if (ret) + return ret; + + ctx->aes_mode =3D DTHE_AES_CTR; + + crypto_sync_skcipher_clear_flags(ctx->skcipher_fb, CRYPTO_TFM_REQ_MASK); + crypto_sync_skcipher_set_flags(ctx->skcipher_fb, + crypto_skcipher_get_flags(tfm) & + CRYPTO_TFM_REQ_MASK); + + return crypto_sync_skcipher_setkey(ctx->skcipher_fb, key, keylen); +} + static int dthe_aes_xts_setkey(struct crypto_skcipher *tfm, const u8 *key,= unsigned int keylen) { struct dthe_tfm_ctx *ctx =3D crypto_skcipher_ctx(tfm); @@ -171,8 +194,8 @@ static int dthe_aes_xts_setkey(struct crypto_skcipher *= tfm, const u8 *key, unsig =20 crypto_sync_skcipher_clear_flags(ctx->skcipher_fb, CRYPTO_TFM_REQ_MASK); crypto_sync_skcipher_set_flags(ctx->skcipher_fb, - crypto_skcipher_get_flags(tfm) & - CRYPTO_TFM_REQ_MASK); + crypto_skcipher_get_flags(tfm) & + CRYPTO_TFM_REQ_MASK); =20 return crypto_sync_skcipher_setkey(ctx->skcipher_fb, key, keylen); } @@ -236,6 +259,10 @@ static void dthe_aes_set_ctrl_key(struct dthe_tfm_ctx = *ctx, case DTHE_AES_CBC: ctrl_val |=3D AES_CTRL_CBC_MASK; break; + case DTHE_AES_CTR: + ctrl_val |=3D AES_CTRL_CTR_MASK; + ctrl_val |=3D DTHE_AES_CTRL_CTR_WIDTH_128B; + break; case DTHE_AES_XTS: ctrl_val |=3D AES_CTRL_XTS_MASK; break; @@ -251,6 +278,22 @@ static void dthe_aes_set_ctrl_key(struct dthe_tfm_ctx = *ctx, writel_relaxed(ctrl_val, aes_base_reg + DTHE_P_AES_CTRL); } =20 +static int dthe_aes_do_fallback(struct skcipher_request *req) +{ + struct dthe_tfm_ctx *ctx =3D crypto_skcipher_ctx(crypto_skcipher_reqtfm(r= eq)); + struct dthe_aes_req_ctx *rctx =3D skcipher_request_ctx(req); + + SYNC_SKCIPHER_REQUEST_ON_STACK(subreq, ctx->skcipher_fb); + + skcipher_request_set_callback(subreq, skcipher_request_flags(req), + req->base.complete, req->base.data); + skcipher_request_set_crypt(subreq, req->src, req->dst, + req->cryptlen, req->iv); + + return rctx->enc ? crypto_skcipher_encrypt(subreq) : + crypto_skcipher_decrypt(subreq); +} + static void dthe_aes_dma_in_callback(void *data) { struct skcipher_request *req =3D (struct skcipher_request *)data; @@ -271,7 +314,7 @@ static int dthe_aes_run(struct crypto_engine *engine, v= oid *areq) struct scatterlist *dst =3D req->dst; =20 int src_nents =3D sg_nents_for_len(src, len); - int dst_nents; + int dst_nents =3D sg_nents_for_len(dst, len); =20 int src_mapped_nents; int dst_mapped_nents; @@ -305,25 +348,62 @@ static int dthe_aes_run(struct crypto_engine *engine,= void *areq) dst_dir =3D DMA_FROM_DEVICE; } =20 + /* + * CTR mode can operate on any input length, but the hardware + * requires input length to be a multiple of the block size. + * We need to handle the padding in the driver. + */ + if (ctx->aes_mode =3D=3D DTHE_AES_CTR && req->cryptlen % AES_BLOCK_SIZE) { + unsigned int pad_size =3D AES_BLOCK_SIZE - (req->cryptlen % AES_BLOCK_SI= ZE); + u8 *pad_buf =3D rctx->padding; + struct scatterlist *sg; + + len +=3D pad_size; + src_nents++; + dst_nents++; + + src =3D kmalloc_array(src_nents, sizeof(*src), GFP_ATOMIC); + if (!src) { + ret =3D -ENOMEM; + goto aes_ctr_src_alloc_err; + } + + sg_init_table(src, src_nents); + sg =3D dthe_copy_sg(src, req->src, req->cryptlen); + memzero_explicit(pad_buf, AES_BLOCK_SIZE); + sg_set_buf(sg, pad_buf, pad_size); + + if (diff_dst) { + dst =3D kmalloc_array(dst_nents, sizeof(*dst), GFP_ATOMIC); + if (!dst) { + ret =3D -ENOMEM; + goto aes_ctr_dst_alloc_err; + } + + sg_init_table(dst, dst_nents); + sg =3D dthe_copy_sg(dst, req->dst, req->cryptlen); + sg_set_buf(sg, pad_buf, pad_size); + } else { + dst =3D src; + } + } + tx_dev =3D dmaengine_get_dma_device(dev_data->dma_aes_tx); rx_dev =3D dmaengine_get_dma_device(dev_data->dma_aes_rx); =20 src_mapped_nents =3D dma_map_sg(tx_dev, src, src_nents, src_dir); if (src_mapped_nents =3D=3D 0) { ret =3D -EINVAL; - goto aes_err; + goto aes_map_src_err; } =20 if (!diff_dst) { - dst_nents =3D src_nents; dst_mapped_nents =3D src_mapped_nents; } else { - dst_nents =3D sg_nents_for_len(dst, len); dst_mapped_nents =3D dma_map_sg(rx_dev, dst, dst_nents, dst_dir); if (dst_mapped_nents =3D=3D 0) { - dma_unmap_sg(tx_dev, src, src_nents, src_dir); ret =3D -EINVAL; - goto aes_err; + goto aes_map_dst_err; } } =20 @@ -353,8 +433,8 @@ static int dthe_aes_run(struct crypto_engine *engine, v= oid *areq) else dthe_aes_set_ctrl_key(ctx, rctx, (u32 *)req->iv); =20 - writel_relaxed(lower_32_bits(req->cryptlen), aes_base_reg + DTHE_P_AES_C_= LENGTH_0); - writel_relaxed(upper_32_bits(req->cryptlen), aes_base_reg + DTHE_P_AES_C_= LENGTH_1); + writel_relaxed(lower_32_bits(len), aes_base_reg + DTHE_P_AES_C_LENGTH_0); + writel_relaxed(upper_32_bits(len), aes_base_reg + DTHE_P_AES_C_LENGTH_1); =20 dmaengine_submit(desc_in); dmaengine_submit(desc_out); @@ -386,11 +466,26 @@ static int dthe_aes_run(struct crypto_engine *engine,= void *areq) } =20 aes_prep_err: - dma_unmap_sg(tx_dev, src, src_nents, src_dir); if (dst_dir !=3D DMA_BIDIRECTIONAL) dma_unmap_sg(rx_dev, dst, dst_nents, dst_dir); +aes_map_dst_err: + dma_unmap_sg(tx_dev, src, src_nents, src_dir); + +aes_map_src_err: + if (ctx->aes_mode =3D=3D DTHE_AES_CTR && req->cryptlen % AES_BLOCK_SIZE) { + memzero_explicit(rctx->padding, AES_BLOCK_SIZE); + if (diff_dst) + kfree(dst); +aes_ctr_dst_alloc_err: + kfree(src); +aes_ctr_src_alloc_err: + /* + * Fallback to software if ENOMEM + */ + if (ret =3D=3D -ENOMEM) + ret =3D dthe_aes_do_fallback(req); + } =20 -aes_err: local_bh_disable(); crypto_finalize_skcipher_request(dev_data->engine, req, ret); local_bh_enable(); @@ -400,7 +495,6 @@ static int dthe_aes_run(struct crypto_engine *engine, v= oid *areq) static int dthe_aes_crypt(struct skcipher_request *req) { struct dthe_tfm_ctx *ctx =3D crypto_skcipher_ctx(crypto_skcipher_reqtfm(r= eq)); - struct dthe_aes_req_ctx *rctx =3D skcipher_request_ctx(req); struct dthe_data *dev_data =3D dthe_get_dev(ctx); struct crypto_engine *engine; =20 @@ -408,20 +502,14 @@ static int dthe_aes_crypt(struct skcipher_request *re= q) * If data is not a multiple of AES_BLOCK_SIZE: * - need to return -EINVAL for ECB, CBC as they are block ciphers * - need to fallback to software as H/W doesn't support Ciphertext Steal= ing for XTS + * - do nothing for CTR */ if (req->cryptlen % AES_BLOCK_SIZE) { - if (ctx->aes_mode =3D=3D DTHE_AES_XTS) { - SYNC_SKCIPHER_REQUEST_ON_STACK(subreq, ctx->skcipher_fb); - - skcipher_request_set_callback(subreq, skcipher_request_flags(req), - req->base.complete, req->base.data); - skcipher_request_set_crypt(subreq, req->src, req->dst, - req->cryptlen, req->iv); + if (ctx->aes_mode =3D=3D DTHE_AES_XTS) + return dthe_aes_do_fallback(req); =20 - return rctx->enc ? crypto_skcipher_encrypt(subreq) : - crypto_skcipher_decrypt(subreq); - } - return -EINVAL; + if (ctx->aes_mode !=3D DTHE_AES_CTR) + return -EINVAL; } =20 /* @@ -501,8 +589,33 @@ static struct skcipher_engine_alg cipher_algs[] =3D { .op.do_one_request =3D dthe_aes_run, }, /* CBC AES */ { - .base.init =3D dthe_cipher_xts_init_tfm, - .base.exit =3D dthe_cipher_xts_exit_tfm, + .base.init =3D dthe_cipher_init_tfm_fallback, + .base.exit =3D dthe_cipher_exit_tfm, + .base.setkey =3D dthe_aes_ctr_setkey, + .base.encrypt =3D dthe_aes_encrypt, + .base.decrypt =3D dthe_aes_decrypt, + .base.min_keysize =3D AES_MIN_KEY_SIZE, + .base.max_keysize =3D AES_MAX_KEY_SIZE, + .base.ivsize =3D AES_IV_SIZE, + .base.chunksize =3D AES_BLOCK_SIZE, + .base.base =3D { + .cra_name =3D "ctr(aes)", + .cra_driver_name =3D "ctr-aes-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_SKCIPHER | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_NEED_FALLBACK, + .cra_blocksize =3D 1, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_aes_req_ctx), + .cra_module =3D THIS_MODULE, + }, + .op.do_one_request =3D dthe_aes_run, + }, /* CTR AES */ + { + .base.init =3D dthe_cipher_init_tfm_fallback, + .base.exit =3D dthe_cipher_exit_tfm, .base.setkey =3D dthe_aes_xts_setkey, .base.encrypt =3D dthe_aes_encrypt, .base.decrypt =3D dthe_aes_decrypt, diff --git a/drivers/crypto/ti/dthev2-common.c b/drivers/crypto/ti/dthev2-c= ommon.c index c39d37933b9ee..a2ad79bec105a 100644 --- a/drivers/crypto/ti/dthev2-common.c +++ b/drivers/crypto/ti/dthev2-common.c @@ -48,6 +48,25 @@ struct dthe_data *dthe_get_dev(struct dthe_tfm_ctx *ctx) return dev_data; } =20 +struct scatterlist *dthe_copy_sg(struct scatterlist *dst, + struct scatterlist *src, + int buflen) +{ + struct scatterlist *from_sg, *to_sg; + int sglen; + + for (to_sg =3D dst, from_sg =3D src; buflen && from_sg; buflen -=3D sglen= ) { + sglen =3D from_sg->length; + if (sglen > buflen) + sglen =3D buflen; + sg_set_buf(to_sg, sg_virt(from_sg), sglen); + from_sg =3D sg_next(from_sg); + to_sg =3D sg_next(to_sg); + } + + return to_sg; +} + static int dthe_dma_init(struct dthe_data *dev_data) { int ret; diff --git a/drivers/crypto/ti/dthev2-common.h b/drivers/crypto/ti/dthev2-c= ommon.h index c7a06a4c353ff..5239ee93c9442 100644 --- a/drivers/crypto/ti/dthev2-common.h +++ b/drivers/crypto/ti/dthev2-common.h @@ -36,6 +36,7 @@ enum dthe_aes_mode { DTHE_AES_ECB =3D 0, DTHE_AES_CBC, + DTHE_AES_CTR, DTHE_AES_XTS, }; =20 @@ -92,10 +93,12 @@ struct dthe_tfm_ctx { /** * struct dthe_aes_req_ctx - AES engine req ctx struct * @enc: flag indicating encryption or decryption operation + * @padding: padding buffer for handling unaligned data * @aes_compl: Completion variable for use in manual completion in case of= DMA callback failure */ struct dthe_aes_req_ctx { int enc; + u8 padding[AES_BLOCK_SIZE]; struct completion aes_compl; }; =20 @@ -103,6 +106,20 @@ struct dthe_aes_req_ctx { =20 struct dthe_data *dthe_get_dev(struct dthe_tfm_ctx *ctx); =20 +/** + * dthe_copy_sg - Copy sg entries from src to dst + * @dst: Destination sg to be filled + * @src: Source sg to be copied from + * @buflen: Number of bytes to be copied + * + * Description: + * Copy buflen bytes of data from src to dst. + * + **/ +struct scatterlist *dthe_copy_sg(struct scatterlist *dst, + struct scatterlist *src, + int buflen); + int dthe_register_aes_algs(void); void dthe_unregister_aes_algs(void); =20 --=20 2.34.1