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Thu, 26 Feb 2026 04:30:28 -0800 (PST) From: Pengyu Luo To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Pengyu Luo , Mark Brown , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov Subject: [PATCH 2/2] drm/msm/dsi/phy: rename DSI_PHY_7NM_QUIRK_PRE_V4_1 to DSI_PHY_7NM_QUIRK_V4_0 Date: Thu, 26 Feb 2026 20:29:58 +0800 Message-ID: <20260226122958.22555-3-mitltlatltl@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260226122958.22555-1-mitltlatltl@gmail.com> References: <20260226122958.22555-1-mitltlatltl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The quirk flag DSI_PHY_7NM_QUIRK_PRE_V4_1 is renamed to DSI_PHY_7NM_QUIRK_V4_0 to better reflect the actual hardware revision it applies to. (Only SM8150 uses it, its hardware revision is 4.0) No functional change. Suggested-by: Dmitry Baryshkov Signed-off-by: Pengyu Luo Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/ms= m/dsi/phy/dsi_phy_7nm.c index 01182442d..8f4b03713 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -41,8 +41,8 @@ #define VCO_REF_CLK_RATE 19200000 #define FRAC_BITS 18 =20 -/* Hardware is pre V4.1 */ -#define DSI_PHY_7NM_QUIRK_PRE_V4_1 BIT(0) +/* Hardware is V4.0 */ +#define DSI_PHY_7NM_QUIRK_V4_0 BIT(0) /* Hardware is V4.1 */ #define DSI_PHY_7NM_QUIRK_V4_1 BIT(1) /* Hardware is V4.2 */ @@ -141,7 +141,7 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *p= ll, struct dsi_pll_config dec_multiple =3D div_u64(pll_freq * multiplier, divider); dec =3D div_u64_rem(dec_multiple, multiplier, &frac); =20 - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) { + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_0) { config->pll_clock_inverters =3D 0x28; } else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_2)) { if (pll_freq < 163000000ULL) @@ -264,7 +264,7 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7= nm *pll) void __iomem *base =3D pll->phy->pll_base; u8 analog_controls_five_1 =3D 0x01, vco_config_1 =3D 0x00; =20 - if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_0)) if (pll->vco_current_rate >=3D 3100000000ULL) analog_controls_five_1 =3D 0x03; =20 @@ -313,10 +313,10 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll= _7nm *pll) writel(0x29, base + REG_DSI_7nm_PHY_PLL_PFILT); writel(0x2f, base + REG_DSI_7nm_PHY_PLL_PFILT); writel(0x2a, base + REG_DSI_7nm_PHY_PLL_IFILT); - writel(!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) ? 0x3f : 0x2= 2, + writel(!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_0) ? 0x3f : 0x22, base + REG_DSI_7nm_PHY_PLL_IFILT); =20 - if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) { + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_0)) { writel(0x22, base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE); if (pll->slave) writel(0x22, pll->slave->phy->pll_base + REG_DSI_7nm_PHY_PLL_PERF_OPTIM= IZE); @@ -928,7 +928,7 @@ static void dsi_phy_hw_v4_0_lane_settings(struct msm_ds= i_phy *phy) const u8 *tx_dctrl =3D tx_dctrl_0; void __iomem *lane_base =3D phy->lane_base; =20 - if (!(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) + if (!(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_0)) tx_dctrl =3D tx_dctrl_1; =20 /* Strength ctrl settings */ @@ -1319,7 +1319,7 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = =3D { .max_pll_rate =3D 3500000000UL, .io_start =3D { 0xae94400, 0xae96400 }, .num_dsi_phy =3D 2, - .quirks =3D DSI_PHY_7NM_QUIRK_PRE_V4_1, + .quirks =3D DSI_PHY_7NM_QUIRK_V4_0, }; =20 const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs =3D { --=20 2.53.0