From nobody Tue Apr 7 15:28:06 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 784B0396B87 for ; Thu, 26 Feb 2026 10:11:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772100710; cv=none; b=eGMZo1vXeQ53EukYXrIGt4fVWq7H0M69svF1ItMunh0+r6kGVRY1rkm68L+3Zq2NuZ7IOrCyq9g881nVAdVzPCIAw7xbN/3TScAHjRTiJG/alGLFArsJ0un0NX/KhqSOmPr2UY27Hx7gIqOmu3LoFC2ASSKfLiMyMsTjSAKJBvM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772100710; c=relaxed/simple; bh=uUZ12Y7btsAdg5RteYrhizDP81eRxETZHQRuZqgzDYc=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=DXAejr21elFXfQBpc/VAeYNKEqAPzkJ1RzwCsxdnlYr2B8H5Gds0nHb25IYZmK+356d9f4rOazb/rsAwuVncG1gwJwIAe1q0XDrgTE/rif4xQ7p5UQ3yCa5Zf4nnXci4MaoQufO5hW3Xhf/HSjnN4bPER2gKklXaPN6rF328D2s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C49FF1516; Thu, 26 Feb 2026 02:11:41 -0800 (PST) Received: from ergosum.cambridge.arm.com (ergosum.cambridge.arm.com [10.1.196.45]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C3F063F7BD; Thu, 26 Feb 2026 02:11:46 -0800 (PST) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Ryan Roberts , Mark Rutland , linux-kernel@vger.kernel.org Subject: [PATCH] arm64/mm: Describe 52 bits PA folding into TTBRx_EL1 Date: Thu, 26 Feb 2026 10:11:35 +0000 Message-Id: <20260226101135.1915529-1-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.30.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" A 52 bits physical address gets stored in TTBR_BADDR_MASK_52 in a folded manner. Shifting PA[51:0] right ward by '46' bits, aligns PA[51:48] into TTBRx_EL1[5:2] which gets ORed for the final TTBRx_EL1 encoding. Define TTBR_BADDR_HIGH_52_PA_PIVOT which describes this inflection point, where this right shift is done thus bringing some clarity to this 52 bits PA address folding process in TTBRx_EL1. Cc: Catalin Marinas Cc: Will Deacon Cc: Ryan Roberts Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- This applies on v7.0-rc1 Earlier context can be found here. https://lore.kernel.org/linux-arm-kernel/aRb8ezhQd0c0jp9G@J2N7QTR9R3/ arch/arm64/include/asm/assembler.h | 2 +- arch/arm64/include/asm/pgtable-hwdef.h | 14 ++++++++++++++ arch/arm64/include/asm/pgtable.h | 3 ++- 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/as= sembler.h index d3d46e5f7188..a68002dd4c0e 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -615,7 +615,7 @@ alternative_else_nop_endif */ .macro phys_to_ttbr, ttbr, phys #ifdef CONFIG_ARM64_PA_BITS_52 - orr \ttbr, \phys, \phys, lsr #46 + orr \ttbr, \phys, \phys, lsr #TTBR_BADDR_52_PA_PIVOT and \ttbr, \ttbr, #TTBR_BADDR_MASK_52 #else mov \ttbr, \phys diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/as= m/pgtable-hwdef.h index d49180bb7cb3..21ca79f02a5d 100644 --- a/arch/arm64/include/asm/pgtable-hwdef.h +++ b/arch/arm64/include/asm/pgtable-hwdef.h @@ -284,6 +284,20 @@ * TTBR_ELx[1] is RES0 in this configuration. */ #define TTBR_BADDR_MASK_52 GENMASK_ULL(47, 2) + +/* + * A 52 bit physical address gets stored in TTBR_BADDR_MASK_52 i.e + * GENMASK(47, 2) in a folded manner. Shifting PA[51:0] right ward + * by 46 bits aligns PA[51:48] into TTBRx_EL1[5:2] which gets ORed + * subsequently for the final TTBRx_EL1 encoding. + * + * 47 5 2 0 + * +----------------------------------------------+-----------+--+ + * | PA[47:X] | PA[51:48] | | + * +----------------------------------------------+-----------+--+ + * + */ +#define TTBR_BADDR_52_PA_PIVOT (51 - 5) #endif =20 #ifdef CONFIG_ARM64_VA_BITS_52 diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgta= ble.h index b3e58735c49b..2f274c468d83 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -1576,7 +1576,8 @@ static inline void update_mmu_cache_range(struct vm_f= ault *vmf, #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) =20 #ifdef CONFIG_ARM64_PA_BITS_52 -#define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) +#define phys_to_ttbr(addr) (((addr) | ((addr) >> TTBR_BADDR_52_PA_PIVOT)) = & \ + TTBR_BADDR_MASK_52) #else #define phys_to_ttbr(addr) (addr) #endif --=20 2.30.2