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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-679f2d9e8d6sm549939eaf.13.2026.02.25.18.05.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Feb 2026 18:05:27 -0800 (PST) From: Songwei Chai To: andersson@kernel.org, alexander.shishkin@linux.intel.com, mike.leach@linaro.org, konrad.dybcio@oss.qualcomm.com, suzuki.poulose@arm.com, james.clark@arm.com, krzk+dt@kernel.org, conor+dt@kernel.org Cc: Songwei Chai , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, devicetree@vger.kernel.org, gregkh@linuxfoundation.org Subject: [PATCH v11 6/7] qcom-tgu: Add timer/counter functionality for TGU Date: Wed, 25 Feb 2026 18:04:53 -0800 Message-Id: <20260226020454.3210149-7-songwei.chai@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260226020454.3210149-1-songwei.chai@oss.qualcomm.com> References: <20260226020454.3210149-1-songwei.chai@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: 5tf912dG-ctDdIBi1MdaXaOmacm3NcPv X-Authority-Analysis: v=2.4 cv=Zs/g6t7G c=1 sm=1 tr=0 ts=699faa69 cx=c_pps a=V4L7fE8DliODT/OoDI2WOg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=eGDQztGCVwpQsGOtWZEA:9 a=WZGXeFmKUf7gPmL3hEjn:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjI2MDAxNiBTYWx0ZWRfXz95/EXz/wX15 2M6QpZoqX9cP4/LtVpOoSaWd6L/UZixfx73txkf0XkU2JWlZvSZfyChtl4IlNwok3B5SwBGh9bz ygPZybfWV0sVHkH7eEVpU4ERuyhi+mtAu6NGHHXYeFnEOvfHAnBMyYElKyFrz+ePoNZcd6gasXH gXbnGGx9BjSz8LhgUCTBJ7uXDwRZUu7Csy+ZTb0d6OcVXcFQAfgAoXSCQ5JiH28FjByzn3ZUzpF SCEc5UayjTrszY7G4xhkIUklYOpCElgiEodPWKHeXSUAiRGMNXl4FU4Hez34vlivf1JoPFxR41o ay4BSRDUPkxlthW/6pa8h826433M6t52OnSMQYGdxa6xsqEtCtWs2poHeC2tu04Exuha8kpfrme q67UU6Ue31RdaWLsWek7uy14B3x8e9jUNKpp5JTqQnlE5enV9UHOydGy6p9IGty76Qep6n/d+q3 ufOuj77GNogM6HZ24kA== X-Proofpoint-ORIG-GUID: 5tf912dG-ctDdIBi1MdaXaOmacm3NcPv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-25_04,2026-02-25_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602260016 Content-Type: text/plain; charset="utf-8" Add counter and timer node for each step which could be programed if they are to be utilized in trigger event/sequence. Signed-off-by: Songwei Chai --- .../ABI/testing/sysfs-bus-amba-devices-tgu | 14 +++ drivers/hwtracing/qcom/tgu.c | 116 +++++++++++++++++- drivers/hwtracing/qcom/tgu.h | 54 ++++++++ 3 files changed, 182 insertions(+), 2 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documen= tation/ABI/testing/sysfs-bus-amba-devices-tgu index fbe8efe470d1..9daacd68eed0 100644 --- a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu @@ -28,3 +28,17 @@ KernelVersion 6.20 Contact: Jinlong Mao , Songwei Chai Description: (RW) Set/Get the next action with specific step for TGU. + +What: /sys/bus/amba/devices//step[0:7]_timer/reg[0:1] +Date: February 2026 +KernelVersion 6.20 +Contact: Jinlong Mao , Songwei Chai +Description: + (RW) Set/Get the timer value with specific step for TGU. + +What: /sys/bus/amba/devices//step[0:7]_counter/reg[0:1] +Date: February 2026 +KernelVersion 6.20 +Contact: Jinlong Mao , Songwei Chai +Description: + (RW) Set/Get the counter value with specific step for TGU. diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c index 1d996b9e303a..4539415571f6 100644 --- a/drivers/hwtracing/qcom/tgu.c +++ b/drivers/hwtracing/qcom/tgu.c @@ -32,6 +32,10 @@ static int calculate_array_location(struct tgu_drvdata *= drvdata, case TGU_CONDITION_SELECT: return step_index * (drvdata->num_condition_select) + reg_index; + case TGU_COUNTER: + return step_index * (drvdata->num_counter) + reg_index; + case TGU_TIMER: + return step_index * (drvdata->num_timer) + reg_index; default: break; } @@ -77,6 +81,12 @@ static ssize_t tgu_dataset_show(struct device *dev, case TGU_CONDITION_SELECT: return sysfs_emit(buf, "0x%x\n", drvdata->value_table->condition_select[index]); + case TGU_TIMER: + return sysfs_emit(buf, "0x%x\n", + drvdata->value_table->timer[index]); + case TGU_COUNTER: + return sysfs_emit(buf, "0x%x\n", + drvdata->value_table->counter[index]); default: break; } @@ -122,6 +132,14 @@ static ssize_t tgu_dataset_store(struct device *dev, tgu_drvdata->value_table->condition_select[index] =3D val; ret =3D size; break; + case TGU_TIMER: + tgu_drvdata->value_table->timer[index] =3D val; + ret =3D size; + break; + case TGU_COUNTER: + tgu_drvdata->value_table->counter[index] =3D val; + ret =3D size; + break; default: ret =3D -EINVAL; break; @@ -163,6 +181,18 @@ static umode_t tgu_node_visible(struct kobject *kobjec= t, if (tgu_attr->reg_num < drvdata->num_condition_select) return attr->mode; break; + case TGU_COUNTER: + if (!drvdata->num_counter) + break; + if (tgu_attr->reg_num < drvdata->num_counter) + return attr->mode; + break; + case TGU_TIMER: + if (!drvdata->num_timer) + break; + if (tgu_attr->reg_num < drvdata->num_timer) + return attr->mode; + break; default: break; } @@ -213,6 +243,30 @@ static ssize_t tgu_write_all_hw_regs(struct tgu_drvdat= a *drvdata) drvdata->base + CONDITION_SELECT_STEP(i, j)); } } + + for (i =3D 0; i < drvdata->num_step; i++) { + for (j =3D 0; j < drvdata->num_timer; j++) { + index =3D check_array_location(drvdata, i, TGU_TIMER, j); + + if (index =3D=3D -EINVAL) + goto exit; + + writel(drvdata->value_table->timer[index], + drvdata->base + TIMER_COMPARE_STEP(i, j)); + } + } + + for (i =3D 0; i < drvdata->num_step; i++) { + for (j =3D 0; j < drvdata->num_counter; j++) { + index =3D check_array_location(drvdata, i, TGU_COUNTER, j); + + if (index =3D=3D -EINVAL) + goto exit; + + writel(drvdata->value_table->counter[index], + drvdata->base + COUNTER_COMPARE_STEP(i, j)); + } + } /* Enable TGU to program the triggers */ writel(1, drvdata->base + TGU_CONTROL); exit: @@ -256,6 +310,27 @@ static void tgu_set_conditions(struct tgu_drvdata *drv= data) drvdata->num_condition_select =3D TGU_DEVID_CONDITIONS(devid) + 1; } =20 +static void tgu_set_timer_counter(struct tgu_drvdata *drvdata) +{ + int num_timers =3D 0, num_counters =3D 0; + u32 devid2; + + devid2 =3D readl(drvdata->base + CORESIGHT_DEVID2); + + if (TGU_DEVID2_TIMER0(devid2)) + num_timers++; + if (TGU_DEVID2_TIMER1(devid2)) + num_timers++; + + if (TGU_DEVID2_COUNTER0(devid2)) + num_counters++; + if (TGU_DEVID2_COUNTER1(devid2)) + num_counters++; + + drvdata->num_timer =3D num_timers; + drvdata->num_counter =3D num_counters; +} + static int tgu_enable(struct device *dev) { struct tgu_drvdata *drvdata =3D dev_get_drvdata(dev); @@ -395,6 +470,22 @@ static const struct attribute_group *tgu_attr_groups[]= =3D { CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(5), CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(6), CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(7), + TIMER_ATTRIBUTE_GROUP_INIT(0), + TIMER_ATTRIBUTE_GROUP_INIT(1), + TIMER_ATTRIBUTE_GROUP_INIT(2), + TIMER_ATTRIBUTE_GROUP_INIT(3), + TIMER_ATTRIBUTE_GROUP_INIT(4), + TIMER_ATTRIBUTE_GROUP_INIT(5), + TIMER_ATTRIBUTE_GROUP_INIT(6), + TIMER_ATTRIBUTE_GROUP_INIT(7), + COUNTER_ATTRIBUTE_GROUP_INIT(0), + COUNTER_ATTRIBUTE_GROUP_INIT(1), + COUNTER_ATTRIBUTE_GROUP_INIT(2), + COUNTER_ATTRIBUTE_GROUP_INIT(3), + COUNTER_ATTRIBUTE_GROUP_INIT(4), + COUNTER_ATTRIBUTE_GROUP_INIT(5), + COUNTER_ATTRIBUTE_GROUP_INIT(6), + COUNTER_ATTRIBUTE_GROUP_INIT(7), NULL, }; =20 @@ -402,8 +493,8 @@ static int tgu_probe(struct amba_device *adev, const st= ruct amba_id *id) { struct device *dev =3D &adev->dev; struct tgu_drvdata *drvdata; - unsigned int *priority, *condition, *select; - size_t priority_size, condition_size, select_size; + unsigned int *priority, *condition, *select, *timer, *counter; + size_t priority_size, condition_size, select_size, timer_size, counter_si= ze; int ret; =20 drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); @@ -422,6 +513,7 @@ static int tgu_probe(struct amba_device *adev, const st= ruct amba_id *id) tgu_set_reg_number(drvdata); tgu_set_steps(drvdata); tgu_set_conditions(drvdata); + tgu_set_timer_counter(drvdata); =20 ret =3D sysfs_create_groups(&dev->kobj, tgu_attr_groups); if (ret) { @@ -464,6 +556,26 @@ static int tgu_probe(struct amba_device *adev, const s= truct amba_id *id) =20 drvdata->value_table->condition_select =3D select; =20 + timer_size =3D drvdata->num_step * drvdata->num_timer; + + timer =3D devm_kcalloc(dev, timer_size, + sizeof(*(drvdata->value_table->timer)), + GFP_KERNEL); + if (!timer) + return -ENOMEM; + + drvdata->value_table->timer =3D timer; + + counter_size =3D drvdata->num_step * drvdata->num_counter; + + counter =3D devm_kcalloc(dev, counter_size, + sizeof(*(drvdata->value_table->counter)), + GFP_KERNEL); + if (!counter) + return -ENOMEM; + + drvdata->value_table->counter =3D counter; + drvdata->enabled =3D false; =20 pm_runtime_put(&adev->dev); diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h index 5beaf82b4b8c..6ea71963e672 100644 --- a/drivers/hwtracing/qcom/tgu.h +++ b/drivers/hwtracing/qcom/tgu.h @@ -11,6 +11,7 @@ #define TGU_LAR 0xfb0 #define TGU_UNLOCK_OFFSET 0xc5acce55 #define TGU_DEVID 0xfc8 +#define CORESIGHT_DEVID2 0xfc0 =20 #define TGU_DEVID_SENSE_INPUT(devid_val) \ ((int)FIELD_GET(GENMASK(17, 10), devid_val)) @@ -18,6 +19,14 @@ ((int)FIELD_GET(GENMASK(6, 3), devid_val)) #define TGU_DEVID_CONDITIONS(devid_val) \ ((int)FIELD_GET(GENMASK(2, 0), devid_val)) +#define TGU_DEVID2_TIMER0(devid_val) \ + ((int)FIELD_GET(GENMASK(23, 18), devid_val)) +#define TGU_DEVID2_TIMER1(devid_val) \ + ((int)FIELD_GET(GENMASK(17, 13), devid_val)) +#define TGU_DEVID2_COUNTER0(devid_val) \ + ((int)FIELD_GET(GENMASK(11, 6), devid_val)) +#define TGU_DEVID2_COUNTER1(devid_val) \ + ((int)FIELD_GET(GENMASK(5, 0), devid_val)) =20 #define TGU_BITS_PER_SIGNAL 4 #define LENGTH_REGISTER 32 @@ -54,6 +63,8 @@ #define PRIORITY_START_OFFSET 0x0074 #define CONDITION_DECODE_OFFSET 0x0050 #define CONDITION_SELECT_OFFSET 0x0060 +#define TIMER_START_OFFSET 0x0040 +#define COUNTER_START_OFFSET 0x0048 #define PRIORITY_OFFSET 0x60 #define REG_OFFSET 0x4 =20 @@ -68,6 +79,12 @@ #define CONDITION_SELECT_STEP(step, select) \ (CONDITION_SELECT_OFFSET + REG_OFFSET * select + STEP_OFFSET * step) =20 +#define TIMER_COMPARE_STEP(step, timer) \ + (TIMER_START_OFFSET + REG_OFFSET * timer + STEP_OFFSET * step) + +#define COUNTER_COMPARE_STEP(step, counter) \ + (COUNTER_START_OFFSET + REG_OFFSET * counter + STEP_OFFSET * step) + #define tgu_dataset_rw(name, step_index, type, reg_num) \ (&((struct tgu_attribute[]){ { \ __ATTR(name, 0644, tgu_dataset_show, tgu_dataset_store), \ @@ -83,6 +100,10 @@ tgu_dataset_rw(reg##reg_num, step_index, TGU_CONDITION_DECODE, reg_num) #define STEP_SELECT(step_index, reg_num) \ tgu_dataset_rw(reg##reg_num, step_index, TGU_CONDITION_SELECT, reg_num) +#define STEP_TIMER(step_index, reg_num) \ + tgu_dataset_rw(reg##reg_num, step_index, TGU_TIMER, reg_num) +#define STEP_COUNTER(step_index, reg_num) \ + tgu_dataset_rw(reg##reg_num, step_index, TGU_COUNTER, reg_num) =20 #define STEP_PRIORITY_LIST(step_index, priority) \ {STEP_PRIORITY(step_index, 0, priority), \ @@ -123,6 +144,18 @@ NULL \ } =20 +#define STEP_TIMER_LIST(n) \ + {STEP_TIMER(n, 0), \ + STEP_TIMER(n, 1), \ + NULL \ + } + +#define STEP_COUNTER_LIST(n) \ + {STEP_COUNTER(n, 0), \ + STEP_COUNTER(n, 1), \ + NULL \ + } + #define PRIORITY_ATTRIBUTE_GROUP_INIT(step, priority)\ (&(const struct attribute_group){\ .attrs =3D (struct attribute*[])STEP_PRIORITY_LIST(step, priority),\ @@ -144,6 +177,19 @@ .name =3D "step" #step "_condition_select" \ }) =20 +#define TIMER_ATTRIBUTE_GROUP_INIT(step)\ + (&(const struct attribute_group){\ + .attrs =3D (struct attribute*[])STEP_TIMER_LIST(step),\ + .is_visible =3D tgu_node_visible,\ + .name =3D "step" #step "_timer" \ + }) + +#define COUNTER_ATTRIBUTE_GROUP_INIT(step)\ + (&(const struct attribute_group){\ + .attrs =3D (struct attribute*[])STEP_COUNTER_LIST(step),\ + .is_visible =3D tgu_node_visible,\ + .name =3D "step" #step "_counter" \ + }) =20 enum operation_index { TGU_PRIORITY0, @@ -152,6 +198,8 @@ enum operation_index { TGU_PRIORITY3, TGU_CONDITION_DECODE, TGU_CONDITION_SELECT, + TGU_TIMER, + TGU_COUNTER }; =20 /* Maximum priority that TGU supports */ @@ -168,6 +216,8 @@ struct value_table { unsigned int *priority; unsigned int *condition_decode; unsigned int *condition_select; + unsigned int *timer; + unsigned int *counter; }; =20 static inline void TGU_LOCK(void __iomem *addr) @@ -199,6 +249,8 @@ static inline void TGU_UNLOCK(void __iomem *addr) * @num_step: Maximum step size * @num_condition_decode: Maximum number of condition_decode * @num_condition_select: Maximum number of condition_select + * @num_timer: Maximum number of timers + * @num_counter: Maximum number of counters * * This structure defines the data associated with a TGU device, * including its base address, device pointers, clock, spinlock for @@ -215,6 +267,8 @@ struct tgu_drvdata { int num_step; int num_condition_decode; int num_condition_select; + int num_timer; + int num_counter; }; =20 #endif --=20 2.34.1