From nobody Tue Apr 7 18:48:30 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1EED3D3CF7 for ; Thu, 26 Feb 2026 16:17:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772122679; cv=none; b=oR7IsoKaXinmDyLwRrcOFEx1a9DnXkWqpPgfoccf+IdBHtNCIHcigBgUpqUiZ9SkEJ42SwebxiowjRwArmDreNY0Rtus5XP5IfV63obk+y8NgqTTNU3u4wioTxQL1I2JDlHKbzSw3p3zxY24lNBGrxcNcyRja9QJo8C2KwCoh00= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772122679; c=relaxed/simple; bh=QjDfBOjj+v9+tm8usbQFDuQsLWjBDEFBxE2wtwecyhA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WyOYqV86od7eCSnLK8vBmCxgPX4XgAQXRyhDRBgbs6HM8lOQe0zjn29UWS10i55hZ29DPIr1Y2if1uX3MR6xMT20duLhVW1eyG/YD2WLL0v7g8KW33vczBKPeJ51nqdlTswlYsTv2WbcsbKFbtQ+YxbmTZM45W3GptNlq43Ixow= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=Th4jixQk; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Th4jixQk" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 5B1D94E4122E; Thu, 26 Feb 2026 16:17:51 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 2F0D45FDE9; Thu, 26 Feb 2026 16:17:51 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 3694F103693C1; Thu, 26 Feb 2026 17:17:48 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1772122670; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=8XkrbW1hnirnZLGMwEegjlBI4fLIXypAXffpHsh+X60=; b=Th4jixQkyCmPeaFtAecWi2A1PmjmPfSM0/peoVmRNauB/hxMWa35AID7i4yYTPH0KYkW5r Wd8p3MN0TZEPQvnXHN59vEeMDXm+UI3cYTmT92WA4TNLw9oRdeepM1VeHKAnv1PJr0Gd6N T9GlU8wkQY+sBYZcrAGO3geU06L11B7dDTZ+iBILinZ4uV5syAGPvjS9U4vEA9h4M00DWX dsonptG6TrQu2O5QuVcCtn5gLVV7HcrAdPaqdhuRl8k6gjTQJG67CctyrmxcE/QTkHyo11 mslwaDbfPHVY7Wu+G1Pzpl9M/klUA5MrjNj/+co8lWM2xagL1ak19s+zWdRQqQ== From: Luca Ceresoli Date: Thu, 26 Feb 2026 17:16:44 +0100 Subject: [PATCH 1/3] drm/bridge: ti-sn65dsi83: fix CHA_DSI_CLK_RANGE rounding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260226-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v1-1-2e15f5a9a6a0@bootlin.com> References: <20260226-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v1-0-2e15f5a9a6a0@bootlin.com> In-Reply-To: <20260226-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v1-0-2e15f5a9a6a0@bootlin.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Frieder Schrempf , Marek Vasut , Linus Walleij Cc: Thomas Petazzoni , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Luca Ceresoli , stable@vger.kernel.org X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The DSI frequency must be in the range: (CHA_DSI_CLK_RANGE * 5 MHz) <=3D DSI freq < ((CHA_DSI_CLK_RANGE + 1) * 5 = MHz) So the register value shouldpoint to the lower range value, but DIV_ROUND_UP() rounds the division to the higher range value, resulting in an excess of 1 (unless the frequency is an exact multiple of 5 MHz). For example for a 437100000 MHz clock CHA_DSI_CLK_RANGE should be 87 (0x57): (87 * 5 =3D 435) <=3D 437.1 < (88 * 5 =3D 440) but current code returns 88 (0x58). Fix the computation by removing the DIV_ROUND_UP(). Fixes: ceb515ba29ba ("drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DS= I84 driver") Cc: stable@vger.kernel.org Signed-off-by: Luca Ceresoli Reviewed-by: Marek Vasut --- drivers/gpu/drm/bridge/ti-sn65dsi83.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge= /ti-sn65dsi83.c index f6736b4457bb..d2a81175d279 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c @@ -351,9 +351,9 @@ static u8 sn65dsi83_get_dsi_range(struct sn65dsi83 *ctx, * DSI_CLK =3D mode clock * bpp / dsi_data_lanes / 2 * the 2 is there because the bus is DDR. */ - return DIV_ROUND_UP(clamp((unsigned int)mode->clock * - mipi_dsi_pixel_format_to_bpp(ctx->dsi->format) / - ctx->dsi->lanes / 2, 40000U, 500000U), 5000U); + return clamp((unsigned int)mode->clock * + mipi_dsi_pixel_format_to_bpp(ctx->dsi->format) / + ctx->dsi->lanes / 2, 40000U, 500000U) / 5000U; } =20 static u8 sn65dsi83_get_dsi_div(struct sn65dsi83 *ctx) --=20 2.53.0