From nobody Tue Apr 7 17:16:49 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1EED3D3CF7 for ; Thu, 26 Feb 2026 16:17:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772122679; cv=none; b=oR7IsoKaXinmDyLwRrcOFEx1a9DnXkWqpPgfoccf+IdBHtNCIHcigBgUpqUiZ9SkEJ42SwebxiowjRwArmDreNY0Rtus5XP5IfV63obk+y8NgqTTNU3u4wioTxQL1I2JDlHKbzSw3p3zxY24lNBGrxcNcyRja9QJo8C2KwCoh00= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772122679; c=relaxed/simple; bh=QjDfBOjj+v9+tm8usbQFDuQsLWjBDEFBxE2wtwecyhA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WyOYqV86od7eCSnLK8vBmCxgPX4XgAQXRyhDRBgbs6HM8lOQe0zjn29UWS10i55hZ29DPIr1Y2if1uX3MR6xMT20duLhVW1eyG/YD2WLL0v7g8KW33vczBKPeJ51nqdlTswlYsTv2WbcsbKFbtQ+YxbmTZM45W3GptNlq43Ixow= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=Th4jixQk; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Th4jixQk" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 5B1D94E4122E; Thu, 26 Feb 2026 16:17:51 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 2F0D45FDE9; Thu, 26 Feb 2026 16:17:51 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 3694F103693C1; Thu, 26 Feb 2026 17:17:48 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1772122670; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=8XkrbW1hnirnZLGMwEegjlBI4fLIXypAXffpHsh+X60=; b=Th4jixQkyCmPeaFtAecWi2A1PmjmPfSM0/peoVmRNauB/hxMWa35AID7i4yYTPH0KYkW5r Wd8p3MN0TZEPQvnXHN59vEeMDXm+UI3cYTmT92WA4TNLw9oRdeepM1VeHKAnv1PJr0Gd6N T9GlU8wkQY+sBYZcrAGO3geU06L11B7dDTZ+iBILinZ4uV5syAGPvjS9U4vEA9h4M00DWX dsonptG6TrQu2O5QuVcCtn5gLVV7HcrAdPaqdhuRl8k6gjTQJG67CctyrmxcE/QTkHyo11 mslwaDbfPHVY7Wu+G1Pzpl9M/klUA5MrjNj/+co8lWM2xagL1ak19s+zWdRQqQ== From: Luca Ceresoli Date: Thu, 26 Feb 2026 17:16:44 +0100 Subject: [PATCH 1/3] drm/bridge: ti-sn65dsi83: fix CHA_DSI_CLK_RANGE rounding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260226-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v1-1-2e15f5a9a6a0@bootlin.com> References: <20260226-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v1-0-2e15f5a9a6a0@bootlin.com> In-Reply-To: <20260226-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v1-0-2e15f5a9a6a0@bootlin.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Frieder Schrempf , Marek Vasut , Linus Walleij Cc: Thomas Petazzoni , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Luca Ceresoli , stable@vger.kernel.org X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The DSI frequency must be in the range: (CHA_DSI_CLK_RANGE * 5 MHz) <=3D DSI freq < ((CHA_DSI_CLK_RANGE + 1) * 5 = MHz) So the register value shouldpoint to the lower range value, but DIV_ROUND_UP() rounds the division to the higher range value, resulting in an excess of 1 (unless the frequency is an exact multiple of 5 MHz). For example for a 437100000 MHz clock CHA_DSI_CLK_RANGE should be 87 (0x57): (87 * 5 =3D 435) <=3D 437.1 < (88 * 5 =3D 440) but current code returns 88 (0x58). Fix the computation by removing the DIV_ROUND_UP(). Fixes: ceb515ba29ba ("drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DS= I84 driver") Cc: stable@vger.kernel.org Signed-off-by: Luca Ceresoli Reviewed-by: Marek Vasut --- drivers/gpu/drm/bridge/ti-sn65dsi83.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge= /ti-sn65dsi83.c index f6736b4457bb..d2a81175d279 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c @@ -351,9 +351,9 @@ static u8 sn65dsi83_get_dsi_range(struct sn65dsi83 *ctx, * DSI_CLK =3D mode clock * bpp / dsi_data_lanes / 2 * the 2 is there because the bus is DDR. */ - return DIV_ROUND_UP(clamp((unsigned int)mode->clock * - mipi_dsi_pixel_format_to_bpp(ctx->dsi->format) / - ctx->dsi->lanes / 2, 40000U, 500000U), 5000U); + return clamp((unsigned int)mode->clock * + mipi_dsi_pixel_format_to_bpp(ctx->dsi->format) / + ctx->dsi->lanes / 2, 40000U, 500000U) / 5000U; } =20 static u8 sn65dsi83_get_dsi_div(struct sn65dsi83 *ctx) --=20 2.53.0 From nobody Tue Apr 7 17:16:49 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0DFC44D03A for ; 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arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="vWjKSWbG" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id B1F1A1A168B; Thu, 26 Feb 2026 16:17:54 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 870F25FDE9; Thu, 26 Feb 2026 16:17:54 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 9B12F103693EF; Thu, 26 Feb 2026 17:17:50 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1772122673; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=J7rzqyCwEJE4QXCmYRXeLF0zeRFmIwZ7a/ILMFOO6lk=; b=vWjKSWbGaHRLu3pK8EgSpxFFj8Twa/amgqR7pjMNa/N4VH+zHuLyp0fNwGyGZuuQMFJE/M AU165sADWJr6Q2JYK4bkmYXs++Q3vyPe0zx2SS6LgDsqvzVNnJjGODa705WpLPN5HeIfgR 3FHdedKuzs0tL4PpbiJ/WMBaaVSbDvZEno9caipVzsmTWLpp/F4NmOMI8OqNDq5e3+hPBQ Kiydg2dcv0cz8aiEZoYkBZDmNxSsjkF0C8Ng+E0llsheA6zXiAgTl9XTF4635QOFWtwSPf +741P1lxczB9Wr8cVbZ3W3f/TDG3y4sUSA0ls0qtwGmypQ2MTZBhTFsg2Va6qA== From: Luca Ceresoli Date: Thu, 26 Feb 2026 17:16:45 +0100 Subject: [PATCH 2/3] drm/bridge: ti-sn65dsi83: halve horizontal syncs for dual LVDS output Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260226-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v1-2-2e15f5a9a6a0@bootlin.com> References: <20260226-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v1-0-2e15f5a9a6a0@bootlin.com> In-Reply-To: <20260226-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v1-0-2e15f5a9a6a0@bootlin.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Frieder Schrempf , Marek Vasut , Linus Walleij Cc: Thomas Petazzoni , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Luca Ceresoli , stable@vger.kernel.org X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Dual LVDS output (available on the SN65DSI84) requires HSYNC_PULSE_WIDTH and HORIZONTAL_BACK_PORCH to be divided by two with respect to the values used for single LVDS output. While not clearly stated in the datasheet, this is needed according to the DSI Tuner [0] output. It also makes sense intuitively because in dual LVDS output two pixels at a time are output and so the output clock is half of the pixel clock. Some dual-LVDS panels refuse to show any picture without this fix. Divide by two HORIZONTAL_FRONT_PORCH too, even though this register is used only for test pattern generation which is not currently implemented by this driver. [0] https://www.ti.com/tool/DSI-TUNER Fixes: ceb515ba29ba ("drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DS= I84 driver") Cc: stable@vger.kernel.org Signed-off-by: Luca Ceresoli Reviewed-by: Marek Vasut --- drivers/gpu/drm/bridge/ti-sn65dsi83.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge= /ti-sn65dsi83.c index d2a81175d279..17a885244e1e 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c @@ -517,6 +517,7 @@ static void sn65dsi83_atomic_pre_enable(struct drm_brid= ge *bridge, struct drm_atomic_state *state) { struct sn65dsi83 *ctx =3D bridge_to_sn65dsi83(bridge); + const unsigned int dual_factor =3D ctx->lvds_dual_link ? 2 : 1; const struct drm_bridge_state *bridge_state; const struct drm_crtc_state *crtc_state; const struct drm_display_mode *mode; @@ -653,18 +654,18 @@ static void sn65dsi83_atomic_pre_enable(struct drm_br= idge *bridge, /* 32 + 1 pixel clock to ensure proper operation */ le16val =3D cpu_to_le16(32 + 1); regmap_bulk_write(ctx->regmap, REG_VID_CHA_SYNC_DELAY_LOW, &le16val, 2); - le16val =3D cpu_to_le16(mode->hsync_end - mode->hsync_start); + le16val =3D cpu_to_le16((mode->hsync_end - mode->hsync_start) / dual_fact= or); regmap_bulk_write(ctx->regmap, REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, &le16val, 2); le16val =3D cpu_to_le16(mode->vsync_end - mode->vsync_start); regmap_bulk_write(ctx->regmap, REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, &le16val, 2); regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_BACK_PORCH, - mode->htotal - mode->hsync_end); + (mode->htotal - mode->hsync_end) / dual_factor); regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_BACK_PORCH, mode->vtotal - mode->vsync_end); regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_FRONT_PORCH, - mode->hsync_start - mode->hdisplay); + (mode->hsync_start - mode->hdisplay) / dual_factor); regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH, mode->vsync_start - mode->vdisplay); regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00); --=20 2.53.0 From nobody Tue Apr 7 17:16:49 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1E5C363C58 for ; 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bh=w5vPufaau/3I2QpJ9e2+Z9v2JqhTHbqrTx3oXaG/ZO4=; b=SHZw10H+CRxh0DMlHtFEARQLTPyEM0rce1xFoOvnREX4YLoCytnQZn7K8oGDwMTn0RWNLX tRLdcrIZzQ49RjSThw8Z3cIBWZ7+LffiQHIpdK578hl5UCFpCyd1eGXhyaeY3aClwuGi90 X4w3RZh1u3fOK4Et881Ya/FA2ZlwXAtYT5gt/gPS9pqzVEzoKGXB/6puAtUM6pc8BtJEzu WroSs6fqNMgHWL5VkqqvU0CBRVWs6pv90Z7dy1D1cVUXs/F+YFOOXPhh/L6L7WaotxZKMm OP94AVuy4REkMxP+fcj5vPEafML0Uw5buzRAc4GikxobSkqYVLQvA484TdCkhA== From: Luca Ceresoli Date: Thu, 26 Feb 2026 17:16:46 +0100 Subject: [PATCH 3/3] drm/bridge: ti-sn65dsi83: add test pattern generation support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260226-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v1-3-2e15f5a9a6a0@bootlin.com> References: <20260226-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v1-0-2e15f5a9a6a0@bootlin.com> In-Reply-To: <20260226-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v1-0-2e15f5a9a6a0@bootlin.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Frieder Schrempf , Marek Vasut , Linus Walleij Cc: Thomas Petazzoni , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Luca Ceresoli X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Generation of a test pattern output is a useful tool for panel bringup and debugging, and very simple to support with this chip. The value of REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW needs to be divided by two for the test pattern to work in dual LVDS mode. While not clearly stated in the datasheet, this is needed according to the DSI Tuner [0] output. And some dual-LVDS panels refuse to show any picture without this division by two. [0] https://www.ti.com/tool/DSI-TUNER Signed-off-by: Luca Ceresoli --- drivers/gpu/drm/bridge/ti-sn65dsi83.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge= /ti-sn65dsi83.c index 17a885244e1e..ddc8b5e1dd15 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c @@ -114,6 +114,7 @@ #define REG_VID_CHA_HORIZONTAL_FRONT_PORCH 0x38 #define REG_VID_CHA_VERTICAL_FRONT_PORCH 0x3a #define REG_VID_CHA_TEST_PATTERN 0x3c +#define REG_VID_CHA_TEST_PATTERN_EN BIT(4) /* IRQ registers */ #define REG_IRQ_GLOBAL 0xe0 #define REG_IRQ_GLOBAL_IRQ_EN BIT(0) @@ -134,6 +135,9 @@ #define REG_IRQ_STAT_CHA_SOT_BIT_ERR BIT(2) #define REG_IRQ_STAT_CHA_PLL_UNLOCK BIT(0) =20 +static bool sn65dsi83_test_pattern; +module_param_named(test_pattern, sn65dsi83_test_pattern, bool, 0644); + enum sn65dsi83_channel { CHANNEL_A, CHANNEL_B @@ -645,7 +649,11 @@ static void sn65dsi83_atomic_pre_enable(struct drm_bri= dge *bridge, REG_LVDS_LANE_CHB_LVDS_TERM : 0)); regmap_write(ctx->regmap, REG_LVDS_CM, 0x00); =20 - le16val =3D cpu_to_le16(mode->hdisplay); + /* + * Active line length needs to be halved for test pattern + * generation in dual LVDS output. + */ + le16val =3D cpu_to_le16(mode->hdisplay / (sn65dsi83_test_pattern ? 2 : 1)= ); regmap_bulk_write(ctx->regmap, REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, &le16val, 2); le16val =3D cpu_to_le16(mode->vdisplay); @@ -668,7 +676,8 @@ static void sn65dsi83_atomic_pre_enable(struct drm_brid= ge *bridge, (mode->hsync_start - mode->hdisplay) / dual_factor); regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH, mode->vsync_start - mode->vdisplay); - regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00); + regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, + sn65dsi83_test_pattern ? REG_VID_CHA_TEST_PATTERN_EN : 0); =20 /* Enable PLL */ regmap_write(ctx->regmap, REG_RC_PLL_EN, REG_RC_PLL_EN_PLL_EN); --=20 2.53.0