From nobody Tue Apr 7 18:48:12 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0AB3E355F3B for ; Thu, 26 Feb 2026 16:42:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772124129; cv=none; b=MslQDN6el5zHeK+XcF9gZNciulvrhHgoP6wM3ViYcfFjd6GZN9RNKNeWXnqbcFZWkf4nmuuYvVJtY34XKYSFA0zq7lfgy2ndSyVbaK/xuZ5poGwVH/K+O+K8KUPjZ70GwWEcEmZGe1qJcChQ+49zJIfhYSnqLio1TrlAxQcgQLM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772124129; c=relaxed/simple; bh=RYRy5g8W0Xf7Fu2ii+9Dvn7gs9XC+WhAzXnGhEem1q4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Typ2PT/Au3EJp25qEyGdAkCYTVmlsyi4DSepHMLYm/gq1WZkkF4pYFndwsopPIQ/bDEzIowR17gx1qZ2rgJ+0UdlHZJYw3BFT+P0tazQX7AfScvGthp1PS2q2ATap2YS8eVbPU2P8Bvw0i94mZvWvtK6bAZUMqV4B7/t9iBe+Ww= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=FC3BlTxk; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="FC3BlTxk" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 38463C4069B; Thu, 26 Feb 2026 16:42:15 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id B2DC45FDE9; Thu, 26 Feb 2026 16:41:59 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id D77D6103693DF; Thu, 26 Feb 2026 17:41:56 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1772124118; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=IITRpU+zvv8SCI02oLy3IeJ6AI5N5yaZpXdgBXpsLWg=; b=FC3BlTxkSs3TpfWiGZeTncsVoWzc+wyKHx6XCFipnO6idVeYgGkv0yh/zs2uMkYogaBY12 tomYrSqXn187XFDchwPCBcVIAsEbYn8EVPSJyKn0Nrw8/R3mnDj/ykjNdvyvBunI1ZeO7z ibYOInalPTcQF7eX/XTQDESVmTGf3/KRhyoEJfPhsDS0DVfFmq5BgrCDQo0ieeHbqFSDQB yOphfg8bJzy3eEOUboQf7oquKb/QDZu+Z/mJmpTZL5OyISE/Eh7xXpnMnYrzmwTSV0/LRY HDtSDXAGxJXFfBacoDmI/PE4dQ3MNJpqY7iPQCKkEfT6PK7dEUmZD5oAJ8dXnQ== From: "Bastien Curutchet (Schneider Electric)" Date: Thu, 26 Feb 2026 17:41:48 +0100 Subject: [PATCH net-next v5 1/9] net: dsa: microchip: Add support for KSZ8463 global irq Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260226-ksz8463-ptp-v5-1-1bc24fb9627d@bootlin.com> References: <20260226-ksz8463-ptp-v5-0-1bc24fb9627d@bootlin.com> In-Reply-To: <20260226-ksz8463-ptp-v5-0-1bc24fb9627d@bootlin.com> To: Woojung Huh , UNGLinuxDriver@microchip.com, Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Richard Cochran , Simon Horman Cc: Pascal Eberhard , =?utf-8?q?Miqu=C3=A8l_Raynal?= , Thomas Petazzoni , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, "Bastien Curutchet (Schneider Electric)" , Maxime Chevallier X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 KSZ8463's interrupt scheme differs from the others KSZ swicthes. Its global interrupt handling is done through an 'enable irq' register instead of a 'mask irq' one, so the bit logic to enable/disable interrupt is reversed. Also its interrupts registers are 16-bits registers and don't have the same address. Add ksz8463-specific global interrupt setup function that still relies on the ksz_irq_common_setup(). Add a check on the device type in the irq_chip operations to adjust the bit logic for KSZ8463 Reviewed-by: Maxime Chevallier Signed-off-by: Bastien Curutchet (Schneider Electric) --- drivers/net/dsa/microchip/ksz_common.c | 40 +++++++++++++++++++++++++++++-= ---- drivers/net/dsa/microchip/ksz_common.h | 3 +++ 2 files changed, 37 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/micro= chip/ksz_common.c index c517478cc47677544b6523faee113ece036c9ed9..0102b950e09df7d33c8e429d9b3= 4f51375e0ef73 100644 --- a/drivers/net/dsa/microchip/ksz_common.c +++ b/drivers/net/dsa/microchip/ksz_common.c @@ -2817,14 +2817,20 @@ static void ksz_irq_mask(struct irq_data *d) { struct ksz_irq *kirq =3D irq_data_get_irq_chip_data(d); =20 - kirq->masked |=3D BIT(d->hwirq); + if (ksz_is_ksz8463(kirq->dev)) + kirq->masked &=3D ~BIT(d->hwirq); + else + kirq->masked |=3D BIT(d->hwirq); } =20 static void ksz_irq_unmask(struct irq_data *d) { struct ksz_irq *kirq =3D irq_data_get_irq_chip_data(d); =20 - kirq->masked &=3D ~BIT(d->hwirq); + if (ksz_is_ksz8463(kirq->dev)) + kirq->masked |=3D BIT(d->hwirq); + else + kirq->masked &=3D ~BIT(d->hwirq); } =20 static void ksz_irq_bus_lock(struct irq_data *d) @@ -2840,7 +2846,10 @@ static void ksz_irq_bus_sync_unlock(struct irq_data = *d) struct ksz_device *dev =3D kirq->dev; int ret; =20 - ret =3D ksz_write8(dev, kirq->reg_mask, kirq->masked); + if (ksz_is_ksz8463(dev)) + ret =3D ksz_write16(dev, kirq->reg_mask, kirq->masked); + else + ret =3D ksz_write8(dev, kirq->reg_mask, kirq->masked); if (ret) dev_err(dev->dev, "failed to change IRQ mask\n"); =20 @@ -2890,14 +2899,14 @@ static irqreturn_t ksz_irq_thread_fn(int irq, void = *dev_id) unsigned int nhandled =3D 0; struct ksz_device *dev; unsigned int sub_irq; - u8 data; + u16 data; int ret; u8 n; =20 dev =3D kirq->dev; =20 /* Read interrupt status register */ - ret =3D ksz_read8(dev, kirq->reg_status, &data); + ret =3D ksz_read16(dev, kirq->reg_status, &data); if (ret) goto out; =20 @@ -2939,6 +2948,22 @@ static int ksz_irq_common_setup(struct ksz_device *d= ev, struct ksz_irq *kirq) return ret; } =20 +static int ksz8463_girq_setup(struct dsa_switch *ds) +{ + struct ksz_device *dev =3D ds->priv; + struct ksz_irq *girq =3D &dev->girq; + + girq->nirqs =3D 15; + girq->reg_mask =3D KSZ8463_REG_IER; + girq->reg_status =3D KSZ8463_REG_ISR; + girq->masked =3D 0; + snprintf(girq->name, sizeof(girq->name), "global_irq"); + + girq->irq_num =3D dev->irq; + + return ksz_irq_common_setup(dev, girq); +} + static int ksz_girq_setup(struct ksz_device *dev) { struct ksz_irq *girq =3D &dev->girq; @@ -3044,7 +3069,10 @@ static int ksz_setup(struct dsa_switch *ds) p->learning =3D true; =20 if (dev->irq > 0) { - ret =3D ksz_girq_setup(dev); + if (ksz_is_ksz8463(dev)) + ret =3D ksz8463_girq_setup(ds); + else + ret =3D ksz_girq_setup(dev); if (ret) return ret; =20 diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/micro= chip/ksz_common.h index 929aff4c55de5254defdc1afb52b224b3898233b..67a488a3b5787f93f9e2a9266ce= 04f6611b56bf8 100644 --- a/drivers/net/dsa/microchip/ksz_common.h +++ b/drivers/net/dsa/microchip/ksz_common.h @@ -839,6 +839,9 @@ static inline bool ksz_is_sgmii_port(struct ksz_device = *dev, int port) #define KSZ87XX_INT_PME_MASK BIT(4) =20 /* Interrupt */ +#define KSZ8463_REG_ISR 0x190 +#define KSZ8463_REG_IER 0x192 + #define REG_SW_PORT_INT_STATUS__1 0x001B #define REG_SW_PORT_INT_MASK__1 0x001F =20 --=20 2.53.0