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Thu, 26 Feb 2026 07:47:10 -0800 (PST) From: Alexey Klimov Date: Thu, 26 Feb 2026 15:47:07 +0000 Subject: [PATCH RFC 1/8] dt-bindings: soc: move and rename google,gs101-pmu-intr-gen schema under soc/samsung/ Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260226-exynos850-cpuhotplug-v1-1-71d7c4063382@linaro.org> References: <20260226-exynos850-cpuhotplug-v1-0-71d7c4063382@linaro.org> In-Reply-To: <20260226-exynos850-cpuhotplug-v1-0-71d7c4063382@linaro.org> To: Sam Protsenko , linux-samsung-soc@vger.kernel.org, Krzysztof Kozlowski , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Conor Dooley Cc: Tudor Ambarus , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexey Klimov X-Mailer: b4 0.14.3 The GS101 PMU interrupts generation block is actually a standard Samsung Exynos IP block found in older SoCs like the Exynos 850 and others and not exclusive to Google SoCs. Thus, renaming to samsung,exynos850-pmu-intr-gen, moving the schema file to soc/samsung directory to reflect its origin, since Exynos850 predates GS101 SoCs, and preparing for adding Exynos850 description. Signed-off-by: Alexey Klimov --- .../samsung,exynos850-pmu-intr-gen.yaml} | 4 = ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/google/google,gs101-pmu-= intr-gen.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exyno= s850-pmu-intr-gen.yaml similarity index 80% rename from Documentation/devicetree/bindings/soc/google/google,gs101-pmu-i= ntr-gen.yaml rename to Documentation/devicetree/bindings/soc/samsung/samsung,exynos850-p= mu-intr-gen.yaml index 2be022ca6a7d..f9b40f3fd165 100644 --- a/Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-ge= n.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos850-pmu-i= ntr-gen.yaml @@ -1,10 +1,10 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/soc/google/google,gs101-pmu-intr-gen.ya= ml# +$id: http://devicetree.org/schemas/soc/samsung/samsung,exynos850-pmu-intr-= gen.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Google Power Management Unit (PMU) Interrupt Generation +title: Samsung Power Management Unit (PMU) Interrupt Generation =20 description: | PMU interrupt generator for handshaking between PMU through interrupts. --=20 2.51.0 From nobody Thu Apr 16 17:38:43 2026 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 841953876DD for ; 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Thu, 26 Feb 2026 07:47:11 -0800 (PST) Received: from [127.0.1.1] ([94.4.193.72]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483c3b4410bsm56007365e9.6.2026.02.26.07.47.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Feb 2026 07:47:11 -0800 (PST) From: Alexey Klimov Date: Thu, 26 Feb 2026 15:47:08 +0000 Subject: [PATCH RFC 2/8] dt-bindings: soc: samsung: exynos850-pmu-intr-gen: add Exynos850 compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260226-exynos850-cpuhotplug-v1-2-71d7c4063382@linaro.org> References: <20260226-exynos850-cpuhotplug-v1-0-71d7c4063382@linaro.org> In-Reply-To: <20260226-exynos850-cpuhotplug-v1-0-71d7c4063382@linaro.org> To: Sam Protsenko , linux-samsung-soc@vger.kernel.org, Krzysztof Kozlowski , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Conor Dooley Cc: Tudor Ambarus , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexey Klimov X-Mailer: b4 0.14.3 Add samsung,exynos850-pmu-intr-gen compatible to the bindings documentation. PMU interrupts generator block support is required to enable power management related functionality like CPU hotplug, sleep states, etc. Signed-off-by: Alexey Klimov --- .../bindings/soc/samsung/samsung,exynos850-pmu-intr-gen.yaml | 4 = +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos85= 0-pmu-intr-gen.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung= ,exynos850-pmu-intr-gen.yaml index f9b40f3fd165..df23467d0e0e 100644 --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos850-pmu-i= ntr-gen.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos850-pmu-i= ntr-gen.yaml @@ -15,7 +15,9 @@ maintainers: properties: compatible: items: - - const: google,gs101-pmu-intr-gen + - enum: + - google,gs101-pmu-intr-gen + - samsung,exynos850-pmu-intr-gen - const: syscon =20 reg: --=20 2.51.0 From nobody Thu Apr 16 17:38:43 2026 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DAA9423A7F for ; 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Thu, 26 Feb 2026 07:47:12 -0800 (PST) Received: from [127.0.1.1] ([94.4.193.72]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483c3b4410bsm56007365e9.6.2026.02.26.07.47.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Feb 2026 07:47:12 -0800 (PST) From: Alexey Klimov Date: Thu, 26 Feb 2026 15:47:09 +0000 Subject: [PATCH RFC 3/8] dt-bindings: soc: samsung: exynos-pmu: add samsung,pmu-intr-gen phandle Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260226-exynos850-cpuhotplug-v1-3-71d7c4063382@linaro.org> References: <20260226-exynos850-cpuhotplug-v1-0-71d7c4063382@linaro.org> In-Reply-To: <20260226-exynos850-cpuhotplug-v1-0-71d7c4063382@linaro.org> To: Sam Protsenko , linux-samsung-soc@vger.kernel.org, Krzysztof Kozlowski , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Conor Dooley Cc: Tudor Ambarus , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexey Klimov X-Mailer: b4 0.14.3 Some Exynos-based SoCs, for instance Exynos850, require access to the pmu interrupt generation register region which is exposed as a syscon. Update the exynos-pmu bindings documentation to reflect this. Signed-off-by: Alexey Klimov --- .../devicetree/bindings/soc/samsung/exynos-pmu.yaml | 18 ++++++++++++++= ++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml = b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index 76ce7e98c10f..92acdfd5d44e 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -110,6 +110,11 @@ properties: description: Node for reboot method =20 + samsung,pmu-intr-gen-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to PMU interrupt generation interface. + google,pmu-intr-gen-syscon: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -189,6 +194,19 @@ allOf: properties: google,pmu-intr-gen-syscon: false =20 + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos850-pmu + then: + required: + - samsung,pmu-intr-gen-syscon + else: + properties: + samsung,pmu-intr-gen-syscon: false + examples: - | #include --=20 2.51.0 From nobody Thu Apr 16 17:38:43 2026 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0D403876BB for ; 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Thu, 26 Feb 2026 07:47:14 -0800 (PST) Received: from [127.0.1.1] ([94.4.193.72]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483c3b4410bsm56007365e9.6.2026.02.26.07.47.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Feb 2026 07:47:13 -0800 (PST) From: Alexey Klimov Date: Thu, 26 Feb 2026 15:47:10 +0000 Subject: [PATCH RFC 4/8] dt-bindings: soc: samsung: exynos-pmu: deprecate google,pmu-intr-gen-syscon Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260226-exynos850-cpuhotplug-v1-4-71d7c4063382@linaro.org> References: <20260226-exynos850-cpuhotplug-v1-0-71d7c4063382@linaro.org> In-Reply-To: <20260226-exynos850-cpuhotplug-v1-0-71d7c4063382@linaro.org> To: Sam Protsenko , linux-samsung-soc@vger.kernel.org, Krzysztof Kozlowski , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Conor Dooley Cc: Tudor Ambarus , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexey Klimov X-Mailer: b4 0.14.3 The generic property samsung,pmu-intr-gen-syscon should be used by default for Samsung Exynos PMU hardware blocks. Update binding document to add deprecated flag for google,pmu-intr-gen-syscon property. While at this, also add dependency to not allow usage of both above mentioned properties in the same time. Signed-off-by: Alexey Klimov --- Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml = b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index 92acdfd5d44e..1ff1a8729989 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -119,6 +119,7 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle description: Phandle to PMU interrupt generation interface. + deprecated: true =20 required: - compatible @@ -207,6 +208,11 @@ allOf: properties: samsung,pmu-intr-gen-syscon: false =20 +dependencies: + google,pmu-intr-gen-syscon: + not: + required: ['samsung,pmu-intr-gen-syscon'] + examples: - | #include --=20 2.51.0 From nobody Thu Apr 16 17:38:43 2026 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 173CA387588 for ; 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Thu, 26 Feb 2026 07:47:15 -0800 (PST) Received: from [127.0.1.1] ([94.4.193.72]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483c3b4410bsm56007365e9.6.2026.02.26.07.47.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Feb 2026 07:47:14 -0800 (PST) From: Alexey Klimov Date: Thu, 26 Feb 2026 15:47:11 +0000 Subject: [PATCH RFC 5/8] soc: samsung: exynos-pmu: rename GS101_INTR_* regs to EXYNOS_INTR_* Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260226-exynos850-cpuhotplug-v1-5-71d7c4063382@linaro.org> References: <20260226-exynos850-cpuhotplug-v1-0-71d7c4063382@linaro.org> In-Reply-To: <20260226-exynos850-cpuhotplug-v1-0-71d7c4063382@linaro.org> To: Sam Protsenko , linux-samsung-soc@vger.kernel.org, Krzysztof Kozlowski , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Conor Dooley Cc: Tudor Ambarus , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexey Klimov X-Mailer: b4 0.14.3 The PMU interrupt generation block is not exclusive to gs101 SoCs and is present on few Exynos-based platforms. Rename registers of this hardware block prefixed with GS101_INTR to be prefixed with EXYNOS_INTR. Signed-off-by: Alexey Klimov --- drivers/soc/samsung/exynos-pmu.c | 16 ++++++++-------- include/linux/soc/samsung/exynos-regs-pmu.h | 10 +++++----- 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-= pmu.c index d58376c38179..92870e6ffc1c 100644 --- a/drivers/soc/samsung/exynos-pmu.c +++ b/drivers/soc/samsung/exynos-pmu.c @@ -244,12 +244,12 @@ static int __gs101_cpu_pmu_online(unsigned int cpu) =20 mask =3D BIT(cpu); =20 - regmap_update_bits(pmu_context->pmuintrgen, GS101_GRP2_INTR_BID_ENABLE, + regmap_update_bits(pmu_context->pmuintrgen, EXYNOS_GRP2_INTR_BID_ENABLE, mask, (0 << cpu)); =20 - regmap_read(pmu_context->pmuintrgen, GS101_GRP2_INTR_BID_UPEND, ®); + regmap_read(pmu_context->pmuintrgen, EXYNOS_GRP2_INTR_BID_UPEND, ®); =20 - regmap_write(pmu_context->pmuintrgen, GS101_GRP2_INTR_BID_CLEAR, + regmap_write(pmu_context->pmuintrgen, EXYNOS_GRP2_INTR_BID_CLEAR, reg & mask); =20 return 0; @@ -304,16 +304,16 @@ static int __gs101_cpu_pmu_offline(unsigned int cpu) CPU_INFORM_C2); =20 mask =3D BIT(cpu); - regmap_update_bits(pmu_context->pmuintrgen, GS101_GRP2_INTR_BID_ENABLE, + regmap_update_bits(pmu_context->pmuintrgen, EXYNOS_GRP2_INTR_BID_ENABLE, mask, BIT(cpu)); =20 - regmap_read(pmu_context->pmuintrgen, GS101_GRP1_INTR_BID_UPEND, ®); - regmap_write(pmu_context->pmuintrgen, GS101_GRP1_INTR_BID_CLEAR, + regmap_read(pmu_context->pmuintrgen, EXYNOS_GRP1_INTR_BID_UPEND, ®); + regmap_write(pmu_context->pmuintrgen, EXYNOS_GRP1_INTR_BID_CLEAR, reg & mask); =20 mask =3D (BIT(cpu + 8)); - regmap_read(pmu_context->pmuintrgen, GS101_GRP1_INTR_BID_UPEND, ®); - regmap_write(pmu_context->pmuintrgen, GS101_GRP1_INTR_BID_CLEAR, + regmap_read(pmu_context->pmuintrgen, EXYNOS_GRP1_INTR_BID_UPEND, ®); + regmap_write(pmu_context->pmuintrgen, EXYNOS_GRP1_INTR_BID_CLEAR, reg & mask); =20 return 0; diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/so= c/samsung/exynos-regs-pmu.h index db8a7ca81080..9c4d3da41dbf 100644 --- a/include/linux/soc/samsung/exynos-regs-pmu.h +++ b/include/linux/soc/samsung/exynos-regs-pmu.h @@ -1009,11 +1009,11 @@ #define GS101_PHY_CTRL_UFS 0x3ec8 =20 /* PMU INTR GEN */ -#define GS101_GRP1_INTR_BID_UPEND (0x0108) -#define GS101_GRP1_INTR_BID_CLEAR (0x010c) -#define GS101_GRP2_INTR_BID_ENABLE (0x0200) -#define GS101_GRP2_INTR_BID_UPEND (0x0208) -#define GS101_GRP2_INTR_BID_CLEAR (0x020c) +#define EXYNOS_GRP1_INTR_BID_UPEND (0x0108) +#define EXYNOS_GRP1_INTR_BID_CLEAR (0x010c) +#define EXYNOS_GRP2_INTR_BID_ENABLE (0x0200) +#define EXYNOS_GRP2_INTR_BID_UPEND (0x0208) +#define EXYNOS_GRP2_INTR_BID_CLEAR (0x020c) =20 /* exynosautov920 */ #define EXYNOSAUTOV920_PHY_CTRL_USB20 (0x0710) --=20 2.51.0 From nobody Thu Apr 16 17:38:43 2026 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E6AC425CCF for ; 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Thu, 26 Feb 2026 07:47:16 -0800 (PST) Received: from [127.0.1.1] ([94.4.193.72]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483c3b4410bsm56007365e9.6.2026.02.26.07.47.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Feb 2026 07:47:15 -0800 (PST) From: Alexey Klimov Date: Thu, 26 Feb 2026 15:47:12 +0000 Subject: [PATCH RFC 6/8] soc: samsung: exynos-pmu: generalise GS101 PMU intr gen for Exynos SoCs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260226-exynos850-cpuhotplug-v1-6-71d7c4063382@linaro.org> References: <20260226-exynos850-cpuhotplug-v1-0-71d7c4063382@linaro.org> In-Reply-To: <20260226-exynos850-cpuhotplug-v1-0-71d7c4063382@linaro.org> To: Sam Protsenko , linux-samsung-soc@vger.kernel.org, Krzysztof Kozlowski , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Conor Dooley Cc: Tudor Ambarus , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexey Klimov X-Mailer: b4 0.14.3 The GS101 PMU interrupts generation block is not exclusive to Google GS101 SoCs and is a standard Exynos IP block found in different older SoCs like Exynos850 and others. To prepare for the addition of Exynos850 PMU interrupts generation block and cpu hotplug support we need to generalise (Exynosize or Exynosify) names and calls related to CPU hotplug and CPU idle. pmu_context struct has now calls to offline and online procedures which are SoC specific (and maybe even firmware-specific for any given board), and one of this set of {offline,online} calls becomes GS101-specific. This allows adding calls for other boards later. Signed-off-by: Alexey Klimov --- drivers/soc/samsung/exynos-pmu.c | 39 ++++++++++++++++++++++--------------= --- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-= pmu.c index 92870e6ffc1c..0967fa56708a 100644 --- a/drivers/soc/samsung/exynos-pmu.c +++ b/drivers/soc/samsung/exynos-pmu.c @@ -36,6 +36,8 @@ struct exynos_pmu_context { */ raw_spinlock_t cpupm_lock; unsigned long *in_cpuhp; + int (*cpu_pmu_offline)(unsigned int cpu); + int (*cpu_pmu_online)(unsigned int cpu); bool sys_insuspend; bool sys_inreboot; }; @@ -256,7 +258,7 @@ static int __gs101_cpu_pmu_online(unsigned int cpu) } =20 /* Called from CPU PM notifier (CPUIdle code path) with IRQs disabled */ -static int gs101_cpu_pmu_online(void) +static int exynos_cpu_pmu_online(void) { int cpu; =20 @@ -268,20 +270,20 @@ static int gs101_cpu_pmu_online(void) } =20 cpu =3D smp_processor_id(); - __gs101_cpu_pmu_online(cpu); + pmu_context->cpu_pmu_online(cpu); raw_spin_unlock(&pmu_context->cpupm_lock); =20 return NOTIFY_OK; } =20 /* Called from CPU hot plug callback with IRQs enabled */ -static int gs101_cpuhp_pmu_online(unsigned int cpu) +static int exynos_cpuhp_pmu_online(unsigned int cpu) { unsigned long flags; =20 raw_spin_lock_irqsave(&pmu_context->cpupm_lock, flags); =20 - __gs101_cpu_pmu_online(cpu); + pmu_context->cpu_pmu_online(cpu); /* * Mark this CPU as having finished the hotplug. * This means this CPU can now enter C2 idle state. @@ -320,7 +322,7 @@ static int __gs101_cpu_pmu_offline(unsigned int cpu) } =20 /* Called from CPU PM notifier (CPUIdle code path) with IRQs disabled */ -static int gs101_cpu_pmu_offline(void) +static int exynos_cpu_pmu_offline(void) { int cpu; =20 @@ -338,14 +340,14 @@ static int gs101_cpu_pmu_offline(void) return NOTIFY_OK; } =20 - __gs101_cpu_pmu_offline(cpu); + pmu_context->cpu_pmu_offline(cpu); raw_spin_unlock(&pmu_context->cpupm_lock); =20 return NOTIFY_OK; } =20 /* Called from CPU hot plug callback with IRQs enabled */ -static int gs101_cpuhp_pmu_offline(unsigned int cpu) +static int exynos_cpuhp_pmu_offline(unsigned int cpu) { unsigned long flags; =20 @@ -355,29 +357,29 @@ static int gs101_cpuhp_pmu_offline(unsigned int cpu) * ACPM the CPU entering hotplug should not enter C2 idle state. */ set_bit(cpu, pmu_context->in_cpuhp); - __gs101_cpu_pmu_offline(cpu); + pmu_context->cpu_pmu_offline(cpu); =20 raw_spin_unlock_irqrestore(&pmu_context->cpupm_lock, flags); =20 return 0; } =20 -static int gs101_cpu_pm_notify_callback(struct notifier_block *self, +static int exynos_cpu_pm_notify_callback(struct notifier_block *self, unsigned long action, void *v) { switch (action) { case CPU_PM_ENTER: - return gs101_cpu_pmu_offline(); + return exynos_cpu_pmu_offline(); =20 case CPU_PM_EXIT: - return gs101_cpu_pmu_online(); + return exynos_cpu_pmu_online(); } =20 return NOTIFY_OK; } =20 -static struct notifier_block gs101_cpu_pm_notifier =3D { - .notifier_call =3D gs101_cpu_pm_notify_callback, +static struct notifier_block exynos_cpu_pm_notifier =3D { + .notifier_call =3D exynos_cpu_pm_notify_callback, /* * We want to be called first, as the ACPM hint and handshake is what * puts the CPU into C2. @@ -425,6 +427,9 @@ static int setup_cpuhp_and_cpuidle(struct device *dev) return 0; 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Thu, 26 Feb 2026 07:47:17 -0800 (PST) Received: from [127.0.1.1] ([94.4.193.72]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483c3b4410bsm56007365e9.6.2026.02.26.07.47.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Feb 2026 07:47:16 -0800 (PST) From: Alexey Klimov Date: Thu, 26 Feb 2026 15:47:13 +0000 Subject: [PATCH RFC 7/8] soc: samsung: exynos-pmu: add Exynos850 CPU hotplug support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260226-exynos850-cpuhotplug-v1-7-71d7c4063382@linaro.org> References: <20260226-exynos850-cpuhotplug-v1-0-71d7c4063382@linaro.org> In-Reply-To: <20260226-exynos850-cpuhotplug-v1-0-71d7c4063382@linaro.org> To: Sam Protsenko , linux-samsung-soc@vger.kernel.org, Krzysztof Kozlowski , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Conor Dooley Cc: Tudor Ambarus , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexey Klimov X-Mailer: b4 0.14.3 Some Exynos-based SoCs require specific set of writes/updates to PMU and PMU intr gen blocks in order to put a CPU or a group of CPUs into a different sleep states or prepare these entities for a CPU_OFF. The same is valid for a reverse procedures like wake-ups or CPU(s) online. Without these writes/updates the CPU(s) wake-up or online fails. Add support for Exynos850-based SoCs for PMU and PMU intr gen write/update sequences. While at this, also add description of Exynos850 PMU registers. Signed-off-by: Alexey Klimov --- drivers/soc/samsung/exynos-pmu.c | 86 +++++++++++++++++++++++++= ++-- include/linux/soc/samsung/exynos-regs-pmu.h | 5 ++ 2 files changed, 87 insertions(+), 4 deletions(-) diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-= pmu.c index 0967fa56708a..7b9b8e22d91b 100644 --- a/drivers/soc/samsung/exynos-pmu.c +++ b/drivers/soc/samsung/exynos-pmu.c @@ -118,6 +118,10 @@ static const struct regmap_config regmap_pmu_intr =3D { .use_raw_spinlock =3D true, }; =20 +const struct exynos_pmu_data exynos850_pmu_data =3D { + .pmu_cpuhp =3D true, +}; + /* * PMU platform driver and devicetree bindings. */ @@ -151,6 +155,7 @@ static const struct of_device_id exynos_pmu_of_device_i= ds[] =3D { .compatible =3D "samsung,exynos7-pmu", }, { .compatible =3D "samsung,exynos850-pmu", + .data =3D &exynos850_pmu_data, }, { /*sentinel*/ }, }; @@ -229,6 +234,65 @@ EXPORT_SYMBOL_GPL(exynos_get_pmu_regmap_by_phandle); #define CPU_INFORM_CLEAR 0 #define CPU_INFORM_C2 1 =20 +static int __exynos850_cpu_pmu_online(unsigned int cpu) + __must_hold(&pmu_context->cpupm_lock) +{ + u32 this_cluster =3D MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 2); + u32 cluster_cpu =3D MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1); + unsigned int cpuhint =3D smp_processor_id(); + u32 reg, mask; + + /* clear cpu inform hint */ + regmap_write(pmu_context->pmureg, EXYNOS850_CPU_INFORM(cpuhint), + CPU_INFORM_CLEAR); + + mask =3D BIT(cpu); + + regmap_update_bits(pmu_context->pmuintrgen, EXYNOS_GRP2_INTR_BID_ENABLE, + mask, (0 << cpu)); + + regmap_read(pmu_context->pmuintrgen, EXYNOS_GRP2_INTR_BID_UPEND, ®); + + regmap_write(pmu_context->pmuintrgen, EXYNOS_GRP2_INTR_BID_CLEAR, + reg & mask); + + regmap_update_bits(pmu_context->pmureg, + EXYNOS850_CLUSTER_CPU_INT_EN(this_cluster, cluster_cpu), + 1 << 3, 0 << 3); + return 0; +} + +static int __exynos850_cpu_pmu_offline(unsigned int cpu) + __must_hold(&pmu_context->cpupm_lock) +{ + u32 this_cluster =3D MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 2); + u32 cluster_cpu =3D MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1); + unsigned int cpuhint =3D smp_processor_id(); + u32 reg, mask; + + /* set cpu inform hint */ + regmap_write(pmu_context->pmureg, EXYNOS850_CPU_INFORM(cpuhint), + CPU_INFORM_C2); + + mask =3D BIT(cpu); + regmap_update_bits(pmu_context->pmuintrgen, EXYNOS_GRP2_INTR_BID_ENABLE, + mask, BIT(cpu)); + + regmap_read(pmu_context->pmuintrgen, EXYNOS_GRP1_INTR_BID_UPEND, ®); + regmap_write(pmu_context->pmuintrgen, EXYNOS_GRP1_INTR_BID_CLEAR, + reg & mask); + + mask =3D (BIT(cpu + 8)); + regmap_read(pmu_context->pmuintrgen, EXYNOS_GRP1_INTR_BID_UPEND, ®); + regmap_write(pmu_context->pmuintrgen, EXYNOS_GRP1_INTR_BID_CLEAR, + reg & mask); + + regmap_update_bits(pmu_context->pmureg, + EXYNOS850_CLUSTER_CPU_INT_EN(this_cluster, cluster_cpu), + 1 << 3, 1 << 3); + return 0; +} + /* * __gs101_cpu_pmu_ prefix functions are common code shared by CPU PM noti= fiers * (CPUIdle) and CPU hotplug callbacks. Functions should be called with IR= Qs @@ -416,8 +480,12 @@ static int setup_cpuhp_and_cpuidle(struct device *dev) void __iomem *virt_addr; int ret, cpu; =20 - intr_gen_node =3D of_parse_phandle(dev->of_node, - "google,pmu-intr-gen-syscon", 0); + intr_gen_node =3D of_parse_phandle(dev->of_node, "samsung,pmu-intr-gen-sy= scon", 0); + + /* Fall back to the google pmu intr gen property for older DTBs */ + if (!intr_gen_node) + intr_gen_node =3D of_parse_phandle(dev->of_node, "google,pmu-intr-gen-sy= scon", 0); + if (!intr_gen_node) { /* * To maintain support for older DTs that didn't specify syscon @@ -427,9 +495,19 @@ static int setup_cpuhp_and_cpuidle(struct device *dev) return 0; } =20 - pmu_context->cpu_pmu_online =3D __gs101_cpu_pmu_online; - pmu_context->cpu_pmu_offline =3D __gs101_cpu_pmu_offline; + if (of_machine_is_compatible("google,gs101")) { + pmu_context->cpu_pmu_online =3D __gs101_cpu_pmu_online; + pmu_context->cpu_pmu_offline =3D __gs101_cpu_pmu_offline; + } + + if (of_machine_is_compatible("samsung,exynos850")) { + pmu_context->cpu_pmu_online =3D __exynos850_cpu_pmu_online; + pmu_context->cpu_pmu_offline =3D __exynos850_cpu_pmu_offline; =20 + } else { + dev_err(dev, "pmu-intr-gen is present but machine is not supported\n"); + return -ENODEV; + } /* * To avoid lockdep issues (CPU PM notifiers use raw spinlocks) create * a mmio regmap for pmu-intr-gen that uses raw spinlocks instead of diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/so= c/samsung/exynos-regs-pmu.h index 9c4d3da41dbf..93c4d724c8ea 100644 --- a/include/linux/soc/samsung/exynos-regs-pmu.h +++ b/include/linux/soc/samsung/exynos-regs-pmu.h @@ -1015,6 +1015,11 @@ #define EXYNOS_GRP2_INTR_BID_UPEND (0x0208) #define EXYNOS_GRP2_INTR_BID_CLEAR (0x020c) =20 +/* Exynos850 PMU Alive */ +#define EXYNOS850_CPU_INFORM(cpu) (0x0860 + ((cpu) & 7) * 4) +#define EXYNOS850_CLUSTER_CPU_OFFSET(cl, cpu) (0x1000 + ((cl * 0x400) + ((= cpu) * 0x80))) +#define EXYNOS850_CLUSTER_CPU_INT_EN(cl, cpu) (EXYNOS850_CLUSTER_CPU_OFFSE= T(cl, cpu) + 0x44) + /* exynosautov920 */ #define EXYNOSAUTOV920_PHY_CTRL_USB20 (0x0710) #define EXYNOSAUTOV920_PHY_CTRL_USB31 (0x0714) --=20 2.51.0 From nobody Thu Apr 16 17:38:43 2026 Received: from mail-wm1-f68.google.com (mail-wm1-f68.google.com [209.85.128.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 174B4425CE0 for ; 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Thu, 26 Feb 2026 07:47:18 -0800 (PST) Received: from [127.0.1.1] ([94.4.193.72]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483c3b4410bsm56007365e9.6.2026.02.26.07.47.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Feb 2026 07:47:17 -0800 (PST) From: Alexey Klimov Date: Thu, 26 Feb 2026 15:47:14 +0000 Subject: [PATCH RFC 8/8] arm64: dts: exynos850: add PMU interrupt generation node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260226-exynos850-cpuhotplug-v1-8-71d7c4063382@linaro.org> References: <20260226-exynos850-cpuhotplug-v1-0-71d7c4063382@linaro.org> In-Reply-To: <20260226-exynos850-cpuhotplug-v1-0-71d7c4063382@linaro.org> To: Sam Protsenko , linux-samsung-soc@vger.kernel.org, Krzysztof Kozlowski , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Conor Dooley Cc: Tudor Ambarus , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexey Klimov X-Mailer: b4 0.14.3 Add pmu_intr_gen node for Exynos850. This hw block is required for different power management routines like CPU hotplug and different sleep and idle states. Also reference this node from main PMU node. Signed-off-by: Alexey Klimov --- arch/arm64/boot/dts/exynos/exynos850.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dt= s/exynos/exynos850.dtsi index cb55015c8dce..e3f4fe6ee118 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -211,9 +211,15 @@ gic: interrupt-controller@12a01000 { IRQ_TYPE_LEVEL_HIGH)>; }; =20 + pmu_intr_gen: syscon@11870000 { + compatible =3D "samsung,exynos850-pmu-intr-gen", "syscon"; + reg =3D <0x11870000 0x10000>; + }; + pmu_system_controller: system-controller@11860000 { compatible =3D "samsung,exynos850-pmu", "syscon"; reg =3D <0x11860000 0x10000>; + samsung,pmu-intr-gen-syscon =3D <&pmu_intr_gen>; =20 reboot: syscon-reboot { compatible =3D "syscon-reboot"; --=20 2.51.0