From nobody Tue Apr 7 17:16:54 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 83CDC396D24; Thu, 26 Feb 2026 08:54:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772096055; cv=none; b=h8mRVIoxMgNszY6rqKVJjm7Rd2m1G/JWvW+v6TnQl76ynSjIMwyya+I7YJv/R2laO3xY4OaLu1adX7oo/LVJa8k7bTCh6soWX61NIOpnSc88x4bEwJUyEIZstVAzYuEsEeh850SAIhPY+s1+LxyJ929H162FYxVA/7xJlS0Ajbc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772096055; c=relaxed/simple; bh=tVDFFZNNq+3cx8vwsO+uDpr3OUAYyGNXUn5yFrn4B/A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EL8WU6TsRSFjXSIoGAYrQTOvu4cvN9aMVtWHYZzlBtOrUueqT9b/Hw4v+uSNlo2UXUhEkSxS1QJN+aUqaMNSYly/yhVhKiICEXL/SEyme8dxjbr4rU4F11/ZRhZgCXyB70LPbKBgYHDq3m8V3gE5v0tvg7WW17rKIWH9WdIRSEE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NBmEEySy; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NBmEEySy" Received: by smtp.kernel.org (Postfix) with ESMTPS id 47EF5C2BCB1; Thu, 26 Feb 2026 08:54:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772096055; bh=tVDFFZNNq+3cx8vwsO+uDpr3OUAYyGNXUn5yFrn4B/A=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=NBmEEySyjir0pNKDyl8fZ8qAfnmFnYbxr9lDgyxpvgXoQ/+zgaz0MfudOEH09W4hh M8rKq+oPF9Ehx6tzMETgWhGSmhd0oUHM7dkoG8CpItZ2N3H5a1y94rWWpuk3Y4H/0L rMXHs4PkPLV7UPPdAawLMLfnnR1WYblzIhRQ7xtLkuO57pce3vmUxZZtSIF8do9DoC 9ejFCjVFFUViZjGdJFxUt7o4fSRWm4wIUpQx4D3TbOb2R4KfvufJov1AiyVp3l3zWM lAYtpBL7a1iF63GMo23vxuhIgAoTKjY2L/Hvfjy3OMI6rapDSqn3KFgLevqlwAuFv/ nlec5xtKVfZcA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38AF2FC5916; Thu, 26 Feb 2026 08:54:15 +0000 (UTC) From: Jan Petrous via B4 Relay Date: Thu, 26 Feb 2026 09:54:09 +0100 Subject: [PATCH v7 4/5] dt-bindings: net: nxp,s32-dwmac: Declare per-queue interrupts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260226-dwmac_multi_irq-v7-4-f8fe3b945bb4@oss.nxp.com> References: <20260226-dwmac_multi_irq-v7-0-f8fe3b945bb4@oss.nxp.com> In-Reply-To: <20260226-dwmac_multi_irq-v7-0-f8fe3b945bb4@oss.nxp.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, rmk+kernel@armlinux.org.uk, vladimir.oltean@nxp.com, boon.khai.ng@altera.com, "Jan Petrous (OSS)" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772096053; l=3455; i=jan.petrous@oss.nxp.com; s=20240922; h=from:subject:message-id; bh=Ulgz8SoBFJZWXNyBqoPUpgpX/c4gObaapFU2nTXzIJo=; b=UT9Qnilg/WovbJ350EVFkkHtyTiIJ/8YySev0ZAZqayVGhbPMzLEiSpapf65FmRkFN42GTtjD jsQfEpx3uCsAnn+P+DQUXtsW/Pt4oKRObdxxyWJxA2CxT7ahzuivfgj X-Developer-Key: i=jan.petrous@oss.nxp.com; a=ed25519; pk=Ke3wwK7rb2Me9UQRf6vR8AsfJZfhTyoDaxkUCqmSWYY= X-Endpoint-Received: by B4 Relay for jan.petrous@oss.nxp.com/20240922 with auth_id=217 X-Original-From: "Jan Petrous (OSS)" Reply-To: jan.petrous@oss.nxp.com From: "Jan Petrous (OSS)" The DWMAC IP on NXP S32G/R SoCs has connected queue-based IRQ lines, set them to allow using Multi-IRQ mode. Reviewed-by: Matthias Brugger Reviewed-by: Rob Herring (Arm) Signed-off-by: Jan Petrous (OSS) --- .../devicetree/bindings/net/nxp,s32-dwmac.yaml | 44 ++++++++++++++++++= +--- 1 file changed, 39 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Doc= umentation/devicetree/bindings/net/nxp,s32-dwmac.yaml index 1b2934f3c87c..3a0e41b63c3d 100644 --- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -# Copyright 2021-2024 NXP +# Copyright 2021-2026 NXP %YAML 1.2 --- $id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml# @@ -16,6 +16,8 @@ description: the SoC S32R45 has two instances. The devices can use RGMII/RMII/MII interface over Pinctrl device or the output can be routed to the embedded SerDes for SGMII connectivity. + The DWMAC instances have connected all RX/TX queues interrupts, + enabling load balancing of data traffic across all CPU cores. =20 properties: compatible: @@ -45,10 +47,22 @@ properties: FlexTimer Modules connect to GMAC_0. =20 interrupts: - maxItems: 1 + minItems: 11 + maxItems: 11 =20 interrupt-names: - const: macirq + items: + - const: macirq + - const: tx-queue-0 + - const: rx-queue-0 + - const: tx-queue-1 + - const: rx-queue-1 + - const: tx-queue-2 + - const: rx-queue-2 + - const: tx-queue-3 + - const: rx-queue-3 + - const: tx-queue-4 + - const: rx-queue-4 =20 clocks: items: @@ -88,8 +102,28 @@ examples: <0x0 0x4007c004 0x0 0x4>; /* GMAC_0_CTRL_STS */ nxp,phy-sel =3D <&gpr 0x4>; interrupt-parent =3D <&gic>; - interrupts =3D ; - interrupt-names =3D "macirq"; + interrupts =3D , + /* CHN 0: tx, rx */ + , + , + /* CHN 1: tx, rx */ + , + , + /* CHN 2: tx, rx */ + , + , + /* CHN 3: tx, rx */ + , + , + /* CHN 4: tx, rx */ + , + ; + interrupt-names =3D "macirq", + "tx-queue-0", "rx-queue-0", + "tx-queue-1", "rx-queue-1", + "tx-queue-2", "rx-queue-2", + "tx-queue-3", "rx-queue-3", + "tx-queue-4", "rx-queue-4"; snps,mtl-rx-config =3D <&mtl_rx_setup>; snps,mtl-tx-config =3D <&mtl_tx_setup>; clocks =3D <&clks 24>, <&clks 17>, <&clks 16>, <&clks 15>; --=20 2.47.0