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Thu, 26 Feb 2026 11:31:36 +0100 From: Gatien Chevallier Date: Thu, 26 Feb 2026 11:30:22 +0100 Subject: [PATCH v6 07/12] arm: dts: stm32: introduce the debug bus for stm32mp1x platforms Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260226-debug_bus-v6-7-5d794697798d@foss.st.com> References: <20260226-debug_bus-v6-0-5d794697798d@foss.st.com> In-Reply-To: <20260226-debug_bus-v6-0-5d794697798d@foss.st.com> To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Leo Yan , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= , Linus Walleij , "Maxime Coquelin" , Alexandre Torgue , , , , Sudeep Holla CC: , , , , , , Gatien Chevallier , Antonio Borneo X-Mailer: b4 0.14.3 X-ClientProxiedBy: STKCAS1NODE1.st.com (10.75.128.134) To STKDAG1NODE2.st.com (10.75.128.133) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM3PEPF00009B9B:EE_|AM7PR10MB3543:EE_ X-MS-Office365-Filtering-Correlation-Id: 3e23c5a9-cbe8-434a-73a8-08de752238a2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014|7416014|921020; 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Introduce a debug bus that will check the debug subsystem accessibility before probing these peripheral drivers. Add Coresight peripheral nodes under this bus and add the appropriate access-controllers property to the HDP node. Signed-off-by: Antonio Borneo Signed-off-by: Gatien Chevallier --- arch/arm/boot/dts/st/stm32mp131.dtsi | 117 ++++++++++++++++++++++++ arch/arm/boot/dts/st/stm32mp151.dtsi | 172 +++++++++++++++++++++++++++++++= ++++ arch/arm/boot/dts/st/stm32mp153.dtsi | 68 ++++++++++++++ 3 files changed, 357 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/st= m32mp131.dtsi index b9657ff91c23..a2513d55499f 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -3,6 +3,7 @@ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved * Author: Alexandre Torgue for STMicroelec= tronics. */ +#include #include #include #include @@ -964,9 +965,125 @@ hdp: pinctrl@5002a000 { compatible =3D "st,stm32mp131-hdp"; reg =3D <0x5002a000 0x400>; clocks =3D <&rcc HDP>; + access-controllers =3D <&dbg_bus 1>; status =3D "disabled"; }; =20 + dbg_bus: bus@50080000 { + compatible =3D "st,stm32mp131-dbg-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + #access-controller-cells =3D <1>; + ranges =3D <0x50080000 0x50080000 0x3f80000>; + status =3D "disabled"; + + cs_etf: etf@50092000 { + compatible =3D "arm,coresight-tmc", "arm,primecell"; + reg =3D <0x50092000 0x1000>; + clocks =3D <&rcc CK_DBG>; + clock-names =3D "apb_pclk"; + access-controllers =3D <&dbg_bus 0>; + status =3D "disabled"; + + in-ports { + port { + etf_in_port: endpoint { + remote-endpoint =3D <&etm0_out_port>; + }; + }; + }; + + out-ports { + port { + etf_out_port: endpoint { + remote-endpoint =3D <&tpiu_in_port>; + }; + }; + }; + }; + + cs_tpiu: tpiu@50093000 { + compatible =3D "arm,coresight-tpiu", "arm,primecell"; + reg =3D <0x50093000 0x1000>; + clocks =3D <&rcc CK_DBG>, <&rcc CK_TRACE>; + clock-names =3D "apb_pclk", "atclk"; + access-controllers =3D <&dbg_bus 0>; + status =3D "disabled"; + + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint =3D <&etf_out_port>; + }; + }; + }; + }; + + cs_cti_trace: cti@50094000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x50094000 0x1000>; + clocks =3D <&rcc CK_DBG>; + clock-names =3D "apb_pclk"; + access-controllers =3D <&dbg_bus 0>; + status =3D "disabled"; + }; + + cs_cti_cpu0: cti@500d8000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x500d8000 0x1000>; + clocks =3D <&rcc CK_DBG>; + clock-names =3D "apb_pclk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&dbg_bus 0>; + status =3D "disabled"; + + trig-conns@0 { + reg =3D <0>; + arm,trig-in-sigs =3D <0 4 5>; + arm,trig-in-types =3D ; + arm,trig-out-sigs =3D <0 7>; + arm,trig-out-types =3D ; + cpu =3D <&cpu0>; + }; + + trig-conns@2 { + reg =3D <2>; + arm,trig-in-sigs =3D <2 3 6>; + arm,trig-in-types =3D ; + arm,trig-out-sigs =3D <1 2 3 4>; + arm,trig-out-types =3D ; + arm,cs-dev-assoc =3D <&cs_etm0>; + }; + }; + + cs_etm0: etm@500dc000 { + compatible =3D "arm,coresight-etm3x", "arm,primecell"; + reg =3D <0x500dc000 0x1000>; + cpu =3D <&cpu0>; + clocks =3D <&rcc CK_DBG>, <&rcc CK_TRACE>; + clock-names =3D "apb_pclk", "atclk"; + access-controllers =3D <&dbg_bus 0>; + status =3D "disabled"; + + out-ports { + port { + etm0_out_port: endpoint { + remote-endpoint =3D <&etf_in_port>; + }; + }; + }; + }; + }; + mdma: dma-controller@58000000 { compatible =3D "st,stm32h7-mdma"; reg =3D <0x58000000 0x1000>; diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/st= m32mp151.dtsi index b1b568dfd126..1580fdcfb772 100644 --- a/arch/arm/boot/dts/st/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -3,6 +3,7 @@ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved * Author: Ludovic Barre for STMicroelectronics. */ +#include #include #include #include @@ -274,9 +275,180 @@ hdp: pinctrl@5002a000 { compatible =3D "st,stm32mp151-hdp"; reg =3D <0x5002a000 0x400>; clocks =3D <&rcc HDP>; + access-controllers =3D <&dbg_bus 1>; status =3D "disabled"; }; =20 + dbg_bus: bus@50080000 { + compatible =3D "st,stm32mp151-dbg-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + #access-controller-cells =3D <1>; + ranges =3D <0x50080000 0x50080000 0x3f80000>, + <0x90000000 0x90000000 0x1000000>; + status =3D "disabled"; + + cs_funnel: funnel@50091000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0x50091000 0x1000>; + clocks =3D <&rcc CK_DBG>, <&rcc CK_TRACE>; + clock-names =3D "apb_pclk", "atclk"; + access-controllers =3D <&dbg_bus 0>; + status =3D "disabled"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + port@0 { + reg =3D <0>; + funnel_in_port0: endpoint { + remote-endpoint =3D <&stm_out_port>; + }; + }; + + port@1 { + reg =3D <1>; + funnel_in_port1: endpoint { + remote-endpoint =3D <&etm0_out>; + }; + }; + }; + + out-ports { + port { + funnel_out_port: endpoint { + remote-endpoint =3D <&etf_in_port>; + }; + }; + }; + }; + + cs_etf: etf@50092000 { + compatible =3D "arm,coresight-tmc", "arm,primecell"; + reg =3D <0x50092000 0x1000>; + clocks =3D <&rcc CK_DBG>; + clock-names =3D "apb_pclk"; + access-controllers =3D <&dbg_bus 0>; + status =3D "disabled"; + + in-ports { + port { + etf_in_port: endpoint { + remote-endpoint =3D <&funnel_out_port>; + }; + }; + }; + + out-ports { + port { + etf_out_port: endpoint { + remote-endpoint =3D <&tpiu_in_port>; + }; + }; + }; + }; + + cs_tpiu: tpiu@50093000 { + compatible =3D "arm,coresight-tpiu", "arm,primecell"; + reg =3D <0x50093000 0x1000>; + clocks =3D <&rcc CK_DBG>, <&rcc CK_TRACE>; + clock-names =3D "apb_pclk", "atclk"; + access-controllers =3D <&dbg_bus 0>; + status =3D "disabled"; + + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint =3D <&etf_out_port>; + }; + }; + }; + }; + + cs_cti_trace: cti@50094000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x50094000 0x1000>; + clocks =3D <&rcc CK_DBG>; + clock-names =3D "apb_pclk"; + access-controllers =3D <&dbg_bus 0>; + status =3D "disabled"; + }; + + cs_stm: stm@500a0000 { + compatible =3D "arm,coresight-stm", "arm,primecell"; + reg =3D <0x500a0000 0x00001000>, + <0x90000000 0x01000000>; + reg-names =3D "stm-base", "stm-stimulus-base"; + clocks =3D <&rcc CK_DBG>, <&rcc CK_TRACE>; + clock-names =3D "apb_pclk", "atclk"; + access-controllers =3D <&dbg_bus 0>; + status =3D "disabled"; + + out-ports { + port { + stm_out_port: endpoint { + remote-endpoint =3D <&funnel_in_port0>; + }; + }; + }; + }; + + cs_cti_cpu0: cti@500d8000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x500d8000 0x1000>; + clocks =3D <&rcc CK_DBG>; + clock-names =3D "apb_pclk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&dbg_bus 0>; + status =3D "disabled"; + + trig-conns@0 { + reg =3D <0>; + arm,trig-in-sigs =3D <0 4 5>; + arm,trig-in-types =3D ; + arm,trig-out-sigs =3D <0 7>; + arm,trig-out-types =3D ; + cpu =3D <&cpu0>; + }; + + trig-conns@2 { + reg =3D <2>; + arm,trig-in-sigs =3D <2 3 6>; + arm,trig-in-types =3D ; + arm,trig-out-sigs =3D <1 2 3 4>; + arm,trig-out-types =3D ; + arm,cs-dev-assoc =3D <&cs_etm0>; + }; + }; + + cs_etm0: etm@500dc000 { + compatible =3D "arm,coresight-etm3x", "arm,primecell"; + reg =3D <0x500dc000 0x1000>; + cpu =3D <&cpu0>; + clocks =3D <&rcc CK_DBG>, <&rcc CK_TRACE>; + clock-names =3D "apb_pclk", "atclk"; + access-controllers =3D <&dbg_bus 0>; + status =3D "disabled"; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint =3D <&funnel_in_port1>; + }; + }; + }; + }; + }; + mdma1: dma-controller@58000000 { compatible =3D "st,stm32h7-mdma"; reg =3D <0x58000000 0x1000>; diff --git a/arch/arm/boot/dts/st/stm32mp153.dtsi b/arch/arm/boot/dts/st/st= m32mp153.dtsi index 92794b942ab2..17d52d93695e 100644 --- a/arch/arm/boot/dts/st/stm32mp153.dtsi +++ b/arch/arm/boot/dts/st/stm32mp153.dtsi @@ -30,6 +30,74 @@ timer { }; }; =20 +&cs_funnel { + in-ports { + port@2 { + reg =3D <2>; + funnel_in_port2: endpoint { + remote-endpoint =3D <&etm1_out>; + }; + }; + }; +}; + +&dbg_bus { + cs_cti_cpu1: cti@500d9000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x500d9000 0x1000>; + clocks =3D <&rcc CK_DBG>; + clock-names =3D "apb_pclk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&dbg_bus 0>; + status =3D "disabled"; + + trig-conns@0 { + reg =3D <0>; + arm,trig-in-sigs =3D <0 4 5>; + arm,trig-in-types =3D ; + arm,trig-out-sigs =3D <0 7>; + arm,trig-out-types =3D ; + cpu =3D <&cpu1>; + }; + + trig-conns@2 { + reg =3D <2>; + arm,trig-in-sigs =3D <2 3 6>; + arm,trig-in-types =3D ; + arm,trig-out-sigs =3D <1 2 3 4>; + arm,trig-out-types =3D ; + arm,cs-dev-assoc =3D <&cs_etm1>; + }; + }; + + cs_etm1: etm@500dd000 { + compatible =3D "arm,coresight-etm3x", "arm,primecell"; + reg =3D <0x500dd000 0x1000>; + cpu =3D <&cpu1>; + clocks =3D <&rcc CK_DBG>, <&rcc CK_TRACE>; + clock-names =3D "apb_pclk", "atclk"; + access-controllers =3D <&dbg_bus 0>; + status =3D "disabled"; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint =3D <&funnel_in_port2>; + }; + }; + }; + }; +}; + &etzpc { m_can1: can@4400e000 { compatible =3D "bosch,m_can"; --=20 2.43.0