From nobody Tue Apr 7 12:20:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E1D03D522B for ; Wed, 25 Feb 2026 15:04:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772031885; cv=none; b=A7RXgLrFWsOpYToVdBDL4P2Llfz3bMr66bEDfnZZNWEyirY7VRnQqZ1gSAR/fAtpo5w6YpT8rlTntJvEFkRg7zAuRKB3Psydid39a2o3eGWsDbBdh1vrzHhSJeHOa48xRE3FgJuOBc6zTcwMwY3LAHQpA/huC3De28CBzYxr6pc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772031885; c=relaxed/simple; bh=AeeGpAWlnalKkGljt+Q0JTWXMacSXGiGTEbRoHMMxa8=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=AQa0pdjjuRHSbO0jzcOvfjIM4LhSD28X24QGlUTCSlr1fVFPLIu/mft+pxNEQ3J1jTsQOakHtw2dSSgHi7jQYcU9KfheFCIaPJU4H/ND65VeoMeAhhsp/o56LBecZaLQGFRhG9ipTklPb9VNWP265B22HE8bmcla5+hzCX4MPtk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MtmWOUVb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MtmWOUVb" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BC4B1C2BC86; Wed, 25 Feb 2026 15:04:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772031885; bh=AeeGpAWlnalKkGljt+Q0JTWXMacSXGiGTEbRoHMMxa8=; h=From:To:Cc:Subject:Date:From; b=MtmWOUVbV4BtgVlYAunihoPmvjLR0NY07DV5MwoUtauxI6Qc0/LCFFaW3a8cP29E2 e92RpW1FcUMfHcKw9YRYJqL1mIyj7n4/Nsy2Kek1VNrInA7217/YO1mzKHAlDeMFPm MlUkvnTyECuoYzZ9YgljvVNa+nWHloF6g4YLdDVynX0H47K/k0NyjE8l3kH5ueVCrq H3X/d6NUw1y9EfR9P7dDEUVh5fqoXsWr4k5l0qTbaNMDgddtWNVJhe9jJn7dekeL8Z UyQb8Ey5+2oDsVPxuyHBbCJe2ZnjCcwY75ShMsmWEAxxWzLM/iMlCEFuTcOIhpeNLo PJAKRaGqxj/Tw== From: Jisheng Zhang To: Catalin Marinas , Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] arm64: runtime-const: save one instruction when ARM64_VA_BITS <= 48 Date: Wed, 25 Feb 2026 22:46:13 +0800 Message-ID: <20260225144613.30846-1-jszhang@kernel.org> X-Mailer: git-send-email 2.51.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, the runtime_const_ptr() uses 4 instructions to move a long imm to GP, but when ARM64_VA_BITS <=3D 48(which is true for android and armbian), the top 8bits of runtime cont ptr is all '1', so we can make use of the movn instruction to construct the imm's top 8bits and lower 16bits at the same time, thus save one instruction. Signed-off-by: Jisheng Zhang --- arch/arm64/include/asm/runtime-const.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/include/asm/runtime-const.h b/arch/arm64/include/as= m/runtime-const.h index be5915669d23..6797dd37d690 100644 --- a/arch/arm64/include/asm/runtime-const.h +++ b/arch/arm64/include/asm/runtime-const.h @@ -7,6 +7,8 @@ /* Sigh. You can still run arm64 in BE mode */ #include =20 +#if CONFIG_ARM64_VA_BITS > 48 + #define runtime_const_ptr(sym) ({ \ typeof(sym) __ret; \ asm_inline("1:\t" \ @@ -20,6 +22,22 @@ :"=3Dr" (__ret)); \ __ret; }) =20 +#else + +#define runtime_const_ptr(sym) ({ \ + typeof(sym) __ret; \ + asm_inline("1:\t" \ + "movn %0, #0x3210\n\t" \ + "movk %0, #0x89ab, lsl #16\n\t" \ + "movk %0, #0x4567, lsl #32\n\t" \ + ".pushsection runtime_ptr_" #sym ",\"a\"\n\t" \ + ".long 1b - .\n\t" \ + ".popsection" \ + : "=3Dr" (__ret)); \ + __ret; }) + +#endif + #define runtime_const_shift_right_32(val, sym) ({ \ unsigned long __ret; \ asm_inline("1:\t" \ @@ -58,11 +76,19 @@ static inline void __runtime_fixup_caches(void *where, = unsigned int insns) static inline void __runtime_fixup_ptr(void *where, unsigned long val) { __le32 *p =3D lm_alias(where); +#if CONFIG_ARM64_VA_BITS > 48 __runtime_fixup_16(p, val); +#else + __runtime_fixup_16(p, ~val); +#endif __runtime_fixup_16(p+1, val >> 16); __runtime_fixup_16(p+2, val >> 32); +#if CONFIG_ARM64_VA_BITS > 48 __runtime_fixup_16(p+3, val >> 48); __runtime_fixup_caches(where, 4); +#else + __runtime_fixup_caches(where, 3); +#endif } =20 /* Immediate value is 6 bits starting at bit #16 */ --=20 2.51.0