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charset="utf-8" The current DT binding for pci-imx6 specifies the 'reset-gpios' property in the host bridge node. However, the PERST# signal logically belongs to individual Root Ports rather than the host bridge itself. This becomes important when supporting PCIe KeyE connector and PCI power control framework for pci-imx6 driver, which requires properties to be specified in Root Port nodes. With the common Root Port parsing now handled in dw_pcie_host_init(), update the reset GPIO handling to use the parsed port list from bridge->ports. To maintain DT backwards compatibility, fallback to the legacy method of parsing the host bridge node if the reset property is not present in the Root Port node (indicated by an empty ports list). Signed-off-by: Sherry Sun --- drivers/pci/controller/dwc/pci-imx6.c | 76 +++++++++++++++++++++------ 1 file changed, 61 insertions(+), 15 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index a5b8d0b71677..4860575f5005 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -34,6 +34,7 @@ #include =20 #include "../../pci.h" +#include "../pci-host-common.h" #include "pcie-designware.h" =20 #define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9) @@ -150,7 +151,6 @@ struct imx_lut_data { =20 struct imx_pcie { struct dw_pcie *pci; - struct gpio_desc *reset_gpiod; struct clk_bulk_data *clks; int num_clks; bool supports_clkreq; @@ -897,29 +897,40 @@ static int imx95_pcie_core_reset(struct imx_pcie *imx= _pcie, bool assert) =20 static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie) { + struct dw_pcie *pci =3D imx_pcie->pci; + struct pci_host_bridge *bridge =3D pci->pp.bridge; + struct pci_host_port *port; + reset_control_assert(imx_pcie->pciephy_reset); =20 if (imx_pcie->drvdata->core_reset) imx_pcie->drvdata->core_reset(imx_pcie, true); =20 /* Some boards don't have PCIe reset GPIO. */ - gpiod_set_value_cansleep(imx_pcie->reset_gpiod, 1); + if (bridge) + list_for_each_entry(port, &bridge->ports, list) + gpiod_set_value_cansleep(port->reset, 1); } =20 static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie) { + struct dw_pcie *pci =3D imx_pcie->pci; + struct pci_host_bridge *bridge =3D pci->pp.bridge; + struct pci_host_port *port; + reset_control_deassert(imx_pcie->pciephy_reset); =20 if (imx_pcie->drvdata->core_reset) imx_pcie->drvdata->core_reset(imx_pcie, false); =20 /* Some boards don't have PCIe reset GPIO. */ - if (imx_pcie->reset_gpiod) { - msleep(100); - gpiod_set_value_cansleep(imx_pcie->reset_gpiod, 0); - /* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */ - msleep(100); - } + if (bridge) + list_for_each_entry(port, &bridge->ports, list) + if (port->reset) { + msleep(PCIE_T_PVPERL_MS); + gpiod_set_value_cansleep(port->reset, 0); + msleep(PCIE_RESET_CONFIG_WAIT_MS); + } =20 return 0; } @@ -1233,6 +1244,44 @@ static void imx_pcie_disable_device(struct pci_host_= bridge *bridge, imx_pcie_remove_lut(imx_pcie, pci_dev_id(pdev)); } =20 +static int imx_pcie_parse_legacy_binding(struct imx_pcie *pcie) +{ + struct device *dev =3D pcie->pci->dev; + struct pci_host_bridge *bridge =3D pcie->pci->pp.bridge; + struct pci_host_port *port; + struct gpio_desc *reset; + + if (!bridge) { + dev_err(dev, "Bridge not allocated yet\n"); + return -EINVAL; + } + + /* + * For DT backward compatibility: if no Root Port nodes were parsed + * (indicated by empty ports list), parse reset-gpios from the host + * bridge node. + */ + if (!list_empty(&bridge->ports)) + return 0; + + reset =3D devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(reset)) + return PTR_ERR(reset); + + if (!reset) + return 0; + + port =3D devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); + if (!port) + return -ENOMEM; + + port->reset =3D reset; + INIT_LIST_HEAD(&port->list); + list_add_tail(&port->list, &bridge->ports); + + return 0; +} + static int imx_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); @@ -1240,6 +1289,10 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp) struct imx_pcie *imx_pcie =3D to_imx_pcie(pci); int ret; =20 + ret =3D imx_pcie_parse_legacy_binding(imx_pcie); + if (ret) + return ret; + if (imx_pcie->vpcie) { ret =3D regulator_enable(imx_pcie->vpcie); if (ret) { @@ -1688,13 +1741,6 @@ static int imx_pcie_probe(struct platform_device *pd= ev) return PTR_ERR(imx_pcie->phy_base); } =20 - /* Fetch GPIOs */ - imx_pcie->reset_gpiod =3D devm_gpiod_get_optional(dev, "reset", GPIOD_OUT= _HIGH); - if (IS_ERR(imx_pcie->reset_gpiod)) - return dev_err_probe(dev, PTR_ERR(imx_pcie->reset_gpiod), - "unable to get reset gpio\n"); - gpiod_set_consumer_name(imx_pcie->reset_gpiod, "PCIe reset"); - /* Fetch clocks */ imx_pcie->num_clks =3D devm_clk_bulk_get_all(dev, &imx_pcie->clks); if (imx_pcie->num_clks < 0) --=20 2.37.1