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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , linux-kernel@vger.kernel.org Subject: [PATCH net-next 1/3] net: dsa: yt921x: Refactor long register helpers Date: Wed, 25 Feb 2026 17:08:45 +0800 Message-ID: <20260225090853.2021140-2-mmyangfl@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260225090853.2021140-1-mmyangfl@gmail.com> References: <20260225090853.2021140-1-mmyangfl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dealing long registers with u64 is good, until you realize there are longer registers that are 96 bits. Use u32 arrays instead. Signed-off-by: David Yang --- drivers/net/dsa/yt921x.c | 152 +++++++++++++++++++++++++-------------- drivers/net/dsa/yt921x.h | 37 +++++----- 2 files changed, 116 insertions(+), 73 deletions(-) diff --git a/drivers/net/dsa/yt921x.c b/drivers/net/dsa/yt921x.c index 98e8915dd6c2..fedc72202d1e 100644 --- a/drivers/net/dsa/yt921x.c +++ b/drivers/net/dsa/yt921x.c @@ -255,63 +255,102 @@ yt921x_reg_toggle_bits(struct yt921x_priv *priv, u32= reg, u32 mask, bool set) return yt921x_reg_update_bits(priv, reg, mask, !set ? 0 : mask); } =20 -/* Some registers, like VLANn_CTRL, should always be written in 64-bit, ev= en if - * you are to write only the lower / upper 32 bits. +/* Some registers, like VLANn_CTRL, should always be written in chunks, ev= en if + * you only want to write parts of 32 bits. * - * There is no such restriction for reading, but we still provide 64-bit r= ead - * wrappers so that we always handle u64 values. + * There is no such restriction for reading, but we still provide multi-ch= unk + * read wrappers so that we can handle them consistently. */ =20 -static int yt921x_reg64_read(struct yt921x_priv *priv, u32 reg, u64 *valp) +static int +yt921x_longreg_read(struct yt921x_priv *priv, u32 reg, u32 *vals, + unsigned int span) { - u32 lo; - u32 hi; int res; =20 - res =3D yt921x_reg_read(priv, reg, &lo); - if (res) - return res; - res =3D yt921x_reg_read(priv, reg + 4, &hi); - if (res) - return res; + for (unsigned int i =3D 0; i < span; i++) { + res =3D yt921x_reg_read(priv, reg + 4 * i, &vals[i]); + if (res) + return res; + } =20 - *valp =3D ((u64)hi << 32) | lo; return 0; } =20 -static int yt921x_reg64_write(struct yt921x_priv *priv, u32 reg, u64 val) +static int +yt921x_longreg_write(struct yt921x_priv *priv, u32 reg, const u32 *vals, + unsigned int span) { int res; =20 - res =3D yt921x_reg_write(priv, reg, (u32)val); - if (res) - return res; - return yt921x_reg_write(priv, reg + 4, (u32)(val >> 32)); + for (unsigned int i =3D 0; i < span; i++) { + res =3D yt921x_reg_write(priv, reg + 4 * i, vals[i]); + if (res) + return res; + } + + return 0; } =20 static int -yt921x_reg64_update_bits(struct yt921x_priv *priv, u32 reg, u64 mask, u64 = val) +yt921x_longreg_update_bits(struct yt921x_priv *priv, u32 reg, const u32 *m= asks, + const u32 *vals, unsigned int span) { + bool changed =3D false; + u32 vs[4]; int res; - u64 v; - u64 u; =20 - res =3D yt921x_reg64_read(priv, reg, &v); + BUILD_BUG_ON(span > ARRAY_SIZE(vs)); + + res =3D yt921x_longreg_read(priv, reg, vs, span); if (res) return res; =20 - u =3D v; - u &=3D ~mask; - u |=3D val; - if (u =3D=3D v) + for (unsigned int i =3D 0; i < span; i++) { + u32 u =3D vs[i]; + + u &=3D ~masks[i]; + u |=3D vals[i]; + if (u !=3D vs[i]) + changed =3D true; + + vs[i] =3D u; + } + + if (!changed) return 0; =20 - return yt921x_reg64_write(priv, reg, u); + return yt921x_longreg_write(priv, reg, vs, span); } =20 -static int yt921x_reg64_clear_bits(struct yt921x_priv *priv, u32 reg, u64 = mask) +static int +yt921x_longreg_clear_bits(struct yt921x_priv *priv, u32 reg, const u32 *ma= sks, + unsigned int span) { - return yt921x_reg64_update_bits(priv, reg, mask, 0); + bool changed =3D false; + u32 vs[4]; + int res; + + BUILD_BUG_ON(span > ARRAY_SIZE(vs)); + + res =3D yt921x_longreg_read(priv, reg, vs, span); + if (res) + return res; + + for (unsigned int i =3D 0; i < span; i++) { + u32 u =3D vs[i]; + + u &=3D ~masks[i]; + if (u !=3D vs[i]) + changed =3D true; + + vs[i] =3D u; + } + + if (!changed) + return 0; + + return yt921x_longreg_write(priv, reg, vs, span); } =20 static int yt921x_reg_mdio_read(void *context, u32 reg, u32 *valp) @@ -1844,33 +1883,32 @@ yt921x_vlan_filtering(struct yt921x_priv *priv, int= port, bool vlan_filtering) return 0; } =20 -static int -yt921x_vlan_del(struct yt921x_priv *priv, int port, u16 vid) +static int yt921x_vlan_del(struct yt921x_priv *priv, int port, u16 vid) { - u64 mask64; + u32 masks[YT921X_VLAN_CTRL_S]; =20 - mask64 =3D YT921X_VLAN_CTRL_PORTS(port) | - YT921X_VLAN_CTRL_UNTAG_PORTn(port); + masks[0] =3D YT921X_VLAN_CTRLa_PORTn(port); + masks[1] =3D YT921X_VLAN_CTRLb_UNTAG_PORTn(port); =20 - return yt921x_reg64_clear_bits(priv, YT921X_VLANn_CTRL(vid), mask64); + return yt921x_longreg_clear_bits(priv, YT921X_VLANn_CTRL(vid), masks, + YT921X_VLAN_CTRL_S); } =20 static int yt921x_vlan_add(struct yt921x_priv *priv, int port, u16 vid, bool untagged) { - u64 mask64; - u64 ctrl64; + u32 masks[YT921X_VLAN_CTRL_S]; + u32 ctrls[YT921X_VLAN_CTRL_S]; =20 - mask64 =3D YT921X_VLAN_CTRL_PORTn(port) | - YT921X_VLAN_CTRL_PORTS(priv->cpu_ports_mask); - ctrl64 =3D mask64; + masks[0] =3D YT921X_VLAN_CTRLa_PORTn(port) | + YT921X_VLAN_CTRLa_PORTS(priv->cpu_ports_mask); + ctrls[0] =3D masks[0]; =20 - mask64 |=3D YT921X_VLAN_CTRL_UNTAG_PORTn(port); - if (untagged) - ctrl64 |=3D YT921X_VLAN_CTRL_UNTAG_PORTn(port); + masks[1] =3D YT921X_VLAN_CTRLb_UNTAG_PORTn(port); + ctrls[1] =3D untagged ? masks[1] : 0; =20 - return yt921x_reg64_update_bits(priv, YT921X_VLANn_CTRL(vid), - mask64, ctrl64); + return yt921x_longreg_update_bits(priv, YT921X_VLANn_CTRL(vid), + masks, ctrls, YT921X_VLAN_CTRL_S); } =20 static int @@ -2331,8 +2369,8 @@ yt921x_dsa_vlan_msti_set(struct dsa_switch *ds, struc= t dsa_bridge bridge, const struct switchdev_vlan_msti *msti) { struct yt921x_priv *priv =3D to_yt921x_priv(ds); - u64 mask64; - u64 ctrl64; + u32 masks[YT921X_VLAN_CTRL_S]; + u32 ctrls[YT921X_VLAN_CTRL_S]; int res; =20 if (!msti->vid) @@ -2340,12 +2378,14 @@ yt921x_dsa_vlan_msti_set(struct dsa_switch *ds, str= uct dsa_bridge bridge, if (!msti->msti || msti->msti >=3D YT921X_MSTI_NUM) return -EINVAL; =20 - mask64 =3D YT921X_VLAN_CTRL_STP_ID_M; - ctrl64 =3D YT921X_VLAN_CTRL_STP_ID(msti->msti); + masks[0] =3D 0; + ctrls[0] =3D 0; + masks[1] =3D YT921X_VLAN_CTRLb_STP_ID_M; + ctrls[1] =3D YT921X_VLAN_CTRLb_STP_ID(msti->msti); =20 mutex_lock(&priv->reg_lock); - res =3D yt921x_reg64_update_bits(priv, YT921X_VLANn_CTRL(msti->vid), - mask64, ctrl64); + res =3D yt921x_longreg_update_bits(priv, YT921X_VLANn_CTRL(msti->vid), + masks, ctrls, YT921X_VLAN_CTRL_S); mutex_unlock(&priv->reg_lock); =20 return res; @@ -3096,8 +3136,8 @@ static int yt921x_chip_reset(struct yt921x_priv *priv) static int yt921x_chip_setup_dsa(struct yt921x_priv *priv) { struct dsa_switch *ds =3D &priv->ds; + u32 ctrls[YT921X_VLAN_CTRL_S]; unsigned long cpu_ports_mask; - u64 ctrl64; u32 ctrl; int port; int res; @@ -3158,8 +3198,10 @@ static int yt921x_chip_setup_dsa(struct yt921x_priv = *priv) /* Tagged VID 0 should be treated as untagged, which confuses the * hardware a lot */ - ctrl64 =3D YT921X_VLAN_CTRL_LEARN_DIS | YT921X_VLAN_CTRL_PORTS_M; - res =3D yt921x_reg64_write(priv, YT921X_VLANn_CTRL(0), ctrl64); + ctrls[0] =3D YT921X_VLAN_CTRLa_LEARN_DIS | YT921X_VLAN_CTRLa_PORTS_M; + ctrls[1] =3D 0; + res =3D yt921x_longreg_write(priv, YT921X_VLANn_CTRL(0), ctrls, + YT921X_VLAN_CTRL_S); if (res) return res; =20 diff --git a/drivers/net/dsa/yt921x.h b/drivers/net/dsa/yt921x.h index 3f129b8d403f..361470582687 100644 --- a/drivers/net/dsa/yt921x.h +++ b/drivers/net/dsa/yt921x.h @@ -429,24 +429,25 @@ enum yt921x_app_selector { #define YT921X_FDB_HW_FLUSH_ON_LINKDOWN BIT(0) =20 #define YT921X_VLANn_CTRL(vlan) (0x188000 + 8 * (vlan)) -#define YT921X_VLAN_CTRL_UNTAG_PORTS_M GENMASK_ULL(50, 40) -#define YT921X_VLAN_CTRL_UNTAG_PORTS(x) FIELD_PREP(YT921X_VLAN_CTRL_UNT= AG_PORTS_M, (x)) -#define YT921X_VLAN_CTRL_UNTAG_PORTn(port) BIT_ULL((port) + 40) -#define YT921X_VLAN_CTRL_STP_ID_M GENMASK_ULL(39, 36) -#define YT921X_VLAN_CTRL_STP_ID(x) FIELD_PREP(YT921X_VLAN_CTRL_STP_ID_= M, (x)) -#define YT921X_VLAN_CTRL_SVLAN_EN BIT_ULL(35) -#define YT921X_VLAN_CTRL_FID_M GENMASK_ULL(34, 23) -#define YT921X_VLAN_CTRL_FID(x) FIELD_PREP(YT921X_VLAN_CTRL_FID_M, (x)) -#define YT921X_VLAN_CTRL_LEARN_DIS BIT_ULL(22) -#define YT921X_VLAN_CTRL_PRIO_EN BIT_ULL(21) -#define YT921X_VLAN_CTRL_PRIO_M GENMASK_ULL(20, 18) -#define YT921X_VLAN_CTRL_PRIO(x) FIELD_PREP(YT921X_VLAN_CTRL_PRIO_M, (= x)) -#define YT921X_VLAN_CTRL_PORTS_M GENMASK_ULL(17, 7) -#define YT921X_VLAN_CTRL_PORTS(x) FIELD_PREP(YT921X_VLAN_CTRL_PORTS_M,= (x)) -#define YT921X_VLAN_CTRL_PORTn(port) BIT_ULL((port) + 7) -#define YT921X_VLAN_CTRL_BYPASS_1X_AC BIT_ULL(6) -#define YT921X_VLAN_CTRL_METER_EN BIT_ULL(5) -#define YT921X_VLAN_CTRL_METER_ID_M GENMASK_ULL(4, 0) +#define YT921X_VLAN_CTRL_S 2 +#define YT921X_VLAN_CTRLb_UNTAG_PORTS_M GENMASK(18, 8) +#define YT921X_VLAN_CTRLb_UNTAG_PORTS(x) FIELD_PREP(YT921X_VLAN_CTRLb_U= NTAG_PORTS_M, (x)) +#define YT921X_VLAN_CTRLb_UNTAG_PORTn(port) BIT((port) + 8) +#define YT921X_VLAN_CTRLb_STP_ID_M GENMASK(7, 4) +#define YT921X_VLAN_CTRLb_STP_ID(x) FIELD_PREP(YT921X_VLAN_CTRLb_STP_I= D_M, (x)) +#define YT921X_VLAN_CTRLb_SVLAN_EN BIT(3) +#define YT921X_VLAN_CTRLab_FID_M GENMASK_ULL(34, 23) +#define YT921X_VLAN_CTRLab_FID(x) FIELD_PREP(YT921X_VLAN_CTRLab_FID_M,= (x)) +#define YT921X_VLAN_CTRLa_LEARN_DIS BIT(22) +#define YT921X_VLAN_CTRLa_PRIO_EN BIT(21) +#define YT921X_VLAN_CTRLa_PRIO_M GENMASK(20, 18) +#define YT921X_VLAN_CTRLa_PRIO(x) FIELD_PREP(YT921X_VLAN_CTRLa_PRIO_M,= (x)) +#define YT921X_VLAN_CTRLa_PORTS_M GENMASK(17, 7) +#define YT921X_VLAN_CTRLa_PORTS(x) FIELD_PREP(YT921X_VLAN_CTRLa_PORTS_= M, (x)) +#define YT921X_VLAN_CTRLa_PORTn(port) BIT((port) + 7) +#define YT921X_VLAN_CTRLa_BYPASS_1X_AC BIT(6) +#define YT921X_VLAN_CTRLa_METER_EN BIT(5) +#define YT921X_VLAN_CTRLa_METER_ID_M GENMASK(4, 0) =20 #define YT921X_TPID_IGRn(x) (0x210000 + 4 * (x)) /* [0, 3] */ #define YT921X_TPID_IGR_TPID_M GENMASK(15, 0) --=20 2.51.0 From nobody Thu Apr 16 22:32:42 2026 Received: from mail-pf1-f195.google.com (mail-pf1-f195.google.com [209.85.210.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 962503815C8 for ; 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Wed, 25 Feb 2026 01:09:19 -0800 (PST) Received: from d.home.yangfl.dn42 ([2603:c020:800b:d7ff::38]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-826dd8ecb2dsm12883345b3a.60.2026.02.25.01.09.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Feb 2026 01:09:19 -0800 (PST) From: David Yang To: netdev@vger.kernel.org Cc: David Yang , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , linux-kernel@vger.kernel.org Subject: [PATCH net-next 2/3] net: dsa: yt921x: Add port police support Date: Wed, 25 Feb 2026 17:08:46 +0800 Message-ID: <20260225090853.2021140-3-mmyangfl@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260225090853.2021140-1-mmyangfl@gmail.com> References: <20260225090853.2021140-1-mmyangfl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable rate meter ability and support limiting the rate of incoming traffic. Signed-off-by: David Yang --- drivers/net/dsa/yt921x.c | 269 ++++++++++++++++++++++++++++++++++++++- drivers/net/dsa/yt921x.h | 55 ++++++++ 2 files changed, 323 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/yt921x.c b/drivers/net/dsa/yt921x.c index fedc72202d1e..6fa70cea0631 100644 --- a/drivers/net/dsa/yt921x.c +++ b/drivers/net/dsa/yt921x.c @@ -353,6 +353,14 @@ yt921x_longreg_clear_bits(struct yt921x_priv *priv, u3= 2 reg, const u32 *masks, return yt921x_longreg_write(priv, reg, vs, span); } =20 +static void u32a_update_u64(u32 *arr, u64 mask, u64 val) +{ + arr[0] &=3D ~((u32)mask); + arr[1] &=3D ~((u32)(mask >> 32)); + arr[0] |=3D (u32)val; + arr[1] |=3D (u32)(val >> 32); +} + static int yt921x_reg_mdio_read(void *context, u32 reg, u32 *valp) { struct yt921x_reg_mdio *mdio =3D context; @@ -1046,6 +1054,13 @@ yt921x_dsa_set_mac_eee(struct dsa_switch *ds, int po= rt, struct ethtool_keee *e) return res; } =20 +static int yt921x_mtu_fetch(struct yt921x_priv *priv, int port) +{ + struct dsa_port *dp =3D dsa_to_port(&priv->ds, port); + + return dp->user ? READ_ONCE(dp->user->mtu) : ETH_DATA_LEN; +} + static int yt921x_dsa_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) { @@ -1077,6 +1092,218 @@ static int yt921x_dsa_port_max_mtu(struct dsa_switc= h *ds, int port) return YT921X_FRAME_SIZE_MAX - ETH_HLEN - ETH_FCS_LEN - YT921X_TAG_LEN; } =20 +/* v * 2^e */ +#define ldexpi(v, e) ({ \ + __auto_type _v =3D (v); \ + __auto_type _e =3D (e); \ + _e >=3D 0 ? _v << _e : _v >> -_e; \ +}) + +/* slot (ns) * rate (/s) / 10^9 (ns/s) =3D 2^C * token * 4^unit */ +#define rate2token(rate, unit, slot_ns, C) \ + ((u32)(ldexpi((slot_ns) * (rate), \ + -(2 * (unit) + (C) + YT921X_TOKEN_RATE_C)) / 1000000000)) +#define token2rate(token, unit, slot_ns, C) \ + (ldexpi(1000000000 * (u64)(token), \ + 2 * (unit) + (C) + YT921X_TOKEN_RATE_C) / (slot_ns)) + +/* burst =3D 2^C * token * 4^unit */ +#define burst2token(burst, unit, C) ((u32)ldexpi((burst), -(2 * (unit) + (= C)))) +#define token2burst(token, unit, C) ldexpi((u64)(token), 2 * (unit) + (C)) + +struct yt921x_meter { + u32 cir; + u32 cbs; + u32 ebs; + int unit; +}; + +#define YT921X_METER_PKT_MODE BIT(0) +#define YT921X_METER_SINGLE_BUCKET BIT(1) + +static struct yt921x_meter +yt921x_meter_tfm(struct yt921x_priv *priv, int port, unsigned int slot_ns, + u64 rate, u64 burst, unsigned int flags, + u32 cir_max, u32 cbs_max, int unit_max) +{ + const int C =3D flags & YT921X_METER_PKT_MODE ? YT921X_TOKEN_PKT_C : + YT921X_TOKEN_BYTE_C; + struct device *dev =3D to_device(priv); + struct yt921x_meter meter; + bool distorted; + u64 burst_est; + u64 burst_max; + u64 rate_max; + + meter.unit =3D unit_max; + rate_max =3D token2rate(cir_max, meter.unit, slot_ns, C); + burst_max =3D token2burst(cbs_max, meter.unit, C); + + /* Clamp rate and burst */ + if (rate > rate_max || burst > burst_max) { + dev_warn(dev, + "rate %llu, burst %llu too high, max is %llu, %llu, clamping...\n", + rate, burst, rate_max, burst_max); + + if (rate > rate_max) + rate =3D rate_max; + if (burst > burst_max) + burst =3D burst_max; + + burst_est =3D slot_ns * rate / 1000000000; + } else { + u64 burst_sug; + + burst_est =3D slot_ns * rate / 1000000000; + burst_sug =3D burst_est; + if (flags & YT921X_METER_PKT_MODE) + burst_sug++; + else + burst_sug +=3D ETH_HLEN + yt921x_mtu_fetch(priv, port) + + ETH_FCS_LEN; + if (burst_sug > burst) + dev_warn(dev, + "Consider burst at least %llu to match rate %llu\n", + burst_sug, rate); + + /* Select unit */ + for (; meter.unit > 0; meter.unit--) { + if (rate > (rate_max >> 2) || burst > (burst_max >> 2)) + break; + rate_max >>=3D 2; + burst_max >>=3D 2; + } + } + + /* Calculate information rate and bucket size */ + distorted =3D false; + meter.cir =3D rate2token(rate, meter.unit, slot_ns, C); + if (!meter.cir) { + distorted =3D true; + meter.cir =3D 1; + } else if (meter.cir > cir_max) { + WARN_ON(1); + meter.cir =3D cir_max; + } + meter.cbs =3D burst2token(burst, meter.unit, C); + if (!meter.cbs) { + distorted =3D true; + meter.cbs =3D 1; + } else if (meter.cbs > cbs_max) { + WARN_ON(1); + meter.cbs =3D cbs_max; + } + if (distorted) + dev_warn(dev, + "Have to increase rate %llu, burst %llu to %llu, %llu\n", + rate, burst, + token2rate(meter.cir, meter.unit, slot_ns, C), + token2burst(meter.cbs, meter.unit, C)); + + /* Cut EBS */ + meter.ebs =3D 0; + if (!(flags & YT921X_METER_SINGLE_BUCKET)) { + /* We don't have a chance to adjust rate when MTU is changed */ + if (flags & YT921X_METER_PKT_MODE) + burst_est++; + else + burst_est +=3D YT921X_FRAME_SIZE_MAX; + + if (burst_est < burst) { + u32 pbs =3D meter.cbs; + + meter.cbs =3D burst2token(burst_est, meter.unit, C); + if (!meter.cbs) { + meter.cbs =3D 1; + } else if (meter.cbs > cbs_max) { + WARN_ON(1); + meter.cbs =3D cbs_max; + } + + if (pbs > meter.cbs) + meter.ebs =3D pbs - meter.cbs; + } + } + + dev_dbg(dev, + "slot %u ns, rate %llu, burst %llu -> unit %d, cir %u, cbs %u, ebs %u\n", + slot_ns, rate, burst, + meter.unit, meter.cir, meter.cbs, meter.ebs); + + return meter; +} + +static void yt921x_dsa_port_policer_del(struct dsa_switch *ds, int port) +{ + struct yt921x_priv *priv =3D to_yt921x_priv(ds); + struct device *dev =3D to_device(priv); + int res; + + mutex_lock(&priv->reg_lock); + res =3D yt921x_reg_write(priv, YT921X_PORTn_METER(port), 0); + mutex_unlock(&priv->reg_lock); + + if (res) + dev_err(dev, "Failed to %s port %d: %i\n", "delete policer on", + port, res); +} + +static int +yt921x_dsa_port_policer_add(struct dsa_switch *ds, int port, + const struct flow_action_police *policer) +{ + struct yt921x_priv *priv =3D to_yt921x_priv(ds); + struct device *dev =3D to_device(priv); + u32 ctrls[YT921X_METER_CTRL_S]; + struct yt921x_meter meter; + bool pkt_mode; + u64 burst; + u64 rate; + u32 ctrl; + int res; + + /* mtu defaults to unlimited but we got 2040 here, don't know why */ + if (policer->exceed.act_id !=3D FLOW_ACTION_DROP || + policer->notexceed.act_id !=3D FLOW_ACTION_ACCEPT || + policer->peakrate_bytes_ps || policer->avrate || + policer->overhead) { + dev_err(dev, "Unsupported options specified\n"); + return -EOPNOTSUPP; + } + + pkt_mode =3D !!policer->rate_pkt_ps; + rate =3D pkt_mode ? policer->rate_pkt_ps : policer->rate_bytes_ps; + burst =3D pkt_mode ? policer->burst_pkt : policer->burst; + meter =3D yt921x_meter_tfm(priv, port, priv->meter_slot_ns, rate, burst, + pkt_mode ? YT921X_METER_PKT_MODE : 0, + YT921X_METER_RATE_MAX, YT921X_METER_BURST_MAX, + YT921X_METER_UNIT_MAX); + + mutex_lock(&priv->reg_lock); + ctrl =3D YT921X_PORT_METER_ID(port) | YT921X_PORT_METER_EN; + res =3D yt921x_reg_write(priv, YT921X_PORTn_METER(port), ctrl); + if (res) + goto end; + + ctrls[0] =3D 0; + ctrls[1] =3D YT921X_METER_CTRLb_CIR(meter.cir); + ctrls[2] =3D YT921X_METER_CTRLc_UNIT(meter.unit) | + YT921X_METER_CTRLc_DROP_R | + YT921X_METER_CTRLc_TOKEN_OVERFLOW_EN | + YT921X_METER_CTRLc_METER_EN; + u32a_update_u64(&ctrls[0], YT921X_METER_CTRLab_EBS_M, + YT921X_METER_CTRLab_EBS(meter.ebs)); + u32a_update_u64(&ctrls[1], YT921X_METER_CTRLbc_CBS_M, + YT921X_METER_CTRLbc_CBS(meter.cbs)); + res =3D yt921x_longreg_write(priv, + YT921X_METERn_CTRL(port + YT921X_METER_NUM), + ctrls, YT921X_METER_CTRL_S); +end: + mutex_unlock(&priv->reg_lock); + + return res; +} + static int yt921x_mirror_del(struct yt921x_priv *priv, int port, bool ingress) { @@ -3046,6 +3273,7 @@ static int yt921x_chip_detect(struct yt921x_priv *pri= v) u32 chipid; u32 major; u32 mode; + u32 val; int res; =20 res =3D yt921x_reg_read(priv, YT921X_CHIP_ID, &chipid); @@ -3080,12 +3308,27 @@ static int yt921x_chip_detect(struct yt921x_priv *p= riv) return -ENODEV; } =20 + res =3D yt921x_reg_read(priv, YT921X_SYS_CLK, &val); + if (res) + return res; + switch (FIELD_GET(YT921X_SYS_CLK_SEL_M, val)) { + case 0: + priv->cycle_ns =3D info->major =3D=3D YT9215_MAJOR ? 8 : 6; + break; + case YT921X_SYS_CLK_143M: + priv->cycle_ns =3D 7; + break; + default: + priv->cycle_ns =3D 8; + } + /* Print chipid here since we are interested in lower 16 bits */ dev_info(dev, "Motorcomm %s ethernet switch, chipid: 0x%x, chipmode: 0x%x 0x%x\n", info->name, chipid, mode, extmode); =20 priv->info =3D info; + return 0; } =20 @@ -3208,6 +3451,23 @@ static int yt921x_chip_setup_dsa(struct yt921x_priv = *priv) return 0; } =20 +static int yt921x_chip_setup_tc(struct yt921x_priv *priv) +{ + unsigned int op_ns; + u32 ctrl; + int res; + + op_ns =3D 8 * priv->cycle_ns; + + ctrl =3D max(priv->meter_slot_ns / op_ns, YT921X_METER_SLOT_MIN); + res =3D yt921x_reg_write(priv, YT921X_METER_SLOT, ctrl); + if (res) + return res; + priv->meter_slot_ns =3D ctrl * op_ns; + + return 0; +} + static int __maybe_unused yt921x_chip_setup_qos(struct yt921x_priv *priv) { u32 ctrl; @@ -3254,7 +3514,7 @@ static int yt921x_chip_setup(struct yt921x_priv *priv) u32 ctrl; int res; =20 - ctrl =3D YT921X_FUNC_MIB; + ctrl =3D YT921X_FUNC_MIB | YT921X_FUNC_METER; res =3D yt921x_reg_set_bits(priv, YT921X_FUNC, ctrl); if (res) return res; @@ -3263,6 +3523,10 @@ static int yt921x_chip_setup(struct yt921x_priv *pri= v) if (res) return res; =20 + res =3D yt921x_chip_setup_tc(priv); + if (res) + return res; + #if IS_ENABLED(CONFIG_DCB) res =3D yt921x_chip_setup_qos(priv); if (res) @@ -3354,6 +3618,9 @@ static const struct dsa_switch_ops yt921x_dsa_switch_= ops =3D { /* mtu */ .port_change_mtu =3D yt921x_dsa_port_change_mtu, .port_max_mtu =3D yt921x_dsa_port_max_mtu, + /* rate */ + .port_policer_del =3D yt921x_dsa_port_policer_del, + .port_policer_add =3D yt921x_dsa_port_policer_add, /* hsr */ .port_hsr_leave =3D dsa_port_simple_hsr_leave, .port_hsr_join =3D dsa_port_simple_hsr_join, diff --git a/drivers/net/dsa/yt921x.h b/drivers/net/dsa/yt921x.h index 361470582687..b033b942b394 100644 --- a/drivers/net/dsa/yt921x.h +++ b/drivers/net/dsa/yt921x.h @@ -23,6 +23,7 @@ #define YT921X_RST_HW BIT(31) #define YT921X_RST_SW BIT(1) #define YT921X_FUNC 0x80004 +#define YT921X_FUNC_METER BIT(4) #define YT921X_FUNC_MIB BIT(1) #define YT921X_CHIP_ID 0x80008 #define YT921X_CHIP_ID_MAJOR GENMASK(31, 16) @@ -239,6 +240,11 @@ #define YT921X_EDATA_DATA_STATUS_M GENMASK(3, 0) #define YT921X_EDATA_DATA_STATUS(x) FIELD_PREP(YT921X_EDATA_DATA_STATU= S_M, (x)) #define YT921X_EDATA_DATA_IDLE YT921X_EDATA_DATA_STATUS(3) +#define YT921X_SYS_CLK 0xe0040 +#define YT921X_SYS_CLK_SEL_M GENMASK(1, 0) /* unknown: 167M */ +#define YT9215_SYS_CLK_125M 0 +#define YT9218_SYS_CLK_167M 0 +#define YT921X_SYS_CLK_143M 1 =20 #define YT921X_EXT_MBUS_OP 0x6a000 #define YT921X_INT_MBUS_OP 0xf0000 @@ -466,6 +472,43 @@ enum yt921x_app_selector { #define YT921X_LAG_HASH_MAC_DA BIT(1) #define YT921X_LAG_HASH_SRC_PORT BIT(0) =20 +#define YT921X_PORTn_RATE(port) (0x220000 + 4 * (port)) +#define YT921X_PORT_RATE_GAP_VALUE GENMASK(4, 0) /* default 20 */ +#define YT921X_METER_SLOT 0x220104 +#define YT921X_METER_SLOT_SLOT_M GENMASK(11, 0) +#define YT921X_PORTn_METER(port) (0x220108 + 4 * (port)) +#define YT921X_PORT_METER_EN BIT(4) +#define YT921X_PORT_METER_ID_M GENMASK(3, 0) +#define YT921X_PORT_METER_ID(x) FIELD_PREP(YT921X_PORT_METER_ID_M, (x)) +#define YT921X_METERn_CTRL(x) (0x220800 + 0x10 * (x)) +#define YT921X_METER_CTRL_S 3 +#define YT921X_METER_CTRLc_METER_EN BIT(14) +#define YT921X_METER_CTRLc_TOKEN_OVERFLOW_EN BIT(13) /* RFC4115: yellow u= se unused green bw */ +#define YT921X_METER_CTRLc_DROP_M GENMASK(12, 11) +#define YT921X_METER_CTRLc_DROP(x) FIELD_PREP(YT921X_METER_CTRLc_DROP_= M, (x)) +#define YT921X_METER_CTRLc_DROP_GYR YT921X_METER_CTRLc_DROP(0) +#define YT921X_METER_CTRLc_DROP_YR YT921X_METER_CTRLc_DROP(1) +#define YT921X_METER_CTRLc_DROP_R YT921X_METER_CTRLc_DROP(2) +#define YT921X_METER_CTRLc_DROP_NONE YT921X_METER_CTRLc_DROP(3) +#define YT921X_METER_CTRLc_COLOR_BLIND BIT(10) +#define YT921X_METER_CTRLc_UNIT_M GENMASK(9, 7) +#define YT921X_METER_CTRLc_UNIT(x) FIELD_PREP(YT921X_METER_CTRLc_UNIT_= M, (x)) +#define YT921X_METER_CTRLc_BYTE_MODE_INCLUDE_GAP BIT(6) /* +GAP_VALUE byt= es each packet */ +#define YT921X_METER_CTRLc_PKT_MODE BIT(5) /* 0: byte rate mode */ +#define YT921X_METER_CTRLc_RFC2698 BIT(4) /* 0: RFC4115 */ +#define YT921X_METER_CTRLbc_CBS_M GENMASK_ULL(35, 20) +#define YT921X_METER_CTRLbc_CBS(x) FIELD_PREP(YT921X_METER_CTRLbc_CBS_= M, (x)) +#define YT921X_METER_CTRLb_CIR_M GENMASK(19, 2) +#define YT921X_METER_CTRLb_CIR(x) FIELD_PREP(YT921X_METER_CTRLb_CIR_M,= (x)) +#define YT921X_METER_CTRLab_EBS_M GENMASK_ULL(33, 18) +#define YT921X_METER_CTRLab_EBS(x) FIELD_PREP(YT921X_METER_CTRLab_EBS_= M, (x)) +#define YT921X_METER_CTRLa_EIR_M GENMASK(17, 0) +#define YT921X_METER_CTRLa_EIR(x) FIELD_PREP(YT921X_METER_CTRLa_EIR_M,= (x)) +#define YT921X_METERn_STAT_EXCESS(x) (0x221000 + 8 * (x)) +#define YT921X_METERn_STAT_COMMITTED(x) (0x221004 + 8 * (x)) +#define YT921X_METER_STAT_TOKEN_M GENMASK(30, 15) +#define YT921X_METER_STAT_QUEUE_M GENMASK(14, 0) + #define YT921X_PORTn_VLAN_CTRL(port) (0x230010 + 4 * (port)) #define YT921X_PORT_VLAN_CTRL_SVLAN_PRIO_EN BIT(31) #define YT921X_PORT_VLAN_CTRL_CVLAN_PRIO_EN BIT(30) @@ -509,6 +552,16 @@ enum yt921x_fdb_entry_status { =20 #define YT921X_MSTI_NUM 16 =20 +#define YT921X_TOKEN_BYTE_C 1 /* 1 token =3D 2^1 byte */ +#define YT921X_TOKEN_PKT_C -6 /* 1 token =3D 2^-6 packets */ +#define YT921X_TOKEN_RATE_C -15 +/* for VLAN only, not including port meters */ +#define YT921X_METER_NUM 64 +#define YT921X_METER_SLOT_MIN 80 +#define YT921X_METER_UNIT_MAX ((1 << 3) - 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , linux-kernel@vger.kernel.org Subject: [PATCH net-next 3/3] net: dsa: yt921x: Add port qdisc tbf support Date: Wed, 25 Feb 2026 17:08:47 +0800 Message-ID: <20260225090853.2021140-4-mmyangfl@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260225090853.2021140-1-mmyangfl@gmail.com> References: <20260225090853.2021140-1-mmyangfl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable port shaping and support limiting the rate of outgoing traffic. Signed-off-by: David Yang --- drivers/net/dsa/yt921x.c | 120 +++++++++++++++++++++++++++++++++++++++ drivers/net/dsa/yt921x.h | 67 +++++++++++++++++++++- 2 files changed, 186 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/yt921x.c b/drivers/net/dsa/yt921x.c index 6fa70cea0631..48b322185124 100644 --- a/drivers/net/dsa/yt921x.c +++ b/drivers/net/dsa/yt921x.c @@ -24,6 +24,7 @@ #include #include #include +#include =20 #include "yt921x.h" =20 @@ -1304,6 +1305,110 @@ yt921x_dsa_port_policer_add(struct dsa_switch *ds, = int port, return res; } =20 +static int +yt921x_tbf_validate(struct yt921x_priv *priv, + const struct tc_tbf_qopt_offload *qopt, int *queuep) +{ + struct device *dev =3D to_device(priv); + int queue =3D -1; + + if (qopt->parent !=3D TC_H_ROOT) { + dev_err(dev, "Parent should be \"root\"\n"); + return -EOPNOTSUPP; + } + + switch (qopt->command) { + case TC_TBF_REPLACE: { + const struct tc_tbf_qopt_offload_replace_params *p; + + p =3D &qopt->replace_params; + + if (!p->rate.mpu) { + dev_info(dev, "Assuming you want mpu =3D 64\n"); + } else if (p->rate.mpu !=3D 64) { + dev_err(dev, "mpu other than 64 not supported\n"); + return -EINVAL; + } + } + default: + break; + } + + *queuep =3D queue; + return 0; +} + +static int +yt921x_dsa_port_setup_tc_tbf_port(struct dsa_switch *ds, int port, + const struct tc_tbf_qopt_offload *qopt) +{ + struct yt921x_priv *priv =3D to_yt921x_priv(ds); + u32 ctrls[YT921X_PORT_SHAPE_CTRL_S]; + int res; + + switch (qopt->command) { + case TC_TBF_DESTROY: + ctrls[0] =3D 0; + ctrls[1] =3D 0; + break; + case TC_TBF_REPLACE: { + const struct tc_tbf_qopt_offload_replace_params *p; + struct yt921x_meter meter; + u64 burst; + + p =3D &qopt->replace_params; + + /* where is burst??? */ + burst =3D priv->port_shape_slot_ns * p->rate.rate_bytes_ps / + 1000000000 + 10000; + meter =3D yt921x_meter_tfm(priv, port, priv->port_shape_slot_ns, + p->rate.rate_bytes_ps, burst, + YT921X_METER_SINGLE_BUCKET, + YT921X_SHAPE_RATE_MAX, + YT921X_SHAPE_BURST_MAX, + YT921X_SHAPE_UNIT_MAX); + + ctrls[0] =3D YT921X_PORT_SHAPE_CTRLa_CIR(meter.cir) | + YT921X_PORT_SHAPE_CTRLa_CBS(meter.cbs); + ctrls[1] =3D YT921X_PORT_SHAPE_CTRLb_UNIT(meter.unit) | + YT921X_PORT_SHAPE_CTRLb_EN; + break; + } + default: + return -EOPNOTSUPP; + } + + mutex_lock(&priv->reg_lock); + res =3D yt921x_longreg_write(priv, YT921X_PORTn_SHAPE_CTRL(port), + ctrls, YT921X_PORT_SHAPE_CTRL_S); + mutex_unlock(&priv->reg_lock); + + return res; +} + +static int +yt921x_dsa_port_setup_tc(struct dsa_switch *ds, int port, + enum tc_setup_type type, void *type_data) +{ + struct yt921x_priv *priv =3D to_yt921x_priv(ds); + int res; + + switch (type) { + case TC_SETUP_QDISC_TBF: { + const struct tc_tbf_qopt_offload *qopt =3D type_data; + int queue; + + res =3D yt921x_tbf_validate(priv, qopt, &queue); + if (res) + return res; + + return yt921x_dsa_port_setup_tc_tbf_port(ds, port, qopt); + } + default: + return -EOPNOTSUPP; + } +} + static int yt921x_mirror_del(struct yt921x_priv *priv, int port, bool ingress) { @@ -3465,6 +3570,20 @@ static int yt921x_chip_setup_tc(struct yt921x_priv *= priv) return res; priv->meter_slot_ns =3D ctrl * op_ns; =20 + ctrl =3D max(priv->port_shape_slot_ns / op_ns, + YT921X_PORT_SHAPE_SLOT_MIN); + res =3D yt921x_reg_write(priv, YT921X_PORT_SHAPE_SLOT, ctrl); + if (res) + return res; + priv->port_shape_slot_ns =3D ctrl * op_ns; + + ctrl =3D max(priv->queue_shape_slot_ns / op_ns, + YT921X_QUEUE_SHAPE_SLOT_MIN); + res =3D yt921x_reg_write(priv, YT921X_QUEUE_SHAPE_SLOT, ctrl); + if (res) + return res; + priv->queue_shape_slot_ns =3D ctrl * op_ns; + return 0; } =20 @@ -3621,6 +3740,7 @@ static const struct dsa_switch_ops yt921x_dsa_switch_= ops =3D { /* rate */ .port_policer_del =3D yt921x_dsa_port_policer_del, .port_policer_add =3D yt921x_dsa_port_policer_add, + .port_setup_tc =3D yt921x_dsa_port_setup_tc, /* hsr */ .port_hsr_leave =3D dsa_port_simple_hsr_leave, .port_hsr_join =3D dsa_port_simple_hsr_join, diff --git a/drivers/net/dsa/yt921x.h b/drivers/net/dsa/yt921x.h index b033b942b394..e18216996ee9 100644 --- a/drivers/net/dsa/yt921x.h +++ b/drivers/net/dsa/yt921x.h @@ -526,6 +526,12 @@ enum yt921x_app_selector { #define YT921X_PORT_VLAN_CTRL1_CVLAN_DROP_TAGGED BIT(1) #define YT921X_PORT_VLAN_CTRL1_CVLAN_DROP_UNTAGGED BIT(0) =20 +#define YT921X_PORTn_PRIO_UCAST_QUEUE(port) (0x300200 + 4 * (port)) +#define YT921X_PORT_PRIOm_UCAST_QUEUE_M(m) (7 << (3 * (m))) +#define YT921X_PORT_PRIOm_UCAST_QUEUE(m, x) ((x) << (3 * (m))) +#define YT921X_PORTn_PRIO_MCAST_QUEUE(port) (0x300280 + 4 * (port)) +#define YT921X_PORT_PRIOm_MCAST_QUEUE_M(m) (3 << (2 * (m))) +#define YT921X_PORT_PRIOm_MCAST_QUEUE(m, x) ((x) << (2 * (m))) #define YT921X_MIRROR 0x300300 #define YT921X_MIRROR_IGR_PORTS_M GENMASK(26, 16) #define YT921X_MIRROR_IGR_PORTS(x) FIELD_PREP(YT921X_MIRROR_IGR_PORTS_= M, (x)) @@ -536,6 +542,49 @@ enum yt921x_app_selector { #define YT921X_MIRROR_PORT_M GENMASK(3, 0) #define YT921X_MIRROR_PORT(x) FIELD_PREP(YT921X_MIRROR_PORT_M, (x)) =20 +#define YT921X_QUEUE_SHAPE_SLOT 0x340008 +#define YT921X_QUEUE_SHAPE_SLOT_SLOT_M GENMASK(11, 0) +#define YT921X_PORT_SHAPE_SLOT 0x34000c +#define YT921X_PORT_SHAPE_SLOT_SLOT_M GENMASK(11, 0) +#define YT921X_QUEUEn_SCH(x) (0x341000 + 4 * (x)) +#define YT921X_QUEUE_SCH_E_DWRR_M GENMASK(27, 18) +#define YT921X_QUEUE_SCH_E_DWRR(x) FIELD_PREP(YT921X_QUEUE_SCH_E_DWRR_= M, (x)) +#define YT921X_QUEUE_SCH_C_DWRR_M GENMASK(17, 8) +#define YT921X_QUEUE_SCH_C_DWRR(x) FIELD_PREP(YT921X_QUEUE_SCH_C_DWRR_= M, (x)) +#define YT921X_QUEUE_SCH_E_PRIO_M GENMASK(7, 4) +#define YT921X_QUEUE_SCH_E_PRIO(x) FIELD_PREP(YT921X_QUEUE_SCH_E_PRIO_= M, (x)) +#define YT921X_QUEUE_SCH_C_PRIO_M GENMASK(3, 0) +#define YT921X_QUEUE_SCH_C_PRIO(x) FIELD_PREP(YT921X_QUEUE_SCH_C_PRIO_= M, (x)) +#define YT921X_C_DWRRn(x) (0x342000 + 4 * (x)) +#define YT921X_E_DWRRn(x) (0x343000 + 4 * (x)) +#define YT921X_DWRR_PKT_MODE BIT(0) /* 0: byte rate mode */ +#define YT921X_QUEUEn_SHAPE_CTRL(x) (0x34c000 + 0x10 * (x)) +#define YT921X_QUEUE_SHAPE_CTRL_S 3 +#define YT921X_QUEUE_SHAPE_CTRLc_TOKEN_OVERFLOW_EN BIT(6) +#define YT921X_QUEUE_SHAPE_CTRLc_E_EN BIT(5) +#define YT921X_QUEUE_SHAPE_CTRLc_C_EN BIT(4) +#define YT921X_QUEUE_SHAPE_CTRLc_PKT_MODE BIT(3) /* 0: byte rate mode */ +#define YT921X_QUEUE_SHAPE_CTRLc_UNIT_M GENMASK(2, 0) +#define YT921X_QUEUE_SHAPE_CTRLc_UNIT(x) FIELD_PREP(YT921X_QUEUE_SHAPE_= CTRLc_UNIT_M, (x)) +#define YT921X_QUEUE_SHAPE_CTRLb_EBS_M GENMASK(31, 18) +#define YT921X_QUEUE_SHAPE_CTRLb_EBS(x) FIELD_PREP(YT921X_QUEUE_SHAPE_C= TRLb_EBS_M, (x)) +#define YT921X_QUEUE_SHAPE_CTRLb_EIR_M GENMASK(17, 0) +#define YT921X_QUEUE_SHAPE_CTRLb_EIR(x) FIELD_PREP(YT921X_QUEUE_SHAPE_C= TRLb_EIR_M, (x)) +#define YT921X_QUEUE_SHAPE_CTRLa_CBS_M GENMASK(31, 18) +#define YT921X_QUEUE_SHAPE_CTRLa_CBS(x) FIELD_PREP(YT921X_QUEUE_SHAPE_C= TRLa_CBS_M, (x)) +#define YT921X_QUEUE_SHAPE_CTRLa_CIR_M GENMASK(17, 0) +#define YT921X_QUEUE_SHAPE_CTRLa_CIR(x) FIELD_PREP(YT921X_QUEUE_SHAPE_C= TRLa_CIR_M, (x)) +#define YT921X_PORTn_SHAPE_CTRL(port) (0x354000 + 8 * (port)) +#define YT921X_PORT_SHAPE_CTRL_S 2 +#define YT921X_PORT_SHAPE_CTRLb_EN BIT(4) +#define YT921X_PORT_SHAPE_CTRLb_PKT_MODE BIT(3) /* 0: byte rate mode */ +#define YT921X_PORT_SHAPE_CTRLb_UNIT_M GENMASK(2, 0) +#define YT921X_PORT_SHAPE_CTRLb_UNIT(x) FIELD_PREP(YT921X_PORT_SHAPE_CT= RLb_UNIT_M, (x)) +#define YT921X_PORT_SHAPE_CTRLa_CBS_M GENMASK(31, 18) +#define YT921X_PORT_SHAPE_CTRLa_CBS(x) FIELD_PREP(YT921X_PORT_SHAPE_CTR= La_CBS_M, (x)) +#define YT921X_PORT_SHAPE_CTRLa_CIR_M GENMASK(17, 0) +#define YT921X_PORT_SHAPE_CTRLa_CIR(x) FIELD_PREP(YT921X_PORT_SHAPE_CTR= La_CIR_M, (x)) + #define YT921X_EDATA_EXTMODE 0xfb #define YT921X_EDATA_LEN 0x100 =20 @@ -561,6 +610,11 @@ enum yt921x_fdb_entry_status { #define YT921X_METER_UNIT_MAX ((1 << 3) - 1) #define YT921X_METER_BURST_MAX ((1 << 16) - 1) #define YT921X_METER_RATE_MAX ((1 << 18) - 1) +#define YT921X_PORT_SHAPE_SLOT_MIN 80 +#define YT921X_QUEUE_SHAPE_SLOT_MIN 132 +#define YT921X_SHAPE_UNIT_MAX ((1 << 3) - 1) +#define YT921X_SHAPE_BURST_MAX ((1 << 14) - 1) +#define YT921X_SHAPE_RATE_MAX ((1 << 18) - 1) =20 #define YT921X_LAG_NUM 2 #define YT921X_LAG_PORT_NUM 4 @@ -578,7 +632,16 @@ enum yt921x_fdb_entry_status { #define YT921X_TAG_LEN 8 =20 /* 8 internal + 2 external + 1 mcu */ -#define YT921X_PORT_NUM 11 +#define YT921X_PORT_NUM 11 +#define YT921X_UCAST_QUEUE_NUM 8 +#define YT921X_MCAST_QUEUE_NUM 4 +#define YT921X_PORT_QUEUE_NUM \ + (YT921X_UCAST_QUEUE_NUM + YT921X_MCAST_QUEUE_NUM) +#define YT921X_UCAST_QUEUE_ID(port, queue) \ + (YT921X_UCAST_QUEUE_NUM * (port) + (queue)) +#define YT921X_MCAST_QUEUE_ID(port, queue) \ + (YT921X_UCAST_QUEUE_NUM * YT921X_PORT_NUM + \ + YT921X_MCAST_QUEUE_NUM * (port) + (queue)) =20 #define yt921x_port_is_internal(port) ((port) < 8) #define yt921x_port_is_external(port) (8 <=3D (port) && (port) < 9) @@ -657,6 +720,8 @@ struct yt921x_priv { =20 const struct yt921x_info *info; unsigned int meter_slot_ns; + unsigned int port_shape_slot_ns; + unsigned int queue_shape_slot_ns; /* cache of dsa_cpu_ports(ds) */ u16 cpu_ports_mask; u8 cycle_ns; --=20 2.51.0