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charset="utf-8" mtk_pcie_parse_port() in the pcie-mediatek-gen driver has a bunch of if (err) { dev_err(dev, "error message\n"); return err; # or goto } patterns. Simplify these with dev_err_probe(). The system also gains proper deferred probe messages that can be seen in /sys/kernel/debug/devices_deferred Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Bartosz Golaszewski Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/pcie-mediatek-gen3.c | 36 ++++++--------------- 1 file changed, 10 insertions(+), 26 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index 75ddb8bee168..1939cac995b5 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -876,10 +876,8 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *p= cie) if (!regs) return -EINVAL; pcie->base =3D devm_ioremap_resource(dev, regs); - if (IS_ERR(pcie->base)) { - dev_err(dev, "failed to map register base\n"); - return PTR_ERR(pcie->base); - } + if (IS_ERR(pcie->base)) + return dev_err_probe(dev, PTR_ERR(pcie->base), "failed to map register b= ase\n"); =20 pcie->reg_base =3D regs->start; =20 @@ -888,34 +886,20 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *= pcie) =20 ret =3D devm_reset_control_bulk_get_optional_shared(dev, num_resets, pcie->phy_resets); - if (ret) { - dev_err(dev, "failed to get PHY bulk reset\n"); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, "failed to get PHY bulk reset\n"); =20 pcie->mac_reset =3D devm_reset_control_get_optional_exclusive(dev, "mac"); - if (IS_ERR(pcie->mac_reset)) { - ret =3D PTR_ERR(pcie->mac_reset); - if (ret !=3D -EPROBE_DEFER) - dev_err(dev, "failed to get MAC reset\n"); - - return ret; - } + if (IS_ERR(pcie->mac_reset)) + return dev_err_probe(dev, PTR_ERR(pcie->mac_reset), "failed to get MAC r= eset\n"); =20 pcie->phy =3D devm_phy_optional_get(dev, "pcie-phy"); - if (IS_ERR(pcie->phy)) { - ret =3D PTR_ERR(pcie->phy); - if (ret !=3D -EPROBE_DEFER) - dev_err(dev, "failed to get PHY\n"); - - return ret; - } + if (IS_ERR(pcie->phy)) + return dev_err_probe(dev, PTR_ERR(pcie->phy), "failed to get PHY\n"); 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Tue, 24 Feb 2026 23:22:54 -0800 (PST) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno , Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chen-Yu Tsai , Bartosz Golaszewski , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/7] PCI: mediatek-gen3: Add error path for probe and resume driver callbacks Date: Wed, 25 Feb 2026 15:22:19 +0800 Message-ID: <20260225072225.3345307-3-wenst@chromium.org> X-Mailer: git-send-email 2.53.0.414.gf7e9f6c205-goog In-Reply-To: <20260225072225.3345307-1-wenst@chromium.org> References: <20260225072225.3345307-1-wenst@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The probe and resume callbacks currently do teardown in the conditional block directly. This is going to get ugly when the pwrctrl calls are added. Move the teardown to proper error cleanup paths. Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Bartosz Golaszewski Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/pcie-mediatek-gen3.c | 22 ++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index 1939cac995b5..f2bf4afbdc2f 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -1189,13 +1189,15 @@ static int mtk_pcie_probe(struct platform_device *p= dev) host->sysdata =3D pcie; =20 err =3D pci_host_probe(host); - if (err) { - mtk_pcie_irq_teardown(pcie); - mtk_pcie_power_down(pcie); - return err; - } + if (err) + goto err_teardown_irq_and_power_down; =20 return 0; + +err_teardown_irq_and_power_down: + mtk_pcie_irq_teardown(pcie); + mtk_pcie_power_down(pcie); + return err; } =20 static void mtk_pcie_remove(struct platform_device *pdev) @@ -1301,14 +1303,16 @@ static int mtk_pcie_resume_noirq(struct device *dev) return err; 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Tue, 24 Feb 2026 23:22:57 -0800 (PST) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno , Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chen-Yu Tsai , Bartosz Golaszewski , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/7] PCI: mediatek-gen3: Split out device power helpers Date: Wed, 25 Feb 2026 15:22:20 +0800 Message-ID: <20260225072225.3345307-4-wenst@chromium.org> X-Mailer: git-send-email 2.53.0.414.gf7e9f6c205-goog In-Reply-To: <20260225072225.3345307-1-wenst@chromium.org> References: <20260225072225.3345307-1-wenst@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Split out existing code that deals with device power sequencing into into helpers to allow cleaning up the error paths and integrating the new PCI pwrctrl API, This change is purely code movement. Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Bartosz Golaszewski Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/pcie-mediatek-gen3.c | 87 ++++++++++++--------- 1 file changed, 52 insertions(+), 35 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index f2bf4afbdc2f..870d3b3db11d 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -403,6 +403,54 @@ static void mtk_pcie_enable_msi(struct mtk_gen3_pcie *= pcie) writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG); } =20 +static int mtk_pcie_device_power_up(struct mtk_gen3_pcie *pcie) +{ + int err; + u32 val; + + /* + * Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal + * causing occasional PCIe link down. In order to overcome the issue, + * PCIE_RSTB signals are not asserted/released at this stage and the + * PCIe block is reset using en7523_reset_assert() and + * en7581_pci_enable(). + */ + if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) { + /* Assert all reset signals */ + val =3D readl_relaxed(pcie->base + PCIE_RST_CTRL_REG); + val |=3D PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | + PCIE_PE_RSTB; + writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); + + /* + * Described in PCIe CEM specification revision 6.0. + * + * The deassertion of PERST# should be delayed 100ms (TPVPERL) + * for the power and clock to become stable. + */ + msleep(PCIE_T_PVPERL_MS); + + /* De-assert reset signals */ + val &=3D ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | + PCIE_PE_RSTB); + writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); + } + + return 0; +} + +static void mtk_pcie_device_power_down(struct mtk_gen3_pcie *pcie) +{ + u32 val; + + if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) { + /* Assert the PERST# pin */ + val =3D readl_relaxed(pcie->base + PCIE_RST_CTRL_REG); + val |=3D PCIE_PE_RSTB; + writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); + } +} + static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie) { struct resource_entry *entry; @@ -464,33 +512,9 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie = *pcie) val |=3D PCIE_DISABLE_DVFSRC_VLT_REQ; writel_relaxed(val, pcie->base + PCIE_MISC_CTRL_REG); =20 - /* - * Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal - * causing occasional PCIe link down. In order to overcome the issue, - * PCIE_RSTB signals are not asserted/released at this stage and the - * PCIe block is reset using en7523_reset_assert() and - * en7581_pci_enable(). - */ - if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) { - /* Assert all reset signals */ - val =3D readl_relaxed(pcie->base + PCIE_RST_CTRL_REG); - val |=3D PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | - PCIE_PE_RSTB; - writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); - - /* - * Described in PCIe CEM specification revision 6.0. - * - * The deassertion of PERST# should be delayed 100ms (TPVPERL) - * for the power and clock to become stable. - */ - msleep(PCIE_T_PVPERL_MS); - - /* De-assert reset signals */ - val &=3D ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | - PCIE_PE_RSTB); - writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); - } + err =3D mtk_pcie_device_power_up(pcie); + if (err) + return err; =20 /* Check if the link is up or not */ err =3D readl_poll_timeout(pcie->base + PCIE_LINK_STATUS_REG, val, @@ -1269,7 +1293,6 @@ static int mtk_pcie_suspend_noirq(struct device *dev) { struct mtk_gen3_pcie *pcie =3D dev_get_drvdata(dev); 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Tue, 24 Feb 2026 23:23:01 -0800 (PST) Received: from wenstp920.tpe.corp.google.com ([2a00:79e0:201d:8:9d6:2e6a:941b:690]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ad7503fdc9sm130814435ad.80.2026.02.24.23.22.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Feb 2026 23:23:00 -0800 (PST) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno , Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chen-Yu Tsai , Bartosz Golaszewski , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/7] PCI: mediatek-gen3: Disable device if further setup fails Date: Wed, 25 Feb 2026 15:22:21 +0800 Message-ID: <20260225072225.3345307-5-wenst@chromium.org> X-Mailer: git-send-email 2.53.0.414.gf7e9f6c205-goog In-Reply-To: <20260225072225.3345307-1-wenst@chromium.org> References: <20260225072225.3345307-1-wenst@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If further setup fails after the device is powered on and link training succeeds, we want to place the device back in a quiescence state to avoid unintended activity and save power. This also helps with power state tracking and balancing once pwrctrl API is integrated. Power down the device in the error paths of mtk_pcie_startup_port() and mtk_pcie_setup(). Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Bartosz Golaszewski Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/pcie-mediatek-gen3.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index 870d3b3db11d..7459e1c1899d 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -531,7 +531,7 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *= pcie) dev_err(pcie->dev, "PCIe link down, current LTSSM state: %s (%#x)\n", ltssm_state, val); - return err; + goto err_power_down_device; } =20 mtk_pcie_enable_msi(pcie); @@ -556,10 +556,14 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie= *pcie) err =3D mtk_pcie_set_trans_table(pcie, cpu_addr, pci_addr, size, type, &table_index); if (err) - return err; + goto err_power_down_device; } =20 return 0; + +err_power_down_device: + mtk_pcie_device_power_down(pcie); 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charset="utf-8" With the new PCI pwrctrl API and PCI slot binding and power drivers, we now have a way to describe and power up WiFi/BT adapters connected through a PCIe or M.2 slot, or exploded onto the mainboard itself. Integrate the PCI pwrctrl API into the PCIe driver, so that power is properly enabled before PCIe link training is done, allowing the card to successfully be detected. Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Bartosz Golaszewski Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/pcie-mediatek-gen3.c | 38 ++++++++++++++++----- 1 file changed, 30 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index 7459e1c1899d..93e591f788f7 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -421,15 +422,23 @@ static int mtk_pcie_device_power_up(struct mtk_gen3_p= cie *pcie) val |=3D PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB; writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); + } + + err =3D pci_pwrctrl_power_on_devices(pcie->dev); + if (err) { + dev_err(pcie->dev, "Failed to power on devices: %pe\n", ERR_PTR(err)); + return err; + } =20 - /* - * Described in PCIe CEM specification revision 6.0. - * - * The deassertion of PERST# should be delayed 100ms (TPVPERL) - * for the power and clock to become stable. - */ - msleep(PCIE_T_PVPERL_MS); + /* + * Described in PCIe CEM specification revision 6.0. + * + * The deassertion of PERST# should be delayed 100ms (TPVPERL) + * for the power and clock to become stable. + */ + msleep(PCIE_T_PVPERL_MS); =20 + if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) { /* De-assert reset signals */ val &=3D ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB); @@ -449,6 +458,8 @@ static void mtk_pcie_device_power_down(struct mtk_gen3_= pcie *pcie) val |=3D PCIE_PE_RSTB; writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); } + + pci_pwrctrl_power_off_devices(pcie->dev); } =20 static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie) @@ -1211,9 +1222,13 @@ static int mtk_pcie_probe(struct platform_device *pd= ev) pcie->soc =3D device_get_match_data(dev); platform_set_drvdata(pdev, pcie); =20 + err =3D pci_pwrctrl_create_devices(pcie->dev); + if (err) + return dev_err_probe(dev, err, "failed to create pwrctrl devices\n"); + err =3D mtk_pcie_setup(pcie); if (err) - return err; + goto err_destroy_pwrctrl; =20 host->ops =3D &mtk_pcie_ops; host->sysdata =3D pcie; @@ -1226,7 +1241,12 @@ static int mtk_pcie_probe(struct platform_device *pd= ev) =20 err_teardown_irq_and_power_down: mtk_pcie_irq_teardown(pcie); + mtk_pcie_device_power_down(pcie); mtk_pcie_power_down(pcie); +err_destroy_pwrctrl: + if (err !=3D -EPROBE_DEFER) + pci_pwrctrl_destroy_devices(pcie->dev); + return err; } =20 @@ -1241,7 +1261,9 @@ static void mtk_pcie_remove(struct platform_device *p= dev) pci_unlock_rescan_remove(); =20 mtk_pcie_irq_teardown(pcie); + pci_pwrctrl_power_off_devices(pcie->dev); mtk_pcie_power_down(pcie); + pci_pwrctrl_destroy_devices(pcie->dev); } =20 static void mtk_pcie_irq_save(struct mtk_gen3_pcie *pcie) --=20 2.53.0.414.gf7e9f6c205-goog From nobody Thu Apr 16 22:34:01 2026 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D34F7313E03 for ; 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Tue, 24 Feb 2026 23:23:07 -0800 (PST) Received: from wenstp920.tpe.corp.google.com ([2a00:79e0:201d:8:9d6:2e6a:941b:690]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ad7503fdc9sm130814435ad.80.2026.02.24.23.23.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Feb 2026 23:23:06 -0800 (PST) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno , Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chen-Yu Tsai , Bartosz Golaszewski , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/7] arm64: dts: mediatek: mt8195-cherry: add WiFi PCIe and BT USB power supplies Date: Wed, 25 Feb 2026 15:22:23 +0800 Message-ID: <20260225072225.3345307-7-wenst@chromium.org> X-Mailer: git-send-email 2.53.0.414.gf7e9f6c205-goog In-Reply-To: <20260225072225.3345307-1-wenst@chromium.org> References: <20260225072225.3345307-1-wenst@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MT8195 Cherry design features an M.2 E-key slot wired up with PCIe and USB for a WiFi+BT adapter. Previously the power was just enabled all the time with a default pinctrl setting that set the GPIO pin high. With the PCIe slot description DT binding in place, the power supplies can at least be added and tied to the PCIe and USB hosts. Once the M.2 E-key binding is merged, this description can be further converted to an M.2 E-key. Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Manivannan Sadhasivam --- .../boot/dts/mediatek/mt8195-cherry.dtsi | 47 ++++++++++++++----- 1 file changed, 36 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/b= oot/dts/mediatek/mt8195-cherry.dtsi index 6e99122c65ac..f1ff64a84267 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -83,6 +83,17 @@ pp3300_s3: regulator-pp3300-s3 { vin-supply =3D <&pp3300_z2>; }; =20 + pp3300_wlan: regulator-pp3300-wlan { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pp3300_wlan_en_pin>; + regulator-name =3D "pp3300_wlan"; + /* load switch */ + enable-active-high; + gpio =3D <&pio 58 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&pp3300_z2>; + }; + /* system wide 3.3V power rail */ pp3300_z2: regulator-pp3300-z2 { compatible =3D "regulator-fixed"; @@ -760,10 +771,25 @@ &ovl0_in { }; =20 &pcie1 { - status =3D "okay"; - pinctrl-names =3D "default"; pinctrl-0 =3D <&pcie1_pins_default>; + status =3D "okay"; + + pcie@0 { + compatible =3D "pciclass,0604"; + reg =3D <0 0 0 0 0>; + device_type =3D "pci"; + num-lanes =3D <1>; + vpcie3v3-supply =3D <&pp3300_wlan>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + + wifi@0 { + reg =3D <0 0 0 0 0>; + wakeup-source; + }; + }; }; =20 &pio { @@ -1179,12 +1205,6 @@ pins-vreg-en { }; =20 pio_default: pio-default-pins { - pins-wifi-enable { - pinmux =3D ; - output-high; - drive-strength =3D <14>; - }; - pins-low-power-pd { pinmux =3D , , @@ -1222,6 +1242,12 @@ pins-low-power-pupd { }; }; =20 + pp3300_wlan_en_pin: pp3300-wlan-en-pins { + pins-en { + pinmux =3D ; + }; + }; + rt1019p_pins_default: rt1019p-default-pins { pins-amp-sdb { pinmux =3D ; @@ -1570,11 +1596,10 @@ &xhci2 { }; =20 &xhci3 { - status =3D "okay"; - /* MT7921's USB Bluetooth has issues with USB2 LPM */ usb2-lpm-disable; - vbus-supply =3D <&usb_vbus>; + vbus-supply =3D <&pp3300_wlan>; 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Tue, 24 Feb 2026 23:23:10 -0800 (PST) Received: from wenstp920.tpe.corp.google.com ([2a00:79e0:201d:8:9d6:2e6a:941b:690]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ad7503fdc9sm130814435ad.80.2026.02.24.23.23.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Feb 2026 23:23:09 -0800 (PST) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno , Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chen-Yu Tsai , Bartosz Golaszewski , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/7] arm64: dts: mediatek: mt8195-cherry-dojo: Describe M.2 M-key NVMe slot Date: Wed, 25 Feb 2026 15:22:24 +0800 Message-ID: <20260225072225.3345307-8-wenst@chromium.org> X-Mailer: git-send-email 2.53.0.414.gf7e9f6c205-goog In-Reply-To: <20260225072225.3345307-1-wenst@chromium.org> References: <20260225072225.3345307-1-wenst@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Dojo device has a M.2 M-key slot for an included NVMe on some models. Add a proper device tree description based on the new M.2 M-key binding. Power for the slot is controlled by the embedded controller. As far as the main SoC is concerned, it is always on. Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Manivannan Sadhasivam --- .../dts/mediatek/mt8195-cherry-dojo-r1.dts | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts b/arch/= arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts index 49664de99b88..57cc329f49c4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts @@ -11,6 +11,28 @@ / { compatible =3D "google,dojo-sku7", "google,dojo-sku5", "google,dojo-sku3", "google,dojo-sku1", "google,dojo", "mediatek,mt8195"; + + nvme-connector { + compatible =3D "pcie-m2-m-connector"; + /* power is controlled by EC */ + vpcie3v3-supply =3D <&pp3300_z2>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + nvme_ep: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&pcie0_ep>; + }; + }; + }; + }; }; =20 &audio_codec { @@ -72,6 +94,22 @@ &pcie0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pcie0_pins_default>; status =3D "okay"; + + pcie@0 { + compatible =3D "pciclass,0604"; + reg =3D <0 0 0 0 0>; + device_type =3D "pci"; + num-lanes =3D <2>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + + port { + pcie0_ep: endpoint { + remote-endpoint =3D <&nvme_ep>; + }; + }; + }; }; =20 &pciephy { --=20 2.53.0.414.gf7e9f6c205-goog