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Tue, 24 Feb 2026 21:46:34 -0800 (PST) From: Pengyu Luo To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Krishna Manikandan , Jonathan Marek Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Tianyu Gao , White Lewis , Pengyu Luo Subject: [PATCH] arm64: dts: qcom: sc8280xp: Add dsi nodes on SC8280XP Date: Wed, 25 Feb 2026 13:45:25 +0800 Message-ID: <20260225054525.6803-6-mitltlatltl@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260225054525.6803-1-mitltlatltl@gmail.com> References: <20260225054525.6803-1-mitltlatltl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The DT configuration follows other Samsung 5nm-based Qualcomm SOCs, utilizing the same register layouts and clock structures. However, DSI won't work properly for now (Partial content wrapped to the left side) until we submit dispcc fixes. And some panels require DPU timing calculation fixes too. (hdisplay / width timing round errors cause the fifo error) Co-developed-by: Tianyu Gao Signed-off-by: Tianyu Gao Signed-off-by: Pengyu Luo Tested-by: White Lewis # HUAWEI Gaokun3 --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 423 ++++++++++++++++++++++++- 1 file changed, 415 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 5334adebf..a1507f000 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -5,6 +5,7 @@ */ =20 #include +#include #include #include #include @@ -4657,6 +4658,20 @@ mdss0_intf0_out: endpoint { }; }; =20 + port@1 { + reg =3D <1>; + mdss0_intf1_out: endpoint { + remote-endpoint =3D <&mdss0_dsi0_in>; + }; + }; + + port@2 { + reg =3D <2>; + mdss0_intf2_out: endpoint { + remote-endpoint =3D <&mdss0_dsi1_in>; + }; + }; + port@4 { reg =3D <4>; mdss0_intf4_out: endpoint { @@ -4791,6 +4806,195 @@ opp-810000000 { }; }; =20 + mdss0_dsi0: dsi@ae94000 { + compatible =3D "qcom,sc8280xp-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg =3D <0 0x0ae94000 0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss0>; + interrupts =3D <4>; + + clocks =3D <&dispcc0 DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc0 DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc0 DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc0 DISP_CC_MDSS_ESC0_CLK>, + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc0 DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 =3D <&mdss0_dsi0_opp_table>; + power-domains =3D <&rpmhpd SC8280XP_MMCX>; + + phy-names =3D "dsi"; + + phys =3D <&mdss0_dsi0_phy>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdss0_dsi0_in: endpoint { + remote-endpoint =3D <&mdss0_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + mdss0_dsi0_out: endpoint { + }; + }; + }; + + mdss0_dsi0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz =3D /bits/ 64 <358000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss0_dsi0_phy: phy@ae94400 { + compatible =3D "qcom,sc8280xp-dsi-phy-5nm"; + reg =3D <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x27c>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "ref"; + + status =3D "disabled"; + }; + + mdss0_dsi1: dsi@ae96000 { + compatible =3D "qcom,sc8280xp-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg =3D <0 0x0ae96000 0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss0>; + interrupts =3D <5>; + + clocks =3D <&dispcc0 DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc0 DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc0 DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc0 DISP_CC_MDSS_ESC1_CLK>, + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc0 DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents =3D <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 =3D <&mdss0_dsi1_opp_table>; + power-domains =3D <&rpmhpd SC8280XP_MMCX>; + + phys =3D <&mdss0_dsi1_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdss0_dsi1_in: endpoint { + remote-endpoint =3D <&mdss0_intf2_out>; + }; + }; + + port@1 { + reg =3D <1>; + mdss0_dsi1_out: endpoint { + }; + }; + }; + + mdss0_dsi1_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz =3D /bits/ 64 <358000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss0_dsi1_phy: phy@ae96400 { + compatible =3D "qcom,sc8280xp-dsi-phy-5nm"; + reg =3D <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96900 0 0x27c>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "ref"; + + status =3D "disabled"; + }; + mdss0_dp1: displayport-controller@ae98000 { compatible =3D "qcom,sc8280xp-dp"; reg =3D <0 0xae98000 0 0x200>, @@ -5080,10 +5284,10 @@ dispcc0: clock-controller@af00000 { <&mdss0_dp2_phy 1>, <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>, - <0>, - <0>, - <0>, - <0>; + <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; power-domains =3D <&rpmhpd SC8280XP_MMCX>; =20 #clock-cells =3D <1>; @@ -6008,6 +6212,20 @@ mdss1_intf0_out: endpoint { }; }; =20 + port@1 { + reg =3D <1>; + mdss1_intf1_out: endpoint { + remote-endpoint =3D <&mdss1_dsi0_in>; + }; + }; + + port@2 { + reg =3D <2>; + mdss1_intf2_out: endpoint { + remote-endpoint =3D <&mdss1_dsi1_in>; + }; + }; + port@4 { reg =3D <4>; mdss1_intf4_out: endpoint { @@ -6139,6 +6357,195 @@ opp-810000000 { }; }; =20 + mdss1_dsi0: dsi@22094000 { + compatible =3D "qcom,sc8280xp-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg =3D <0 0x22094000 0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss1>; + interrupts =3D <4>; + + clocks =3D <&dispcc1 DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc1 DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc1 DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc1 DISP_CC_MDSS_ESC0_CLK>, + <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc1 DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss1_dsi0_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 =3D <&mdss1_dsi0_opp_table>; + power-domains =3D <&rpmhpd SC8280XP_MMCX>; + + phy-names =3D "dsi"; + + phys =3D <&mdss1_dsi0_phy>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdss1_dsi0_in: endpoint { + remote-endpoint =3D <&mdss1_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + mdss1_dsi0_out: endpoint { + }; + }; + }; + + mdss1_dsi0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz =3D /bits/ 64 <358000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss1_dsi0_phy: phy@22094400 { + compatible =3D "qcom,sc8280xp-dsi-phy-5nm"; + reg =3D <0 0x22094400 0 0x200>, + <0 0x22094600 0 0x280>, + <0 0x22094900 0 0x260>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "ref"; + + status =3D "disabled"; + }; + + mdss1_dsi1: dsi@22096000 { + compatible =3D "qcom,sc8280xp-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg =3D <0 0x22096000 0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss1>; + interrupts =3D <5>; + + clocks =3D <&dispcc1 DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc1 DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc1 DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc1 DISP_CC_MDSS_ESC1_CLK>, + <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc1 DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents =3D <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss1_dsi1_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 =3D <&mdss1_dsi1_opp_table>; + power-domains =3D <&rpmhpd SC8280XP_MMCX>; + + phys =3D <&mdss1_dsi1_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdss1_dsi1_in: endpoint { + remote-endpoint =3D <&mdss1_intf2_out>; + }; + }; + + port@1 { + reg =3D <1>; + mdss1_dsi1_out: endpoint { + }; + }; + }; + + mdss1_dsi1_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz =3D /bits/ 64 <358000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss1_dsi1_phy: phy@22096400 { + compatible =3D "qcom,sc8280xp-dsi-phy-5nm"; + reg =3D <0 0x22096400 0 0x200>, + <0 0x22096600 0 0x280>, + <0 0x22096900 0 0x260>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "ref"; + + status =3D "disabled"; + }; + mdss1_dp1: displayport-controller@22098000 { compatible =3D "qcom,sc8280xp-dp"; reg =3D <0 0x22098000 0 0x200>, @@ -6426,10 +6833,10 @@ dispcc1: clock-controller@22100000 { <&mdss1_dp2_phy 1>, <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>, - <0>, - <0>, - <0>, - <0>; + <&mdss1_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss1_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss1_dsi1_phy DSI_PIXEL_PLL_CLK>; power-domains =3D <&rpmhpd SC8280XP_MMCX>; =20 #clock-cells =3D <1>; --=20 2.53.0