From nobody Sat Apr 11 04:34:49 2026 Received: from canpmsgout06.his.huawei.com (canpmsgout06.his.huawei.com [113.46.200.221]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A45BA155C82; Wed, 25 Feb 2026 04:04:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.221 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771992269; cv=none; b=hhL9GIKg8moVcxvOcu+r1A0ZR1cYXY70THIAfnxnZK26pjiHYGA9zZgkicvMVd2kmXK1NZvG1Umbvpb6Tx1X82deCw/FHqStpgW+DBZkk6f2TgHubC/SaNb3+F1NwuMYh5CdBvQy2fhZp+UROwJ3dP2YAapIiuL2lRTqVIBO1D0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771992269; c=relaxed/simple; bh=ENenO/cy/T/hJWbdFyRSqVxSeHMgdjnk3MQXCRXpHX0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mYsx7Xo917Di91C0w9Cs/laXOzS5hOUEbtBepGmlgB1M5nTVJpelgskbpLw8A8vfK6G+uAYK2N0oumT4I7AcV6L3QunD5lbZA9lP1KjjjCiPASz9yBl5/1ZgQZlHaFF4D9bxsFTSRZKEVeWtdKDoamRFE+s4p8rDULSRFuSchKY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=iJbwssON; arc=none smtp.client-ip=113.46.200.221 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="iJbwssON" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=lvq/O+R+y6qCmOEUVjR2PUgdD2ilp/5PaX6r9kRJGgc=; b=iJbwssONMnPTRBgo5fw1t6+rLsbPEMOcqvZPDl2ktV9XH7Kf26BtkeotL5os9jUmfXVD/ezk5 YwA7byABP7pxRQ9yfdlnqIAlzDD9ze6AwIYfP09dDFKaLIhN6ZECjyvQWl0RtgMlbKV8AhdTkhs CtMZYK070yqV7n0l4XDFoV4= Received: from mail.maildlp.com (unknown [172.19.162.223]) by canpmsgout06.his.huawei.com (SkyGuard) with ESMTPS id 4fLLSn6sNVzRhRJ; Wed, 25 Feb 2026 11:59:37 +0800 (CST) Received: from kwepemr100010.china.huawei.com (unknown [7.202.195.125]) by mail.maildlp.com (Postfix) with ESMTPS id 021D640569; Wed, 25 Feb 2026 12:04:24 +0800 (CST) Received: from huawei.com (10.50.163.32) by kwepemr100010.china.huawei.com (7.202.195.125) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.36; Wed, 25 Feb 2026 12:04:23 +0800 From: Tian Zheng To: , , , , , , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 1/5] arm64/sysreg: Add HDBSS related register information Date: Wed, 25 Feb 2026 12:04:17 +0800 Message-ID: <20260225040421.2683931-2-zhengtian10@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260225040421.2683931-1-zhengtian10@huawei.com> References: <20260225040421.2683931-1-zhengtian10@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To kwepemr100010.china.huawei.com (7.202.195.125) Content-Type: text/plain; charset="utf-8" From: eillon The ARM architecture added the HDBSS feature and descriptions of related registers (HDBSSBR/HDBSSPROD) in the DDI0601(ID121123) version, add them to Linux. Signed-off-by: eillon Signed-off-by: Tian Zheng --- arch/arm64/include/asm/esr.h | 2 ++ arch/arm64/tools/sysreg | 29 +++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h index 7e86d400864e..81c17320a588 100644 --- a/arch/arm64/include/asm/esr.h +++ b/arch/arm64/include/asm/esr.h @@ -160,6 +160,8 @@ #define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT) /* ISS2 field definitions for Data Aborts */ +#define ESR_ELx_HDBSSF_SHIFT (11) +#define ESR_ELx_HDBSSF (UL(1) << ESR_ELx_HDBSSF_SHIFT) #define ESR_ELx_TnD_SHIFT (10) #define ESR_ELx_TnD (UL(1) << ESR_ELx_TnD_SHIFT) #define ESR_ELx_TagAccess_SHIFT (9) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 9d1c21108057..e166ab322de2 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -4528,6 +4528,35 @@ Sysreg GCSPR_EL2 3 4 2 5 1 Fields GCSPR_ELx EndSysreg +Sysreg HDBSSBR_EL2 3 4 2 3 2 +Res0 63:56 +Field 55:12 BADDR +Res0 11:4 +Enum 3:0 SZ + 0b0000 4KB + 0b0001 8KB + 0b0010 16KB + 0b0011 32KB + 0b0100 64KB + 0b0101 128KB + 0b0110 256KB + 0b0111 512KB + 0b1000 1MB + 0b1001 2MB +EndEnum +EndSysreg + +Sysreg HDBSSPROD_EL2 3 4 2 3 3 +Res0 63:32 +Enum 31:26 FSC + 0b000000 OK + 0b010000 ExternalAbort + 0b101000 GPF +EndEnum +Res0 25:19 +Field 18:0 INDEX +EndSysreg + Sysreg DACR32_EL2 3 4 3 0 0 Res0 63:32 Field 31:30 D15 -- 2.33.0 From nobody Sat Apr 11 04:34:49 2026 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0A43155C82; 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charset="utf-8" From: eillon This patch adds support to set the DBM (Dirty Bit Modifier) attribute in S2 PTE during user_mem_abort(). This bit, introduced in ARMv8.1, enables hardware to automatically promote write-clean pages to write-dirty. This prevents the guest from being trapped in EL2 due to missing write permissions. Signed-off-by: eillon Signed-off-by: Tian Zheng --- arch/arm64/include/asm/kvm_pgtable.h | 4 ++++ arch/arm64/kvm/hyp/pgtable.c | 6 ++++++ 2 files changed, 10 insertions(+) diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/= kvm_pgtable.h index c201168f2857..d0f280972a7a 100644 --- a/arch/arm64/include/asm/kvm_pgtable.h +++ b/arch/arm64/include/asm/kvm_pgtable.h @@ -93,6 +93,8 @@ typedef u64 kvm_pte_t; #define KVM_PTE_LEAF_ATTR_HI_S2_XN GENMASK(54, 53) +#define KVM_PTE_LEAF_ATTR_HI_S2_DBM BIT(51) + #define KVM_PTE_LEAF_ATTR_HI_S1_GP BIT(50) #define KVM_PTE_LEAF_ATTR_S2_PERMS (KVM_PTE_LEAF_ATTR_LO_S2_S2AP_R | \ @@ -248,6 +250,7 @@ enum kvm_pgtable_stage2_flags { * @KVM_PGTABLE_PROT_R: Read permission. * @KVM_PGTABLE_PROT_DEVICE: Device attributes. * @KVM_PGTABLE_PROT_NORMAL_NC: Normal noncacheable attributes. + * @KVM_PGTABLE_PROT_DBM: Dirty bit management attribute. * @KVM_PGTABLE_PROT_SW0: Software bit 0. * @KVM_PGTABLE_PROT_SW1: Software bit 1. * @KVM_PGTABLE_PROT_SW2: Software bit 2. @@ -263,6 +266,7 @@ enum kvm_pgtable_prot { KVM_PGTABLE_PROT_DEVICE =3D BIT(4), KVM_PGTABLE_PROT_NORMAL_NC =3D BIT(5), + KVM_PGTABLE_PROT_DBM =3D BIT(6), KVM_PGTABLE_PROT_SW0 =3D BIT(55), KVM_PGTABLE_PROT_SW1 =3D BIT(56), diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c index 0e4ddd28ef5d..5b4c46d8dc74 100644 --- a/arch/arm64/kvm/hyp/pgtable.c +++ b/arch/arm64/kvm/hyp/pgtable.c @@ -739,6 +739,9 @@ static int stage2_set_prot_attr(struct kvm_pgtable *pgt= , enum kvm_pgtable_prot p if (prot & KVM_PGTABLE_PROT_W) attr |=3D KVM_PTE_LEAF_ATTR_LO_S2_S2AP_W; + if (prot & KVM_PGTABLE_PROT_DBM) + attr |=3D KVM_PTE_LEAF_ATTR_HI_S2_DBM; + if (!kvm_lpa2_is_enabled()) attr |=3D FIELD_PREP(KVM_PTE_LEAF_ATTR_LO_S2_SH, sh); @@ -1361,6 +1364,9 @@ int kvm_pgtable_stage2_relax_perms(struct kvm_pgtable= *pgt, u64 addr, if (prot & KVM_PGTABLE_PROT_W) set |=3D KVM_PTE_LEAF_ATTR_LO_S2_S2AP_W; + if (prot & KVM_PGTABLE_PROT_DBM) + set |=3D KVM_PTE_LEAF_ATTR_HI_S2_DBM; + ret =3D stage2_set_xn_attr(prot, &xn); if (ret) return ret; -- 2.33.0 From nobody Sat Apr 11 04:34:49 2026 Received: from canpmsgout08.his.huawei.com (canpmsgout08.his.huawei.com [113.46.200.223]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1FFFA242D6C; Wed, 25 Feb 2026 04:04:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.223 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771992269; cv=none; b=u/gmxJAVsFJ/tdRf63F2yV3TCFsGCTrVCpZoYPBakmEaZoO9DmrLbXZ/nlN+DAB9TysBz4Pp8BUVzFFsY4ab02zqhkomnW59fEo0F+Bcr+0D3NYdyb3YmrNWzkOvpag50mgplapUAEBPtyRNE+kAGWFdW54zSn6ntu+rk8tqxZc= ARC-Message-Signature: i=1; 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charset="utf-8" From: eillon Armv9.5 introduces the Hardware Dirty Bit State Structure (HDBSS) feature, indicated by ID_AA64MMFR1_EL1.HAFDBS =3D=3D 0b0100. A CPU capability is add= ed to notify the user of the feature. Add KVM_CAP_ARM_HW_DIRTY_STATE_TRACK ioctl and basic framework for ARM64 HDBSS support. Since the HDBSS buffer size is configurable and cannot be determined at KVM initialization, an IOCTL interface is required. Actually exposing the new capability to user space happens in a later patch. Signed-off-by: eillon Signed-off-by: Tian Zheng --- arch/arm64/include/asm/cpufeature.h | 5 +++++ arch/arm64/kernel/cpufeature.c | 12 ++++++++++++ arch/arm64/tools/cpucaps | 1 + include/uapi/linux/kvm.h | 1 + tools/include/uapi/linux/kvm.h | 1 + 5 files changed, 20 insertions(+) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/c= pufeature.h index 4de51f8d92cb..dcc2e2cad5ad 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -856,6 +856,11 @@ static inline bool system_supports_haft(void) return cpus_have_final_cap(ARM64_HAFT); } +static inline bool system_supports_hdbss(void) +{ + return cpus_have_final_cap(ARM64_HAS_HDBSS); +} + static __always_inline bool system_supports_mpam(void) { return alternative_has_cap_unlikely(ARM64_MPAM); diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index c31f8e17732a..348b0afffc3e 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2124,6 +2124,11 @@ static bool hvhe_possible(const struct arm64_cpu_cap= abilities *entry, return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE); } +static bool has_vhe_hdbss(const struct arm64_cpu_capabilities *entry, int = cope) +{ + return is_kernel_in_hyp_mode() && has_cpuid_feature(entry, cope); +} + bool cpu_supports_bbml2_noabort(void) { /* @@ -2759,6 +2764,13 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, HAFT) }, #endif + { + .desc =3D "Hardware Dirty state tracking structure (HDBSS)", + .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, + .capability =3D ARM64_HAS_HDBSS, + .matches =3D has_vhe_hdbss, + ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, HDBSS) + }, { .desc =3D "CRC32 instructions", .capability =3D ARM64_HAS_CRC32, diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 7261553b644b..f6ece5b85532 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -68,6 +68,7 @@ HAS_VA52 HAS_VIRT_HOST_EXTN HAS_WFXT HAS_XNX +HAS_HDBSS HAFT HW_DBM KVM_HVHE diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 65500f5db379..15ee42cdbd51 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -985,6 +985,7 @@ struct kvm_enable_cap { #define KVM_CAP_ARM_SEA_TO_USER 245 #define KVM_CAP_S390_USER_OPEREXEC 246 #define KVM_CAP_S390_KEYOP 247 +#define KVM_CAP_ARM_HW_DIRTY_STATE_TRACK 248 struct kvm_irq_routing_irqchip { __u32 irqchip; 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charset="utf-8" From: eillon HDBSS is enabled via an ioctl from userspace (e.g. QEMU) at the start of migration. This feature is only supported in VHE mode. Initially, S2 PTEs doesn't contain the DBM attribute. During migration, write faults are handled by user_mem_abort, which relaxes permissions and adds the DBM bit when HDBSS is active. Once DBM is set, subsequent writes no longer trap, as the hardware automatically transitions the page from writable-clean to writable-dirty. KVM does not scan S2 page tables to consume DBM. Instead, when HDBSS is enabled, the hardware observes the clean->dirty transition and records the corresponding page into the HDBSS buffer. During sync_dirty_log, KVM kicks all vCPUs to force VM-Exit, ensuring that check_vcpu_requests flushes the HDBSS buffer and propagates the accumulated dirty information into the userspace-visible dirty bitmap. Add fault handling for HDBSS including buffer full, external abort, and general protection fault (GPF). Signed-off-by: eillon Signed-off-by: Tian Zheng --- arch/arm64/include/asm/esr.h | 5 ++ arch/arm64/include/asm/kvm_host.h | 17 +++++ arch/arm64/include/asm/kvm_mmu.h | 1 + arch/arm64/include/asm/sysreg.h | 11 ++++ arch/arm64/kvm/arm.c | 102 ++++++++++++++++++++++++++++++ arch/arm64/kvm/hyp/vhe/switch.c | 19 ++++++ arch/arm64/kvm/mmu.c | 70 ++++++++++++++++++++ arch/arm64/kvm/reset.c | 3 + 8 files changed, 228 insertions(+) diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h index 81c17320a588..2e6b679b5908 100644 --- a/arch/arm64/include/asm/esr.h +++ b/arch/arm64/include/asm/esr.h @@ -437,6 +437,11 @@ #ifndef __ASSEMBLER__ #include +static inline bool esr_iss2_is_hdbssf(unsigned long esr) +{ + return ESR_ELx_ISS2(esr) & ESR_ELx_HDBSSF; +} + static inline unsigned long esr_brk_comment(unsigned long esr) { return esr & ESR_ELx_BRK64_ISS_COMMENT_MASK; diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 5d5a3bbdb95e..57ee6b53e061 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -55,12 +55,17 @@ #define KVM_REQ_GUEST_HYP_IRQ_PENDING KVM_ARCH_REQ(9) #define KVM_REQ_MAP_L1_VNCR_EL2 KVM_ARCH_REQ(10) #define KVM_REQ_VGIC_PROCESS_UPDATE KVM_ARCH_REQ(11) +#define KVM_REQ_FLUSH_HDBSS KVM_ARCH_REQ(12) #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE |= \ KVM_DIRTY_LOG_INITIALLY_SET) #define KVM_HAVE_MMU_RWLOCK +/* HDBSS entry field definitions */ +#define HDBSS_ENTRY_VALID BIT(0) +#define HDBSS_ENTRY_IPA GENMASK_ULL(55, 12) + /* * Mode of operation configurable with kvm-arm.mode early param. * See Documentation/admin-guide/kernel-parameters.txt for more informatio= n. @@ -84,6 +89,7 @@ int __init kvm_arm_init_sve(void); u32 __attribute_const__ kvm_target_cpu(void); void kvm_reset_vcpu(struct kvm_vcpu *vcpu); void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu); +void kvm_arm_vcpu_free_hdbss(struct kvm_vcpu *vcpu); struct kvm_hyp_memcache { phys_addr_t head; @@ -405,6 +411,8 @@ struct kvm_arch { * the associated pKVM instance in the hypervisor. */ struct kvm_protected_vm pkvm; + + bool enable_hdbss; }; struct kvm_vcpu_fault_info { @@ -816,6 +824,12 @@ struct vcpu_reset_state { bool reset; }; +struct vcpu_hdbss_state { + phys_addr_t base_phys; + u32 size; + u32 next_index; +}; + struct vncr_tlb; struct kvm_vcpu_arch { @@ -920,6 +934,9 @@ struct kvm_vcpu_arch { /* Per-vcpu TLB for VNCR_EL2 -- NULL when !NV */ struct vncr_tlb *vncr_tlb; + + /* HDBSS registers info */ + struct vcpu_hdbss_state hdbss; }; /* diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_= mmu.h index d968aca0461a..3fea8cfe8869 100644 --- a/arch/arm64/include/asm/kvm_mmu.h +++ b/arch/arm64/include/asm/kvm_mmu.h @@ -183,6 +183,7 @@ int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t = guest_ipa, int kvm_handle_guest_sea(struct kvm_vcpu *vcpu); int kvm_handle_guest_abort(struct kvm_vcpu *vcpu); +void kvm_flush_hdbss_buffer(struct kvm_vcpu *vcpu); phys_addr_t kvm_mmu_get_httbr(void); phys_addr_t kvm_get_idmap_vector(void); diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index f4436ecc630c..d11f4d0dd4e7 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -1039,6 +1039,17 @@ #define GCS_CAP(x) ((((unsigned long)x) & GCS_CAP_ADDR_MASK) | \ GCS_CAP_VALID_TOKEN) + +/* + * Definitions for the HDBSS feature + */ +#define HDBSS_MAX_SIZE HDBSSBR_EL2_SZ_2MB + +#define HDBSSBR_EL2(baddr, sz) (((baddr) & GENMASK(55, 12 + sz)) | \ + FIELD_PREP(HDBSSBR_EL2_SZ_MASK, sz)) + +#define HDBSSPROD_IDX(prod) FIELD_GET(HDBSSPROD_EL2_INDEX_MASK, prod) + /* * Definitions for GICv5 instructions */ diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 29f0326f7e00..d64da05e25c4 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -125,6 +125,87 @@ int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) return kvm_vcpu_exiting_guest_mode(vcpu) =3D=3D IN_GUEST_MODE; } +void kvm_arm_vcpu_free_hdbss(struct kvm_vcpu *vcpu) +{ + struct page *hdbss_pg; + + hdbss_pg =3D phys_to_page(vcpu->arch.hdbss.base_phys); + if (hdbss_pg) + __free_pages(hdbss_pg, vcpu->arch.hdbss.size); + + vcpu->arch.hdbss.size =3D 0; +} + +static int kvm_cap_arm_enable_hdbss(struct kvm *kvm, + struct kvm_enable_cap *cap) +{ + unsigned long i; + struct kvm_vcpu *vcpu; + struct page *hdbss_pg =3D NULL; + __u64 size =3D cap->args[0]; + bool enable =3D cap->args[1] ? true : false; + + if (!system_supports_hdbss()) + return -EINVAL; + + if (size > HDBSS_MAX_SIZE) + return -EINVAL; + + if (!enable && !kvm->arch.enable_hdbss) /* Already Off */ + return 0; + + if (enable && kvm->arch.enable_hdbss) /* Already On, can't set size */ + return -EINVAL; + + if (!enable) { /* Turn it off */ + kvm->arch.mmu.vtcr &=3D ~(VTCR_EL2_HD | VTCR_EL2_HDBSS | VTCR_EL2_HA); + + kvm_for_each_vcpu(i, vcpu, kvm) { + /* Kick vcpus to flush hdbss buffer. */ + kvm_vcpu_kick(vcpu); + + kvm_arm_vcpu_free_hdbss(vcpu); + } + + kvm->arch.enable_hdbss =3D false; + + return 0; + } + + /* Turn it on */ + kvm_for_each_vcpu(i, vcpu, kvm) { + hdbss_pg =3D alloc_pages(GFP_KERNEL_ACCOUNT, size); + if (!hdbss_pg) + goto error_alloc; + + vcpu->arch.hdbss =3D (struct vcpu_hdbss_state) { + .base_phys =3D page_to_phys(hdbss_pg), + .size =3D size, + .next_index =3D 0, + }; + } + + kvm->arch.enable_hdbss =3D true; + kvm->arch.mmu.vtcr |=3D VTCR_EL2_HD | VTCR_EL2_HDBSS | VTCR_EL2_HA; + + /* + * We should kick vcpus out of guest mode here to load new + * vtcr value to vtcr_el2 register when re-enter guest mode. + */ + kvm_for_each_vcpu(i, vcpu, kvm) + kvm_vcpu_kick(vcpu); + + return 0; + +error_alloc: + kvm_for_each_vcpu(i, vcpu, kvm) { + if (vcpu->arch.hdbss.base_phys) + kvm_arm_vcpu_free_hdbss(vcpu); + } + + return -ENOMEM; +} + int kvm_vm_ioctl_enable_cap(struct kvm *kvm, struct kvm_enable_cap *cap) { @@ -182,6 +263,11 @@ int kvm_vm_ioctl_enable_cap(struct kvm *kvm, r =3D 0; set_bit(KVM_ARCH_FLAG_EXIT_SEA, &kvm->arch.flags); break; + case KVM_CAP_ARM_HW_DIRTY_STATE_TRACK: + mutex_lock(&kvm->lock); + r =3D kvm_cap_arm_enable_hdbss(kvm, cap); + mutex_unlock(&kvm->lock); + break; default: break; } @@ -471,6 +557,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long = ext) r =3D kvm_supports_cacheable_pfnmap(); break; + case KVM_CAP_ARM_HW_DIRTY_STATE_TRACK: + r =3D system_supports_hdbss(); + break; default: r =3D 0; } @@ -1120,6 +1209,9 @@ static int check_vcpu_requests(struct kvm_vcpu *vcpu) if (kvm_dirty_ring_check_request(vcpu)) return 0; + if (kvm_check_request(KVM_REQ_FLUSH_HDBSS, vcpu)) + kvm_flush_hdbss_buffer(vcpu); + check_nested_vcpu_requests(vcpu); } @@ -1898,7 +1990,17 @@ long kvm_arch_vcpu_unlocked_ioctl(struct file *filp,= unsigned int ioctl, void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *mems= lot) { + /* + * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called + * before reporting dirty_bitmap to userspace. Send a request with + * KVM_REQUEST_WAIT to flush buffer synchronously. + */ + struct kvm_vcpu *vcpu; + + if (!kvm->arch.enable_hdbss) + return; + kvm_make_all_cpus_request(kvm, KVM_REQ_FLUSH_HDBSS); } static int kvm_vm_ioctl_set_device_addr(struct kvm *kvm, diff --git a/arch/arm64/kvm/hyp/vhe/switch.c b/arch/arm64/kvm/hyp/vhe/switc= h.c index 9db3f11a4754..600cbc4f8ae9 100644 --- a/arch/arm64/kvm/hyp/vhe/switch.c +++ b/arch/arm64/kvm/hyp/vhe/switch.c @@ -213,6 +213,23 @@ static void __vcpu_put_deactivate_traps(struct kvm_vcp= u *vcpu) local_irq_restore(flags); } +static void __load_hdbss(struct kvm_vcpu *vcpu) +{ + struct kvm *kvm =3D vcpu->kvm; + u64 br_el2, prod_el2; + + if (!kvm->arch.enable_hdbss) + return; + + br_el2 =3D HDBSSBR_EL2(vcpu->arch.hdbss.base_phys, vcpu->arch.hdbss.size); + prod_el2 =3D vcpu->arch.hdbss.next_index; + + write_sysreg_s(br_el2, SYS_HDBSSBR_EL2); + write_sysreg_s(prod_el2, SYS_HDBSSPROD_EL2); + + isb(); +} + void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu) { host_data_ptr(host_ctxt)->__hyp_running_vcpu =3D vcpu; @@ -220,10 +237,12 @@ void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu) __vcpu_load_switch_sysregs(vcpu); __vcpu_load_activate_traps(vcpu); __load_stage2(vcpu->arch.hw_mmu, vcpu->arch.hw_mmu->arch); + __load_hdbss(vcpu); } void kvm_vcpu_put_vhe(struct kvm_vcpu *vcpu) { + kvm_flush_hdbss_buffer(vcpu); __vcpu_put_deactivate_traps(vcpu); __vcpu_put_switch_sysregs(vcpu); diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index 070a01e53fcb..42b0710a16ce 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -1896,6 +1896,9 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys= _addr_t fault_ipa, if (writable) prot |=3D KVM_PGTABLE_PROT_W; + if (writable && kvm->arch.enable_hdbss && logging_active) + prot |=3D KVM_PGTABLE_PROT_DBM; + if (exec_fault) prot |=3D KVM_PGTABLE_PROT_X; @@ -2033,6 +2036,70 @@ int kvm_handle_guest_sea(struct kvm_vcpu *vcpu) return 0; } +void kvm_flush_hdbss_buffer(struct kvm_vcpu *vcpu) +{ + int idx, curr_idx; + u64 br_el2; + u64 *hdbss_buf; + struct kvm *kvm =3D vcpu->kvm; + + if (!kvm->arch.enable_hdbss) + return; + + curr_idx =3D HDBSSPROD_IDX(read_sysreg_s(SYS_HDBSSPROD_EL2)); + br_el2 =3D HDBSSBR_EL2(vcpu->arch.hdbss.base_phys, vcpu->arch.hdbss.size); + + /* Do nothing if HDBSS buffer is empty or br_el2 is NULL */ + if (curr_idx =3D=3D 0 || br_el2 =3D=3D 0) + return; + + hdbss_buf =3D page_address(phys_to_page(vcpu->arch.hdbss.base_phys)); + if (!hdbss_buf) + return; + + guard(write_lock_irqsave)(&vcpu->kvm->mmu_lock); + for (idx =3D 0; idx < curr_idx; idx++) { + u64 gpa; + + gpa =3D hdbss_buf[idx]; + if (!(gpa & HDBSS_ENTRY_VALID)) + continue; + + gpa &=3D HDBSS_ENTRY_IPA; + kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); + } + + /* reset HDBSS index */ + write_sysreg_s(0, SYS_HDBSSPROD_EL2); + vcpu->arch.hdbss.next_index =3D 0; + isb(); +} + +static int kvm_handle_hdbss_fault(struct kvm_vcpu *vcpu) +{ + u64 prod; + u64 fsc; + + prod =3D read_sysreg_s(SYS_HDBSSPROD_EL2); + fsc =3D FIELD_GET(HDBSSPROD_EL2_FSC_MASK, prod); + + switch (fsc) { + case HDBSSPROD_EL2_FSC_OK: + /* Buffer full, which is reported as permission fault. */ + kvm_flush_hdbss_buffer(vcpu); + return 1; + case HDBSSPROD_EL2_FSC_ExternalAbort: + case HDBSSPROD_EL2_FSC_GPF: + return -EFAULT; + default: + /* Unknown fault. */ + WARN_ONCE(1, + "Unexpected HDBSS fault type, FSC: 0x%llx (prod=3D0x%llx, vcpu=3D%d)\n= ", + fsc, prod, vcpu->vcpu_id); + return -EFAULT; + } +} + /** * kvm_handle_guest_abort - handles all 2nd stage aborts * @vcpu: the VCPU pointer @@ -2071,6 +2138,9 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu) is_iabt =3D kvm_vcpu_trap_is_iabt(vcpu); + if (esr_iss2_is_hdbssf(esr)) + return kvm_handle_hdbss_fault(vcpu); + if (esr_fsc_is_translation_fault(esr)) { /* Beyond sanitised PARange (which is the IPA limit) */ if (fault_ipa >=3D BIT_ULL(get_kvm_ipa_limit())) { diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c index 959532422d3a..c03a4b310b53 100644 --- a/arch/arm64/kvm/reset.c +++ b/arch/arm64/kvm/reset.c @@ -161,6 +161,9 @@ void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu) free_page((unsigned long)vcpu->arch.ctxt.vncr_array); kfree(vcpu->arch.vncr_tlb); kfree(vcpu->arch.ccsidr); + + if (vcpu->kvm->arch.enable_hdbss) + kvm_arm_vcpu_free_hdbss(vcpu); } static void kvm_vcpu_reset_sve(struct kvm_vcpu *vcpu) -- 2.33.0 From nobody Sat Apr 11 04:34:49 2026 Received: from canpmsgout08.his.huawei.com (canpmsgout08.his.huawei.com [113.46.200.223]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54D96246788; Wed, 25 Feb 2026 04:04:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.223 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771992269; cv=none; b=KFnvbTkFDXGN5tmB8nRfqVgfdCtODulYA+UkGSrntt5HCq33p0dDDGh6L2Xc9DEi10AE/5RRsiXSY5qiMQJY8s9oEgIZ/+8J5ErqOi3LoUoKku+rD4eoiBmiiYTQt8hb/zLk2JsYf8GLiypELazF7AszT09pv5sLLd81xCTVMzA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771992269; c=relaxed/simple; bh=ufqMb//4EynTfTeBtA6ZVMpY+esPq4UpGRbeRU+KkQE=; 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charset="utf-8" A new ioctl (KVM_CAP_ARM_HW_DIRTY_STATE_TRACK) provides a mechanism for userspace to configure the HDBSS buffer size during live migration, enabling hardware-assisted dirty page tracking. Signed-off-by: eillon Signed-off-by: Tian Zheng --- Documentation/virt/kvm/api.rst | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index fc5736839edd..2b5531d40d02 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -8896,6 +8896,22 @@ helpful if user space wants to emulate instructions = which are not This capability can be enabled dynamically even if VCPUs were already created and are running. +7.47 KVM_CAP_ARM_HW_DIRTY_STATE_TRACK +---------------------------- + +:Architectures: arm64 +:Type: VM +:Parameters: args[0] is the allocation order determining HDBSS buffer size + args[1] is 0 to disable, 1 to enable HDBSS +:Returns: 0 on success, negative value on failure + +Enables hardware-assisted dirty page tracking via the Hardware Dirty State +Tracking Structure (HDBSS). + +When live migration is initiated, userspace can enable this feature by +setting KVM_CAP_ARM_HW_DIRTY_STATE_TRACK through IOCTL. KVM will allocate +per-vCPU HDBSS buffers. + 8. Other capabilities. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -- 2.33.0