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[188.141.3.146]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43970d3fc12sm32445600f8f.24.2026.02.25.06.59.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Feb 2026 06:59:23 -0800 (PST) From: Bryan O'Donoghue Date: Wed, 25 Feb 2026 14:59:12 +0000 Subject: [PATCH v2 1/2] dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260225-x1e-csi2-phy-v2-1-7756edb67ea9@linaro.org> References: <20260225-x1e-csi2-phy-v2-0-7756edb67ea9@linaro.org> In-Reply-To: <20260225-x1e-csi2-phy-v2-0-7756edb67ea9@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong Cc: Bryan O'Donoghue , Vladimir Zapolskiy , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=4179; i=bryan.odonoghue@linaro.org; h=from:subject:message-id; bh=Fb14ZMbHWSFCbI5l4Xnt+AafwH2WdWeazS5XcLdJBpU=; b=owEBbQKS/ZANAwAKASJxO7Ohjcg6AcsmYgBpnw5KQp00QBm1YfmKi8Vnt75xPXqZLRcezK6mA cnFmoYNfzyJAjMEAAEKAB0WIQTmk/sqq6Nt4Rerb7QicTuzoY3IOgUCaZ8OSgAKCRAicTuzoY3I OieiD/43WKOywRAOYv7f9nhA9QwcmaDbv+zwkgk3wp3uuFyL5HIpvv2wpMRbX4y1XGE78oZr0m2 vzKzCuReM6ITwwln0eMYDrggcAOIHe43YvBmN0pP8dcQBhLf8NQw1FeTTBr6uXgqJtb2dwT5N0s OqVm4t3Oz76t+QigA7I3l7kJl7nZB7/wOygvvjKNGcl0BhqiLuKQhKh6NOwqMK+K8OxlMfzIWRm 66/5q7b7PmR+W4VEf5HSiyfiwS4cqppKAReoHcxDua1dMOfT8RHewQMm4RYVMx0mdJdrGIi4fMe GiOE+A3yet91W3WnLPVFIuGCDFxGL5mCp3sTuzchC/wT/sW6gXhHmEhyvhIpiaVaM61ff1Jd3iO 1bDy6OMoA5EwLv6sklQO+4tLTyBMcaeRPlkniXg05Y20D8U/W4gcct6lVz1pXgQgwQqbD5nv0CP uLnE7N/qZc4dPh461Ii8qekDUCIBfc1/qjfDwzPXAwXlCb0CCH26tZBuu6p9LM0/nhc4f2UKWuX kBvIzYU1lPYkhTudfZlSlOz7gTGQy37n9TK+GToQ+l+ERG1uIERlMWr3wBzZd0ouxIaSL/LSEx8 0RZmxE2hR2MTP6kmSQ1BDugtJHlfOLBNo+CGGCzwQbB6ZDVxJqDvMvIqcuwYwz2p9373I0rbRLh x2xwN4gV0D4Pwxg== X-Developer-Key: i=bryan.odonoghue@linaro.org; a=openpgp; fpr=E693FB2AABA36DE117AB6FB422713BB3A18DC83A Add a base schema initially compatible with x1e80100 to describe MIPI CSI2 PHY devices. The hardware can support both C-PHY and D-PHY modes. The CSIPHY devices have their own pinouts on the SoC as well as their own individual voltage rails. The need to model voltage rails on a per-PHY basis leads us to define CSIPHY devices as individual nodes. Two nice outcomes in terms of schema and DT arise from this change. 1. The ability to define on a per-PHY basis voltage rails. 2. The ability to require those voltage. We have had a complete bodge upstream for this where a single set of voltage rail for all CSIPHYs has been buried inside of CAMSS. Much like the I2C bus which is dedicated to Camera sensors - the CCI bus in CAMSS parlance, the CSIPHY devices should be individually modelled. Signed-off-by: Bryan O'Donoghue Reviewed-by: Christopher Obbard --- .../bindings/phy/qcom,x1e80100-csi2-phy.yaml | 114 +++++++++++++++++= ++++ 1 file changed, 114 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.y= aml b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml new file mode 100644 index 0000000000000..c937d26ccbda9 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,x1e80100-csi2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm CSI2 PHY + +maintainers: + - Bryan O'Donoghue + +description: + Qualcomm MIPI CSI2 C-PHY/D-PHY combination PHY. Connects MIPI CSI2 senso= rs + to Qualcomm's Camera CSI Decoder. The PHY supports both C-PHY and D-PHY + modes. + +properties: + compatible: + const: qcom,x1e80100-csi2-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 1 + + clocks: + maxItems: 4 + + clock-names: + items: + - const: csiphy + - const: csiphy_timer + - const: camnoc_axi + - const: cpas_ahb + + interrupts: + maxItems: 1 + + operating-points-v2: + maxItems: 1 + + power-domains: + maxItems: 1 + + vdda-0p8-supply: + description: Phandle to a 0.8V regulator supply to a PHY. + + vdda-1p2-supply: + description: Phandle to 1.2V regulator supply to a PHY. + +required: + - compatible + - reg + - "#phy-cells" + - clocks + - clock-names + - interrupts + - operating-points-v2 + - power-domains + - vdda-0p8-supply + - vdda-1p2-supply + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + csiphy@ace4000 { + compatible =3D "qcom,x1e80100-csi2-phy"; + reg =3D <0x0ace4000 0x2000>; + #phy-cells =3D <1>; + + clocks =3D <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-names =3D "csiphy", + "csiphy_timer", + "camnoc_axi", + "cpas_ahb"; + + operating-points-v2 =3D <&csiphy_opp_table>; + + interrupts =3D ; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + vdda-0p8-supply =3D <&vreg_l2c_0p8>; + vdda-1p2-supply =3D <&vreg_l1c_1p2>; + }; + + csiphy_opp_table: opp-table-csiphy { + compatible =3D "operating-points-v2"; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz =3D /bits/ 64 <480000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + }; --=20 2.52.0