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Wed, 25 Feb 2026 02:12:18 -0800 (PST) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2adda769518sm14443135ad.82.2026.02.25.02.12.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Feb 2026 02:12:18 -0800 (PST) From: Taniya Das Date: Wed, 25 Feb 2026 15:42:12 +0530 Subject: [PATCH v3] arm64: dts: qcom: sm8750: Add camera clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260225-sm8750_camcc_dt-v3-1-a19d3173a160@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIAPvKnmkC/3XNSwrCMBCA4auUrE3JswmuvIdIienUBkyjSQ1K6 d1NC67UzcA/MN/MKEF0kNC+mlGE7JILYwm+q5AdzHgB7LrSiBEmKSMcJ6+VJK013tq2mzCXxOi OUcVVg8rVLULvnpt4PJUeXJpCfG0PMl23/61MMcWCamgkEBCgDyGl+v4wVxu8r8tAK5nZh2kIY +SbYYUBcVa96bnUUvxglmV5Ay2fPbH8AAAA X-Change-ID: 20251203-sm8750_camcc_dt-350a8d217376 To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjI1MDA5OSBTYWx0ZWRfX6luaIcn38pNm FzLRe6Uf0sxEXIhK/IH8Opu6BnjOPkY+UC8PIK3Y391Q6gr2PPPaHyvUsHv+wDvpaeR038UWaDE 1ILiUukV9mG5WJ4U0nWJAYII6yE2ifEEkxCFnt8PX5Zu4D4X8CpaNs9uxjlENaNjrHi/UMPa1nJ EJVY5nV0Yb6bXLP2P/GrEDmUduKsntjmFWTdoUbP4zDqMauUIKwfQwhPbFxwZMxT8LkPJ4M4EsR 77apSpNEHQnyixopUj76Bs0SSaakhf2HzRI6rS8Dp8nOMUfDxeUm1CplMFlDBCpE1/amZQGX2pt rDgyXzZh3AHi/51EqM94vtydAnq1u3AHyAIbTziYYBJ9JRVhtgEBKfy/LozzjNok7DPca1blGYT hQoCWDE2PHEFy9HXCgOFfp5Ulh0B++CP436hhR8Q42zKGLLWDS4xEnSdS2gTquvIEcL4VbvxDx1 e1fdrL/yP9II2vVPiSw== X-Authority-Analysis: v=2.4 cv=FvoIPmrq c=1 sm=1 tr=0 ts=699ecb03 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=YRkI6OSQ6ZkYtCvnlTgA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-GUID: 8ZbYVLSoJ_1C9QipTorplU007mXkr20S X-Proofpoint-ORIG-GUID: 8ZbYVLSoJ_1C9QipTorplU007mXkr20S X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-24_03,2026-02-23_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 priorityscore=1501 clxscore=1015 adultscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602250099 The camera clock controller is split into cambistmclk and camcc. The cambist clock controller handles the mclks and the rest of the clocks of camera are part of the camcc clock controller. Add the camcc clock controller device node for SM8750 SoC. Reviewed-by: Abel Vesa Signed-off-by: Taniya Das --- Changes in v3: - Update the Mx phandle to use MXC for camcc node as it is a always ON rail and can sustain this usecase. - Link to v2: https://lore.kernel.org/r/20260220-sm8750_camcc_dt-v2-1-e4b7f= af35854@oss.qualcomm.com Changes in v2: - Update the MxC phandle to use MX for camcc node. - Add RB tag [Abel Vesa] and update the commit message. - Link to v1: https://lore.kernel.org/r/20251203-sm8750_camcc_dt-v1-1-418e6= 5e0e4e8@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 37 ++++++++++++++++++++++++++++++++= +++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qco= m/sm8750.dtsi index 3f0b57f428bbb388521c27d9ae96bbef3d62b2e2..fa3d933f26600e42cedc5474228= 71cf12bdc6778 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -2,7 +2,8 @@ /* * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ - +#include +#include #include #include #include @@ -2046,6 +2047,23 @@ aggre2_noc: interconnect@1700000 { clocks =3D <&rpmhcc RPMH_IPA_CLK>; }; =20 + cambistmclkcc: clock-controller@1760000 { + compatible =3D "qcom,sm8750-cambistmclkcc"; + reg =3D <0x0 0x1760000 0x0 0x6000>; + clocks =3D <&gcc GCC_CAM_BIST_MCLK_AHB_CLK> , + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MX>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + mmss_noc: interconnect@1780000 { compatible =3D "qcom,sm8750-mmss-noc"; reg =3D <0x0 0x01780000 0x0 0x5b800>; @@ -2740,6 +2758,23 @@ usb_dwc3_ss: endpoint { }; }; =20 + camcc: clock-controller@ade0000 { + compatible =3D "qcom,sm8750-camcc"; + reg =3D <0x0 0xade0000 0x0 0x20000>; + clocks =3D <&gcc GCC_CAMERA_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + pdc: interrupt-controller@b220000 { compatible =3D "qcom,sm8750-pdc", "qcom,pdc"; reg =3D <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; --- base-commit: 47b7b5e32bb7264b51b89186043e1ada4090b558 change-id: 20251203-sm8750_camcc_dt-350a8d217376 Best regards, --=20 Taniya Das