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[188.141.3.146]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483bfba9a5esm33950695e9.4.2026.02.25.07.11.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Feb 2026 07:11:27 -0800 (PST) From: Bryan O'Donoghue Date: Wed, 25 Feb 2026 15:11:19 +0000 Subject: [PATCH v8 02/18] dt-bindings: media: qcom,x1e80100-camss: Convert from inline PHY definitions to PHY handles Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260225-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v8-2-95517393bcb2@linaro.org> References: <20260225-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v8-0-95517393bcb2@linaro.org> In-Reply-To: <20260225-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v8-0-95517393bcb2@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Konrad Dybcio , Vladimir Zapolskiy , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, Bryan O'Donoghue , Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=8029; i=bryan.odonoghue@linaro.org; h=from:subject:message-id; bh=DcA3V6DF2BA2QJePYEKIHuVBmYletxrgnzHZXIVjZ8g=; b=owEBbQKS/ZANAwAKASJxO7Ohjcg6AcsmYgBpnxEZUTlnMTFouzw4B6WU01P4kpYkelCY5Wf5k r2BmmBTG2WJAjMEAAEKAB0WIQTmk/sqq6Nt4Rerb7QicTuzoY3IOgUCaZ8RGQAKCRAicTuzoY3I OkyeEACFsYnUDJjs3w9OvZ+590MQb9cixoRKyCTSECKufPS9VpjGOltXi7+yTUvGe1CIXLlBuYH mnx4UGCVmX0rzkPCrPqjnU2xjJ9PtH8SUHp1fXVNUyaDByAzMUXK0Hmajz9RnGK7L64qCiePZjL sQY1Q9WxJVuoFp8lpDx4gBEZj9g10lcvaDWHnnTxlDeSi1ctXLldeBtWXv5caPttlFd43RL1/4n oGbDb3V/A/hlkfrKmPY4EMQhFBqnG2S6npxUUV21kZVg1mQCB+ctAaHDcO83L1sK290/dZ7xmQ9 WCxbXNI6D+OVX58vcSps2VNArVVCe8RdegUzrB+jRJPy+u/X3Nsff5rfr791JI7ycyABE+1HSLg oS3aib2bxCdhB7lsCgVXnBQx+IOUVf6hZ/mFmoloN9Ex/HQGRobn+XX6ZU7yickXYH32amQf0RW L6K5viGHGaQB6JssKKPrZmr88eoeK2ULRXNIiqKqZjZEVY9tf2VDISs83alGmeWyBOWjNcTZAmm 362axR0Xc5ExLdcaklzwf78D2ga0zIQzSoegVQOznUf5EVXRDJdS5YbLgcxy7jdw89JECmr++Hb D7yswAldHDstwre716pzj8gd12O2Pr34iX9b7592fSEbk1DxTylNcwx1PAaDH+mCmyyUG/G06rx UfKDhdWFjZ97eTQ== X-Developer-Key: i=bryan.odonoghue@linaro.org; a=openpgp; fpr=E693FB2AABA36DE117AB6FB422713BB3A18DC83A We currently do not have an upstream user of the x1e CAMSS schema which allows us to make this the first platform to treat the CSI PHYs as separate devices in much the same way as we treat the CCI block as separate devices. Convert the embedded CSIPHY node data to simple phys =3D <> removing all of the PHY specific stuff previously embedded. I gave some serious thought to making the Test Pattern Generators TPGs into PHY nodes also but, unlike the CSIPHYs the TPGs have no dedicated external pins nor regulators. The CSIPHYs OTOH have dedicated in-fact generally unmuxed pins on Qualcomm SoCs and each CSIPHY has its own set of input power rails usually 0p8 and 1p2. Instead of defining the CSIPHYs as children of the CAMSS block, we take the same approach as the CCI/I2C bus dedicated to CAMSS and define the CSIPHYs as their own nodes. Remove the embedded CSIPHY specific data and give CAMSS regular, bog-standard phys =3D <>; Signed-off-by: Bryan O'Donoghue Reviewed-by: Christopher Obbard --- .../bindings/media/qcom,x1e80100-camss.yaml | 84 ++++++------------= ---- 1 file changed, 20 insertions(+), 64 deletions(-) diff --git a/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.ya= ml b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml index 9aaed897f7e0e..ff14a8248321e 100644 --- a/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml @@ -17,7 +17,7 @@ properties: const: qcom,x1e80100-camss =20 reg: - maxItems: 17 + maxItems: 13 =20 reg-names: items: @@ -27,10 +27,6 @@ properties: - const: csid2 - const: csid_lite0 - const: csid_lite1 - - const: csiphy0 - - const: csiphy1 - - const: csiphy2 - - const: csiphy4 - const: csitpg0 - const: csitpg1 - const: csitpg2 @@ -40,7 +36,7 @@ properties: - const: vfe_lite1 =20 clocks: - maxItems: 29 + maxItems: 21 =20 clock-names: items: @@ -55,14 +51,6 @@ properties: - const: cphy_rx_clk_src - const: csid - const: csid_csiphy_rx - - const: csiphy0 - - const: csiphy0_timer - - const: csiphy1 - - const: csiphy1_timer - - const: csiphy2 - - const: csiphy2_timer - - const: csiphy4 - - const: csiphy4_timer - const: gcc_axi_hf - const: gcc_axi_sf - const: vfe0 @@ -75,7 +63,7 @@ properties: - const: vfe_lite_csid =20 interrupts: - maxItems: 13 + maxItems: 9 =20 interrupt-names: items: @@ -84,15 +72,21 @@ properties: - const: csid2 - const: csid_lite0 - const: csid_lite1 - - const: csiphy0 - - const: csiphy1 - - const: csiphy2 - - const: csiphy4 - const: vfe0 - const: vfe1 - const: vfe_lite0 - const: vfe_lite1 =20 + phys: + maxItems: 4 + + phy-names: + items: + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy4 + interconnects: maxItems: 4 =20 @@ -118,14 +112,6 @@ properties: - const: ife1 - const: top =20 - vdd-csiphy-0p8-supply: - description: - 0.8V supply to a PHY. - - vdd-csiphy-1p2-supply: - description: - 1.2V supply to a PHY. - ports: $ref: /schemas/graph.yaml#/properties/ports =20 @@ -166,13 +152,13 @@ required: - clock-names - interrupts - interrupt-names + - phys + - phy-names - interconnects - interconnect-names - iommus - power-domains - power-domain-names - - vdd-csiphy-0p8-supply - - vdd-csiphy-1p2-supply - ports =20 additionalProperties: false @@ -199,10 +185,6 @@ examples: <0 0x0acbb000 0 0x2000>, <0 0x0acc6000 0 0x1000>, <0 0x0acca000 0 0x1000>, - <0 0x0ace4000 0 0x1000>, - <0 0x0ace6000 0 0x1000>, - <0 0x0ace8000 0 0x1000>, - <0 0x0acec000 0 0x4000>, <0 0x0acf6000 0 0x1000>, <0 0x0acf7000 0 0x1000>, <0 0x0acf8000 0 0x1000>, @@ -217,10 +199,6 @@ examples: "csid2", "csid_lite0", "csid_lite1", - "csiphy0", - "csiphy1", - "csiphy2", - "csiphy4", "csitpg0", "csitpg1", "csitpg2", @@ -240,14 +218,6 @@ examples: <&camcc CAM_CC_CPHY_RX_CLK_SRC>, <&camcc CAM_CC_CSID_CLK>, <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, - <&camcc CAM_CC_CSIPHY0_CLK>, - <&camcc CAM_CC_CSI0PHYTIMER_CLK>, - <&camcc CAM_CC_CSIPHY1_CLK>, - <&camcc CAM_CC_CSI1PHYTIMER_CLK>, - <&camcc CAM_CC_CSIPHY2_CLK>, - <&camcc CAM_CC_CSI2PHYTIMER_CLK>, - <&camcc CAM_CC_CSIPHY4_CLK>, - <&camcc CAM_CC_CSI4PHYTIMER_CLK>, <&gcc GCC_CAMERA_HF_AXI_CLK>, <&gcc GCC_CAMERA_SF_AXI_CLK>, <&camcc CAM_CC_IFE_0_CLK>, @@ -270,14 +240,6 @@ examples: "cphy_rx_clk_src", "csid", "csid_csiphy_rx", - "csiphy0", - "csiphy0_timer", - "csiphy1", - "csiphy1_timer", - "csiphy2", - "csiphy2_timer", - "csiphy4", - "csiphy4_timer", "gcc_axi_hf", "gcc_axi_sf", "vfe0", @@ -294,10 +256,6 @@ examples: , , , - , - , - , - , , , , @@ -308,15 +266,16 @@ examples: "csid2", "csid_lite0", "csid_lite1", - "csiphy0", - "csiphy1", - "csiphy2", - "csiphy4", "vfe0", "vfe1", "vfe_lite0", "vfe_lite1"; =20 + phys =3D <&csiphy0>, <&csiphy1>, + <&csiphy2>, <&csiphy4>; + phy-names =3D "csiphy0", "csiphy1", + "csiphy2", "csiphy4"; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACT= IVE_ONLY &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACT= IVE_ONLY>, <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS @@ -348,9 +307,6 @@ examples: "ife1", "top"; =20 - vdd-csiphy-0p8-supply =3D <&csiphy_0p8_supply>; - vdd-csiphy-1p2-supply =3D <&csiphy_1p2_supply>; - ports { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.52.0