From nobody Thu Apr 2 20:28:05 2026 Received: from mail-pf1-f170.google.com (mail-pf1-f170.google.com [209.85.210.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2DC7396B91 for ; Tue, 24 Feb 2026 12:20:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771935616; cv=none; b=VgH1Edq4+PQTiTos131uJXX/hUWpcs+iu7ELvpuFtSx8kpMnI9/aGqxqZHmw4UbPX/HlugBaQLmH0d3KADle6wg3QNkDchxmalxej5gxyY4hgO15erN5ebVPIIVYDVY1ePyc46MlacUouTWXh11QxqLtpiazYG4hQfMqQzccxd8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771935616; c=relaxed/simple; bh=QaNNOaPvOwZt/4ZjkTmZmmwp/cdF2i55gJPCoB3rWWo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ODMJmpznyxFACoKFZabH13F7K7mY/YfKJkJQmMN8cYMku/2ZuyCjP1zeQq9y5dIQRwc39Y165gyn6n4KqX/6FY3QU5D1RunnEbm9PcdOyG34fF3Fq+K5Vr36EsvHFmoZj3rAEff4jhRrW8Ndm9CkFbWqw6sThQiaBmblIG5fDfs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=XLvdLeJo; arc=none smtp.client-ip=209.85.210.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="XLvdLeJo" Received: by mail-pf1-f170.google.com with SMTP id d2e1a72fcca58-824a3ba5222so2925753b3a.2 for ; Tue, 24 Feb 2026 04:20:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1771935613; x=1772540413; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0CP5OxruqqO0puoKPcOnExnL6WZ3FoqgbnMXhY33wB8=; b=XLvdLeJoEq2DJx0dPItPStEpKCAaQ92/NCuO6YeQLBxX9tmEqjDWkTJFoYObBwWbZj mc7lKHoCg5StNaksB+hjk11YumpNC2wU308M5ebRqb/9CqGlww5dfD/o5EZKTwFiay9E gqjxA3q8KSubNq02V5oq5b+wCdSDsHJCvaKOG/pbM8MzLn6xOiLvJN1Q4t1SaJ9WTAQj J+lf8dWyTY8maNIy2oGv4mScPua/SP2dIJ9oR/GRSqezaM7oEm+RFxGb7j3EuTN9L6+9 avuYOl5cz5gHyaLSJt12+WGGmYKWyr8p4wqo6cjp1zqqV7N4dkel9KHF4XZDBtMdH/Hy aKGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771935613; x=1772540413; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=0CP5OxruqqO0puoKPcOnExnL6WZ3FoqgbnMXhY33wB8=; b=oT5AHx4hBDWc7gy3htHISvi1Ki5m/IGcSNtErj9e2dzYtiTF4NMokY2UsZeSMUwJNT CVC474T2YGYT+VDwQB2eeVLdZDBH25NiGPeK+R3Ft9gsL8mfRpdoIuPgA2R8Y4fnu7oi 2qTPKAm/pkPLij00PTz2vBt74tjV23MG99MzrqZkA02UFaRZAT6sS6iQKnwSNXexjZRX YPeZ+E7DiGxJRY9YV3ablWv/BAckFaIEXUbAMqGocLg4yLgjhQxYKckfWPMt6WLb0R8r p/Nh6tQid+shUzqNSDocEjk+A/Qp+hiTHCjphLFPKNxfOJAgWOKFoFz5SmXr9MKu22t+ aTvA== X-Forwarded-Encrypted: i=1; AJvYcCWwNCnhDrmI0cpTh7+HpCCAZgADHOzrCUdeSRoi9CFf5e3hqljQ8MpV7IuBMysdSH/VaVf4F4A3lQSDnd4=@vger.kernel.org X-Gm-Message-State: AOJu0YzgcdEmRdeBpN8hYtC/QrDNSNi8TOy9j3TvSuiQGMpjSelkVj/e www/GhLHADwh6eB42OSvnW92q9FUFrTkzDg6MZ0jAn1WD0yG4+1chsFW X-Gm-Gg: ATEYQzzPkpZZtJ4KpRZf5LwMORb5hvBvH/T7qacpIBIPLMJfZHOg9aihD1+jWFNLvVV knEoD6qsypcaae6RfMOmlKeyxGC3GjVJ4TA9SzXSosnuo6CY+KB1ZbNGs2mjSVwDQrpkGodhRQI oUzHurigqoum5XmvPpKnDtCtlvkwbRl4oBUkHntwwuhMVeexVs+xHBb6pltOM37gBgzhxYt0vmL T5LRRKernWV3pIK/XOjcjq/+1KcVpo1XOyS4CFZ14HDkrQ5P0eysakwFpsGo1hJoLogDfKR+ELb T7wlFoqufzrsydcTakYgdribqaib3JbZ5JG6memsYn8xzbUmAZZmQAu16tfsgMqaxOIhkfa/cN4 AnGXToaKfTdUIaA8AUXcTCOlrGj1+7+y/bNkgf0i8Zb5tUPIfJCtTQYUSkifFG4/pqt5lJxTb/c Ea3whKsa0DbPo1Te0Dd9w= X-Received: by 2002:a05:6a00:1f04:b0:821:70e7:b10a with SMTP id d2e1a72fcca58-826da8e2c6fmr9454127b3a.8.1771935612996; Tue, 24 Feb 2026 04:20:12 -0800 (PST) Received: from rockpi-5b ([45.112.0.78]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-826dd8ba11bsm10613950b3a.50.2026.02.24.04.20.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Feb 2026 04:20:12 -0800 (PST) From: Anand Moon To: Thierry Reding , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Hunter , Aaron Kling , linux-tegra@vger.kernel.org (open list:PCI DRIVER FOR NVIDIA TEGRA), linux-pci@vger.kernel.org (open list:PCI DRIVER FOR NVIDIA TEGRA), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [PATCH v3 1/5] dt-bindings: PCI: Convert nvidia,tegra-pcie to DT schema Date: Tue, 24 Feb 2026 17:48:57 +0530 Message-ID: <20260224121948.25218-2-linux.amoon@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260224121948.25218-1-linux.amoon@gmail.com> References: <20260224121948.25218-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert the existing text-based DT bindings documentation for the NVIDIA Tegra PCIe host controller to a DT schema format. Also update the MAINTAINERS file to reflect this change. Cc: Jon Hunter Signed-off-by: Anand Moon --- v3: Tried to address the issues Krzysztof pointed out. Added missing regulator binding as suggeested by Jon. v2: Tried to address the isssue Rob pointed [1] https://lkml.org/lkml/2025/9/26/704 improve the $suject and commit message drop few examples only nvidia,tegra20-pcie and nvidia,tegra210-pcie $ make dt_binding_check DT_SCHEMA_FILES=3DDocumentation/devicetree/bindings= /pci/nvidia,tegra-pcie.yaml --- .../bindings/pci/nvidia,tegra-pcie.yaml | 528 ++++++++++++++ .../bindings/pci/nvidia,tegra20-pcie.txt | 670 ------------------ MAINTAINERS | 2 +- 3 files changed, 529 insertions(+), 671 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra-pcie= .yaml delete mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra20-pc= ie.txt diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra-pcie.yaml b= /Documentation/devicetree/bindings/pci/nvidia,tegra-pcie.yaml new file mode 100644 index 000000000000..0675bec205e8 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra-pcie.yaml @@ -0,0 +1,528 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/nvidia,tegra-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra PCIe Controller + +maintainers: + - Jon Hunter + - Thierry Reding + +description: + PCIe controller found on NVIDIA Tegra SoCs which supports multiple + root ports and platform-specific clock, reset, and power supply + configurations. + +properties: + compatible: + enum: + - nvidia,tegra20-pcie + - nvidia,tegra30-pcie + - nvidia,tegra124-pcie + - nvidia,tegra210-pcie + - nvidia,tegra186-pcie + + reg: + items: + - description: PADS registers + - description: AFI registers + - description: Configuration space region + + reg-names: + items: + - const: pads + - const: afi + - const: cs + + interrupts: + items: + - description: Controller interrupt + - description: MSI interrupt + + interrupt-names: + items: + - const: intr + - const: msi + + clocks: + minItems: 3 + items: + - description: PCIe clock + - description: AFI clock + - description: PLL_E clock + - description: Optional CML clock + + clock-names: + description: Names of clocks used by the PCIe controller + minItems: 3 + items: + - const: pex + - const: afi + - const: pll_e + - const: cml + + resets: + items: + - description: PCIe reset + - description: AFI reset + - description: PCIe-X reset + + reset-names: + items: + - const: pex + - const: afi + - const: pcie_x + + power-domains: + maxItems: 1 + + interconnects: + minItems: 1 + maxItems: 2 + + interconnect-names: + items: + - const: dma-mem + - const: write + + pinctrl-names: + items: + - const: default + - const: idle + + pinctrl-0: true + pinctrl-1: true + + operating-points-v2: + description: + Defines operating points with required frequency and voltage values, + and the opp-supported-hw property. + + iommus: + maxItems: 1 + + avdd-pex-supply: + description: Power supply for analog PCIe logic. Must supply 1.05 V. + + vdd-pex-supply: + description: Power supply for digital PCIe I/O. Must supply 1.05 V. + + avdd-pex-pll-supply: + description: Power supply for dedicated (internal) PCIe PLL. Must supp= ly 1.05 V. + + avdd-plle-supply: + description: Power supply for PLLE, which is shared with SATA. Must su= pply 1.05 V. + + vddio-pex-clk-supply: + description: Power supply for PCIe clock. Must supply 3.3 V. + + vddio-pex-ctl-supply: + description: Power supply for PCIe control I/O partition. Must supply = 1.8 V. + + hvdd-pex-supply: + description: High-voltage supply for PCIe I/O and PCIe output clocks. = Must supply 3.3 V. + + avdd-pexa-supply: + description: Power supply for analog PCIe logic. Must supply 1.05 V. + + vdd-pexa-supply: + description: Power supply for digital PCIe I/O. Must supply 1.05 V. + + avdd-pexb-supply: + description: Power supply for analog PCIe logic. Must supply 1.05 V. + + vdd-pexb-supply: + description: Power supply for digital PCIe I/O. Must supply 1.05 V. + + avddio-pex-supply: + description: Power supply for analog PCIe logic. Must supply 1.05 V. + + dvddio-pex-supply: + description: Power supply for digital PCIe I/O. Must supply 1.05 V. + + hvddio-pex-supply: + description: High-voltage supply for PCIe I/O and PCIe output clocks. = Must supply 1.8 V. + + dvdd-pex-supply: + description: Power supply for digital PCIe I/O. Must supply 1.05 V. + + hvdd-pex-pll-supply: + description: High-voltage supply for PLLE (shared with USB3). Must sup= ply 1.8 V. + + vddio-pexctl-aud-supply: + description: Power supply for PCIe side band signals. Must supply 1.8 = V. + +patternProperties: + "^pci@[0-9a-f]+(,[0-9a-f]+)?$": + type: object + allOf: + - $ref: /schemas/pci/pci-pci-bridge.yaml# + properties: + reg: + maxItems: 1 + + nvidia,num-lanes: + description: Number of lanes used by this PCIe port + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 4] + + phys: + description: Phandles to PCIe PHYs + items: + maxItems: 1 + minItems: 1 + maxItems: 4 + + phy-names: + description: Names of PCIe PHYs + items: + pattern: "^pcie(-[0-3])?$" + minItems: 1 + maxItems: 4 + + required: + - nvidia,num-lanes + + unevaluatedProperties: false + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra20-pcie + - nvidia,tegra186-pcie + then: + properties: + clocks: + maxItems: 3 + clock-names: + items: + - const: pex + - const: afi + - const: pll_e + resets: + maxItems: 3 + reset-names: + items: + - const: pex + - const: afi + - const: pcie_x + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra30-pcie + - nvidia,tegra124-pcie + - nvidia,tegra210-pcie + then: + properties: + clocks: + maxItems: 4 + clock-names: + items: + - const: pex + - const: afi + - const: pll_e + - const: cml + resets: + maxItems: 3 + reset-names: + items: + - const: pex + - const: afi + - const: pcie_x + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra20-pcie + - nvidia,tegra30-pcie + then: + required: + - power-domains + - operating-points-v2 + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra186-pcie + then: + required: + - interconnects + - iommus + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra210-pcie + then: + required: + - pinctrl-names + - pinctrl-0 + - pinctrl-1 + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra20-pcie + then: + required: + - avdd-pex-supply + - vdd-pex-supply + - avdd-pex-pll-supply + - avdd-plle-supply + - vddio-pex-clk-supply + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra30-pcie + then: + required: + - avdd-pex-pll-supply + - avdd-plle-supply + - vddio-pex-ctl-supply + - hvdd-pex-supply + anyOf: + - required: + - avdd-pexa-supply + - vdd-pexa-supply + - required: + - avdd-pexb-supply + - vdd-pexb-supply + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra124-pcie + then: + required: + - avddio-pex-supply + - dvddio-pex-supply + - hvdd-pex-supply + - vddio-pex-ctl-supply + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra210-pcie + then: + required: + - hvddio-pex-supply + - dvddio-pex-supply + - vddio-pex-ctl-supply + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra186-pcie + then: + required: + - dvdd-pex-supply + - hvdd-pex-pll-supply + - hvdd-pex-supply + - vddio-pexctl-aud-supply + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - resets + - reset-names + - interrupts + - interrupt-map + - interrupt-map-mask + +unevaluatedProperties: false + +examples: + - | + #include + #include + + bus { + #address-cells =3D <1>; + #size-cells =3D <1>; + + pcie@80003000 { + compatible =3D "nvidia,tegra20-pcie"; + device_type =3D "pci"; + reg =3D <0x80003000 0x00000800>, + <0x80003800 0x00000200>, + <0x90000000 0x10000000>; + reg-names =3D "pads", "afi", "cs"; + interrupts =3D , + ; + interrupt-names =3D "intr", "msi"; + interrupt-parent =3D <&intc>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIG= H>; + + bus-range =3D <0x00 0xff>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + ranges =3D <0x02000000 0 0x80000000 0x80000000 0 0x00001000>, + <0x02000000 0 0x80001000 0x80001000 0 0x00001000>, + <0x01000000 0 0 0x82000000 0 0x00010000>, + <0x02000000 0 0xa0000000 0xa0000000 0 0x08000000>, + <0x42000000 0 0xa8000000 0xa8000000 0 0x18000000>; + + clocks =3D <&tegra_car 70>, + <&tegra_car 72>, + <&tegra_car 118>; + clock-names =3D "pex", "afi", "pll_e"; + resets =3D <&tegra_car 70>, + <&tegra_car 72>, + <&tegra_car 74>; + reset-names =3D "pex", "afi", "pcie_x"; + power-domains =3D <&pd_core>; + operating-points-v2 =3D <&pcie_dvfs_opp_table>; + + avdd-pex-supply =3D <®_pex_1v05>; + vdd-pex-supply =3D <®_pex_1v05>; + avdd-pex-pll-supply =3D <®_pexpll_1v05>; + avdd-plle-supply =3D <®_plle_1v05>; + vddio-pex-clk-supply =3D <®_pexclk_3v3>; + + status =3D "okay"; + + pci@1,0 { + device_type =3D "pci"; + assigned-addresses =3D <0x82000800 0 0x80000000 0 0x1000>; + reg =3D <0x000800 0 0 0 0>; + bus-range =3D <0x00 0xff>; + status =3D "okay"; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + + nvidia,num-lanes =3D <2>; + }; + + pci@2,0 { + device_type =3D "pci"; + assigned-addresses =3D <0x82001000 0 0x80001000 0 0x1000>; + reg =3D <0x001000 0 0 0 0>; + bus-range =3D <0x00 0xff>; + status =3D "okay"; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + + nvidia,num-lanes =3D <2>; + }; + }; + }; + - | + #include + #include + + bus { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@1003000 { + compatible =3D "nvidia,tegra210-pcie"; + device_type =3D "pci"; + reg =3D <0x0 0x01003000 0x0 0x00000800>, + <0x0 0x01003800 0x0 0x00000800>, + <0x0 0x02000000 0x0 0x10000000>; + reg-names =3D "pads", "afi", "cs"; + interrupts =3D , + ; + interrupt-names =3D "intr", "msi"; + interrupt-parent =3D <&gic>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH= >; + + bus-range =3D <0x00 0xff>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + ranges =3D <0x02000000 0 0x01000000 0x0 0x01000000 0 0x0000100= 0>, + <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, + <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, + <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, + <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; + + clocks =3D <&tegra_car 70>, + <&tegra_car 72>, + <&tegra_car 263>, + <&tegra_car 300>; + clock-names =3D "pex", "afi", "pll_e", "cml"; + resets =3D <&tegra_car 70>, + <&tegra_car 72>, + <&tegra_car 74>; + reset-names =3D "pex", "afi", "pcie_x"; + + pinctrl-names =3D "default", "idle"; + pinctrl-0 =3D <&pex_dpd_disable>; + pinctrl-1 =3D <&pex_dpd_enable>; + + hvddio-pex-supply =3D <®_pex_1v8>; + dvddio-pex-supply =3D <®_pex_1v05>; + vddio-pex-ctl-supply =3D <®_pexctl_1v8>; + + status =3D "okay"; + + pci@1,0 { + device_type =3D "pci"; + assigned-addresses =3D <0x82000800 0 0x01000000 0 0x1000>; + reg =3D <0x000800 0 0 0 0>; + bus-range =3D <0x00 0xff>; + status =3D "okay"; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + + nvidia,num-lanes =3D <4>; + }; + + pci@2,0 { + device_type =3D "pci"; + assigned-addresses =3D <0x82001000 0 0x01001000 0 0x1000>; + reg =3D <0x001000 0 0 0 0>; + bus-range =3D <0x00 0xff>; + status =3D "okay"; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + + nvidia,num-lanes =3D <1>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt = b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt deleted file mode 100644 index d099f3476ccc..000000000000 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt +++ /dev/null @@ -1,670 +0,0 @@ -NVIDIA Tegra PCIe controller - -Required properties: -- compatible: Must be: - - "nvidia,tegra20-pcie": for Tegra20 - - "nvidia,tegra30-pcie": for Tegra30 - - "nvidia,tegra124-pcie": for Tegra124 and Tegra132 - - "nvidia,tegra210-pcie": for Tegra210 - - "nvidia,tegra186-pcie": for Tegra186 -- power-domains: To ungate power partition by BPMP powergate driver. Must - contain BPMP phandle and PCIe power partition ID. This is required only - for Tegra186. -- device_type: Must be "pci" -- reg: A list of physical base address and length for each set of controll= er - registers. Must contain an entry for each entry in the reg-names propert= y. -- reg-names: Must include the following entries: - "pads": PADS registers - "afi": AFI registers - "cs": configuration space region -- interrupts: A list of interrupt outputs of the controller. Must contain = an - entry for each entry in the interrupt-names property. -- interrupt-names: Must include the following entries: - "intr": The Tegra interrupt that is asserted for controller interrupts - "msi": The Tegra interrupt that is asserted when an MSI is received -- bus-range: Range of bus numbers associated with this controller -- #address-cells: Address representation for root ports (must be 3) - - cell 0 specifies the bus and device numbers of the root port: - [23:16]: bus number - [15:11]: device number - - cell 1 denotes the upper 32 address bits and should be 0 - - cell 2 contains the lower 32 address bits and is used to translate to = the - CPU address space -- #size-cells: Size representation for root ports (must be 2) -- ranges: Describes the translation of addresses for root ports and standa= rd - PCI regions. The entries must be 6 cells each, where the first three cel= ls - correspond to the address as described for the #address-cells property - above, the fourth cell is the physical CPU address to translate to and t= he - fifth and six cells are as described for the #size-cells property above. - - The first two entries are expected to translate the addresses for the = root - port registers, which are referenced by the assigned-addresses propert= y of - the root port nodes (see below). - - The remaining entries setup the mapping for the standard I/O, memory a= nd - prefetchable PCI regions. The first cell determines the type of region - that is setup: - - 0x81000000: I/O memory region - - 0x82000000: non-prefetchable memory region - - 0xc2000000: prefetchable memory region - Please refer to the standard PCI bus binding document for a more detailed - explanation. -- #interrupt-cells: Size representation for interrupts (must be 1) -- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties - Please refer to the standard PCI bus binding document for a more detailed - explanation. -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - pex - - afi - - pll_e - - cml (not required for Tegra20) -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - pex - - afi - - pcie_x - -Optional properties: -- pinctrl-names: A list of pinctrl state names. Must contain the following - entries: - - "default": active state, puts PCIe I/O out of deep power down state - - "idle": puts PCIe I/O into deep power down state -- pinctrl-0: phandle for the default/active state of pin configurations. -- pinctrl-1: phandle for the idle state of pin configurations. - -Required properties on Tegra124 and later (deprecated): -- phys: Must contain an entry for each entry in phy-names. -- phy-names: Must include the following entries: - - pcie - -These properties are deprecated in favour of per-lane PHYs define in each = of -the root ports (see below). - -Power supplies for Tegra20: -- avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V. -- vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. -- avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must - supply 1.05 V. -- avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must - supply 1.05 V. -- vddio-pex-clk-supply: Power supply for PCIe clock. Must supply 3.3 V. - -Power supplies for Tegra30: -- Required: - - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. M= ust - supply 1.05 V. - - avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Mu= st - supply 1.05 V. - - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must - supply 1.8 V. - - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output cloc= ks. - Must supply 3.3 V. -- Optional: - - If lanes 0 to 3 are used: - - avdd-pexa-supply: Power supply for analog PCIe logic. Must supply 1.= 05 V. - - vdd-pexa-supply: Power supply for digital PCIe I/O. Must supply 1.05= V. - - If lanes 4 or 5 are used: - - avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.= 05 V. - - vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05= V. - -Power supplies for Tegra124: -- Required: - - avddio-pex-supply: Power supply for analog PCIe logic. Must supply 1.0= 5 V. - - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05= V. - - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output cloc= ks. - Must supply 3.3 V. - - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must - supply 2.8-3.3 V. - -Power supplies for Tegra210: -- Required: - - hvddio-pex-supply: High-voltage supply for PCIe I/O and PCIe output - clocks. Must supply 1.8 V. - - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05= V. - - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must - supply 1.8 V. - -Power supplies for Tegra186: -- Required: - - dvdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. - - hvdd-pex-pll-supply: High-voltage supply for PLLE (shared with USB3). = Must - supply 1.8 V. - - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output cloc= ks. - Must supply 1.8 V. - - vddio-pexctl-aud-supply: Power supply for PCIe side band signals. Must - supply 1.8 V. - -Root ports are defined as subnodes of the PCIe controller node. - -Required properties: -- device_type: Must be "pci" -- assigned-addresses: Address and size of the port configuration registers -- reg: PCI bus address of the root port -- #address-cells: Must be 3 -- #size-cells: Must be 2 -- ranges: Sub-ranges distributed from the PCIe controller node. An empty - property is sufficient. -- nvidia,num-lanes: Number of lanes to use for this port. Valid combinatio= ns - are: - - Root port 0 uses 4 lanes, root port 1 is unused. - - Both root ports use 2 lanes. - -Required properties for Tegra124 and later: -- phys: Must contain an phandle to a PHY for each entry in phy-names. -- phy-names: Must include an entry for each active lane. Note that the num= ber - of entries does not have to (though usually will) be equal to the specif= ied - number of lanes in the nvidia,num-lanes property. Entries are of the form - "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lan= es. - -Examples: -=3D=3D=3D=3D=3D=3D=3D=3D=3D - -Tegra20: --------- - -SoC DTSI: - - pcie-controller@80003000 { - compatible =3D "nvidia,tegra20-pcie"; - device_type =3D "pci"; - reg =3D <0x80003000 0x00000800 /* PADS registers */ - 0x80003800 0x00000200 /* AFI registers */ - 0x90000000 0x10000000>; /* configuration space */ - reg-names =3D "pads", "afi", "cs"; - interrupts =3D <0 98 0x04 /* controller interrupt */ - 0 99 0x04>; /* MSI interrupt */ - interrupt-names =3D "intr", "msi"; - - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - - bus-range =3D <0x00 0xff>; - #address-cells =3D <3>; - #size-cells =3D <2>; - - ranges =3D <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 = registers */ - 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers= */ - 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0xa0000000 0xa0000000 0 0x10000000 /* non-prefetchable= memory */ - 0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable mem= ory */ - - clocks =3D <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 118>; - clock-names =3D "pex", "afi", "pll_e"; - resets =3D <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>; - reset-names =3D "pex", "afi", "pcie_x"; - status =3D "disabled"; - - pci@1,0 { - device_type =3D "pci"; - assigned-addresses =3D <0x82000800 0 0x80000000 0 0x1000>; - reg =3D <0x000800 0 0 0 0>; - status =3D "disabled"; - - #address-cells =3D <3>; - #size-cells =3D <2>; - - ranges; - - nvidia,num-lanes =3D <2>; - }; - - pci@2,0 { - device_type =3D "pci"; - assigned-addresses =3D <0x82001000 0 0x80001000 0 0x1000>; - reg =3D <0x001000 0 0 0 0>; - status =3D "disabled"; - - #address-cells =3D <3>; - #size-cells =3D <2>; - - ranges; - - nvidia,num-lanes =3D <2>; - }; - }; - -Board DTS: - - pcie-controller@80003000 { - status =3D "okay"; - - vdd-supply =3D <&pci_vdd_reg>; - pex-clk-supply =3D <&pci_clk_reg>; - - /* root port 00:01.0 */ - pci@1,0 { - status =3D "okay"; - - /* bridge 01:00.0 (optional) */ - pci@0,0 { - reg =3D <0x010000 0 0 0 0>; - - #address-cells =3D <3>; - #size-cells =3D <2>; - - device_type =3D "pci"; - - /* endpoint 02:00.0 */ - pci@0,0 { - reg =3D <0x020000 0 0 0 0>; - }; - }; - }; - }; - -Note that devices on the PCI bus are dynamically discovered using PCI's bus -enumeration and therefore don't need corresponding device nodes in DT. How= ever -if a device on the PCI bus provides a non-probeable bus such as I2C or SPI, -device nodes need to be added in order to allow the bus' children to be -instantiated at the proper location in the operating system's device tree = (as -illustrated by the optional nodes in the example above). - -Tegra30: --------- - -SoC DTSI: - - pcie-controller@3000 { - compatible =3D "nvidia,tegra30-pcie"; - device_type =3D "pci"; - reg =3D <0x00003000 0x00000800 /* PADS registers */ - 0x00003800 0x00000200 /* AFI registers */ - 0x10000000 0x10000000>; /* configuration space */ - reg-names =3D "pads", "afi", "cs"; - interrupts =3D ; /* MSI interrupt */ - interrupt-names =3D "intr", "msi"; - - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - - bus-range =3D <0x00 0xff>; - #address-cells =3D <3>; - #size-cells =3D <2>; - - ranges =3D <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 = configuration space */ - 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configura= tion space */ - 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configura= tion space */ - 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable= memory */ - 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable mem= ory */ - - clocks =3D <&tegra_car TEGRA30_CLK_PCIE>, - <&tegra_car TEGRA30_CLK_AFI>, - <&tegra_car TEGRA30_CLK_PLL_E>, - <&tegra_car TEGRA30_CLK_CML0>; - clock-names =3D "pex", "afi", "pll_e", "cml"; - resets =3D <&tegra_car 70>, - <&tegra_car 72>, - <&tegra_car 74>; - reset-names =3D "pex", "afi", "pcie_x"; - status =3D "disabled"; - - pci@1,0 { - device_type =3D "pci"; - assigned-addresses =3D <0x82000800 0 0x00000000 0 0x1000>; - reg =3D <0x000800 0 0 0 0>; - status =3D "disabled"; - - #address-cells =3D <3>; - #size-cells =3D <2>; - ranges; - - nvidia,num-lanes =3D <2>; - }; - - pci@2,0 { - device_type =3D "pci"; - assigned-addresses =3D <0x82001000 0 0x00001000 0 0x1000>; - reg =3D <0x001000 0 0 0 0>; - status =3D "disabled"; - - #address-cells =3D <3>; - #size-cells =3D <2>; - ranges; - - nvidia,num-lanes =3D <2>; - }; - - pci@3,0 { - device_type =3D "pci"; - assigned-addresses =3D <0x82001800 0 0x00004000 0 0x1000>; - reg =3D <0x001800 0 0 0 0>; - status =3D "disabled"; - - #address-cells =3D <3>; - #size-cells =3D <2>; - ranges; - - nvidia,num-lanes =3D <2>; - }; - }; - -Board DTS: - - pcie-controller@3000 { - status =3D "okay"; - - avdd-pexa-supply =3D <&ldo1_reg>; - vdd-pexa-supply =3D <&ldo1_reg>; - avdd-pexb-supply =3D <&ldo1_reg>; - vdd-pexb-supply =3D <&ldo1_reg>; - avdd-pex-pll-supply =3D <&ldo1_reg>; - avdd-plle-supply =3D <&ldo1_reg>; - vddio-pex-ctl-supply =3D <&sys_3v3_reg>; - hvdd-pex-supply =3D <&sys_3v3_pexs_reg>; - - pci@1,0 { - status =3D "okay"; - }; - - pci@3,0 { - status =3D "okay"; - }; - }; - -Tegra124: ---------- - -SoC DTSI: - - pcie-controller@1003000 { - compatible =3D "nvidia,tegra124-pcie"; - device_type =3D "pci"; - reg =3D <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ - 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ - 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ - reg-names =3D "pads", "afi", "cs"; - interrupts =3D , /* controller interrupt= */ - ; /* MSI interrupt */ - interrupt-names =3D "intr", "msi"; - - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - - bus-range =3D <0x00 0xff>; - #address-cells =3D <3>; - #size-cells =3D <2>; - - ranges =3D <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* por= t 0 configuration space */ - 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 confi= guration space */ - 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I= /O (64 KiB) */ - 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetch= able memory (208 MiB) */ - 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable= memory (512 MiB) */ - - clocks =3D <&tegra_car TEGRA124_CLK_PCIE>, - <&tegra_car TEGRA124_CLK_AFI>, - <&tegra_car TEGRA124_CLK_PLL_E>, - <&tegra_car TEGRA124_CLK_CML0>; - clock-names =3D "pex", "afi", "pll_e", "cml"; - resets =3D <&tegra_car 70>, - <&tegra_car 72>, - <&tegra_car 74>; - reset-names =3D "pex", "afi", "pcie_x"; - status =3D "disabled"; - - pci@1,0 { - device_type =3D "pci"; - assigned-addresses =3D <0x82000800 0 0x01000000 0 0x1000>; - reg =3D <0x000800 0 0 0 0>; - status =3D "disabled"; - - #address-cells =3D <3>; - #size-cells =3D <2>; - ranges; - - nvidia,num-lanes =3D <2>; - }; - - pci@2,0 { - device_type =3D "pci"; - assigned-addresses =3D <0x82001000 0 0x01001000 0 0x1000>; - reg =3D <0x001000 0 0 0 0>; - status =3D "disabled"; - - #address-cells =3D <3>; - #size-cells =3D <2>; - ranges; - - nvidia,num-lanes =3D <1>; - }; - }; - -Board DTS: - - pcie-controller@1003000 { - status =3D "okay"; - - avddio-pex-supply =3D <&vdd_1v05_run>; - dvddio-pex-supply =3D <&vdd_1v05_run>; - avdd-pex-pll-supply =3D <&vdd_1v05_run>; - hvdd-pex-supply =3D <&vdd_3v3_lp0>; - hvdd-pex-pll-e-supply =3D <&vdd_3v3_lp0>; - vddio-pex-ctl-supply =3D <&vdd_3v3_lp0>; - avdd-pll-erefe-supply =3D <&avdd_1v05_run>; - - /* Mini PCIe */ - pci@1,0 { - phys =3D <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; - phy-names =3D "pcie-0"; - status =3D "okay"; - }; - - /* Gigabit Ethernet */ - pci@2,0 { - phys =3D <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; - phy-names =3D "pcie-0"; - status =3D "okay"; - }; - }; - -Tegra210: ---------- - -SoC DTSI: - - pcie-controller@1003000 { - compatible =3D "nvidia,tegra210-pcie"; - device_type =3D "pci"; - reg =3D <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ - 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ - 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ - reg-names =3D "pads", "afi", "cs"; - interrupts =3D , /* controller interrupt= */ - ; /* MSI interrupt */ - interrupt-names =3D "intr", "msi"; - - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - - bus-range =3D <0x00 0xff>; - #address-cells =3D <3>; - #size-cells =3D <2>; - - ranges =3D <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* por= t 0 configuration space */ - 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 confi= guration space */ - 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I= /O (64 KiB) */ - 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetch= able memory (208 MiB) */ - 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable= memory (512 MiB) */ - - clocks =3D <&tegra_car TEGRA210_CLK_PCIE>, - <&tegra_car TEGRA210_CLK_AFI>, - <&tegra_car TEGRA210_CLK_PLL_E>, - <&tegra_car TEGRA210_CLK_CML0>; - clock-names =3D "pex", "afi", "pll_e", "cml"; - resets =3D <&tegra_car 70>, - <&tegra_car 72>, - <&tegra_car 74>; - reset-names =3D "pex", "afi", "pcie_x"; - status =3D "disabled"; - - pci@1,0 { - device_type =3D "pci"; - assigned-addresses =3D <0x82000800 0 0x01000000 0 0x1000>; - reg =3D <0x000800 0 0 0 0>; - status =3D "disabled"; - - #address-cells =3D <3>; - #size-cells =3D <2>; - ranges; - - nvidia,num-lanes =3D <4>; - }; - - pci@2,0 { - device_type =3D "pci"; - assigned-addresses =3D <0x82001000 0 0x01001000 0 0x1000>; - reg =3D <0x001000 0 0 0 0>; - status =3D "disabled"; - - #address-cells =3D <3>; - #size-cells =3D <2>; - ranges; - - nvidia,num-lanes =3D <1>; - }; - }; - -Board DTS: - - pcie-controller@1003000 { - status =3D "okay"; - - avdd-pll-uerefe-supply =3D <&avdd_1v05_pll>; - hvddio-pex-supply =3D <&vdd_1v8>; - dvddio-pex-supply =3D <&vdd_pex_1v05>; - dvdd-pex-pll-supply =3D <&vdd_pex_1v05>; - hvdd-pex-pll-e-supply =3D <&vdd_1v8>; - vddio-pex-ctl-supply =3D <&vdd_1v8>; - - pci@1,0 { - phys =3D <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>; - phy-names =3D "pcie-0", "pcie-1", "pcie-2", "pcie-3"; - status =3D "okay"; - }; - - pci@2,0 { - phys =3D <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; - phy-names =3D "pcie-0"; - status =3D "okay"; - }; - }; - -Tegra186: ---------- - -SoC DTSI: - - pcie@10003000 { - compatible =3D "nvidia,tegra186-pcie"; - power-domains =3D <&bpmp TEGRA186_POWER_DOMAIN_PCX>; - device_type =3D "pci"; - reg =3D <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ - 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ - 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ - reg-names =3D "pads", "afi", "cs"; - - interrupts =3D , /* controller interrupt= */ - ; /* MSI interrupt */ - interrupt-names =3D "intr", "msi"; - - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - - bus-range =3D <0x00 0xff>; - #address-cells =3D <3>; - #size-cells =3D <2>; - - ranges =3D <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* por= t 0 configuration space */ - 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 confi= guration space */ - 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 confi= guration space */ - 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I= /O (64 KiB) */ - 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetch= able memory (127 MiB) */ - 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable= memory (640 MiB) */ - - clocks =3D <&bpmp TEGRA186_CLK_AFI>, - <&bpmp TEGRA186_CLK_PCIE>, - <&bpmp TEGRA186_CLK_PLLE>; - clock-names =3D "afi", "pex", "pll_e"; - - resets =3D <&bpmp TEGRA186_RESET_AFI>, - <&bpmp TEGRA186_RESET_PCIE>, - <&bpmp TEGRA186_RESET_PCIEXCLK>; - reset-names =3D "afi", "pex", "pcie_x"; - - status =3D "disabled"; - - pci@1,0 { - device_type =3D "pci"; - assigned-addresses =3D <0x82000800 0 0x10000000 0 0x1000>; - reg =3D <0x000800 0 0 0 0>; - status =3D "disabled"; - - #address-cells =3D <3>; - #size-cells =3D <2>; - ranges; - - nvidia,num-lanes =3D <2>; - }; - - pci@2,0 { - device_type =3D "pci"; - assigned-addresses =3D <0x82001000 0 0x10001000 0 0x1000>; - reg =3D <0x001000 0 0 0 0>; - status =3D "disabled"; - - #address-cells =3D <3>; - #size-cells =3D <2>; - ranges; - - nvidia,num-lanes =3D <1>; - }; - - pci@3,0 { - device_type =3D "pci"; - assigned-addresses =3D <0x82001800 0 0x10004000 0 0x1000>; - reg =3D <0x001800 0 0 0 0>; - status =3D "disabled"; - - #address-cells =3D <3>; - #size-cells =3D <2>; - ranges; - - nvidia,num-lanes =3D <1>; - }; - }; - -Board DTS: - - pcie@10003000 { - status =3D "okay"; - - dvdd-pex-supply =3D <&vdd_pex>; - hvdd-pex-pll-supply =3D <&vdd_1v8>; - hvdd-pex-supply =3D <&vdd_1v8>; - vddio-pexctl-aud-supply =3D <&vdd_1v8>; - - pci@1,0 { - nvidia,num-lanes =3D <4>; - status =3D "okay"; - }; - - pci@2,0 { - nvidia,num-lanes =3D <0>; - status =3D "disabled"; - }; - - pci@3,0 { - nvidia,num-lanes =3D <1>; - status =3D "disabled"; - }; - }; diff --git a/MAINTAINERS b/MAINTAINERS index 55af015174a5..45584cc85401 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20252,7 +20252,7 @@ M: Thierry Reding L: linux-tegra@vger.kernel.org L: linux-pci@vger.kernel.org S: Supported -F: Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt +F: Documentation/devicetree/bindings/pci/nvidia,tegra-pcie.yaml F: drivers/pci/controller/pci-tegra.c =20 PCI DRIVER FOR NXP LAYERSCAPE GEN4 CONTROLLER --=20 2.50.1 From nobody Thu Apr 2 20:28:05 2026 Received: from mail-pf1-f170.google.com (mail-pf1-f170.google.com [209.85.210.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19D7438B7D8 for ; Tue, 24 Feb 2026 12:20:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771935626; cv=none; b=jZ5hhc8ybDbRBtZax1HY/Zh79+qkxzFdqRJyT6qVz3zs57rjPQw4nGScypLz8cNEDKaHfooCqXyi9q6lRSYhKGGwm1CveNwf0nKemMwxxdSRmYCzD1YgUYwsDKTHHf+y9J0HWraVN1RgxApqhIlL5Jh2l0B1sze+MzVZcL0jyLU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771935626; c=relaxed/simple; bh=Vlv7hjadzolvGAJw7ypQeoRDm1X9EIwDs9/wBQrRNZI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CZjxgR6wMMhbpGJEeq2nweoFHPxFuKT+VVD+seVT30d4TwhlsOFMhBKMh6K6RTnt0BFhYV3eMExc4Avm4NL4/aPeeuaLmCHNr7iKjnPtN85HtYbHOpGKrFiMqVK5VXDXlXd+1zGO8xxHbOBcpaBJZG5A9byYUJ5GJTZPQqh76lg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=crWRUl71; arc=none smtp.client-ip=209.85.210.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="crWRUl71" Received: by mail-pf1-f170.google.com with SMTP id d2e1a72fcca58-823075fed75so2464166b3a.1 for ; Tue, 24 Feb 2026 04:20:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1771935624; x=1772540424; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GDJ0Gfg7oWDz1xGI8ZNNKjjsgjUS855MyxuHLu+cOXw=; b=crWRUl71awcjTgB76VKouvnpvuiOZUl1y2antwG0t6P7OmqbLxZodUNKpnIVRdhE0H EXohvyKwNI6ORwx9T3EdFFglU73it1amVLEUTVVR1+vmHWBCOtYdjTSoQgxN5YhaVe6g LC5U22NTl0bteIkmzdvJIqMYsZ/dders4lUOyj5Ukq+/6nnexOtXfx12fGeoRnhp356x 1eiSzpDLIv8glt2+WpTC3FNpG7+njrKjs6ac08iR/2yg/+vBs5WxV8/CIqhO3Xkz8GsC llelz+oG1oSHrdDaGsLB/Y86uzj6r8LFv3td/cee2qKpqFi3girZsn8CTDNMjGgOxRmm 8zQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771935624; x=1772540424; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=GDJ0Gfg7oWDz1xGI8ZNNKjjsgjUS855MyxuHLu+cOXw=; b=Gwj6Mmoui2YfQjcVvL+ATjjuJ0bOTNf0Rsa06FU/zhVF0SCEGS0aA7G54FrS04laeL H7wXaHietAT9ecEl3UZcZf1a6FeUOpInn2cic/eoeGJ/jLIgiE/Tb90f3VWRR0Y2MNk0 JAZxlkJ3tMSh4/SyTNV4TyGUgK9F2mwugfccTK2z3WdM7x6TEeedsgSdETfEwyvJ8apf y3Mfm8cwr1o5xYyEcGGL04TLj/cbOSBhxhIj9Eb/NyZoRsgj1QYV4XealqD24h6oqPPe lkqVToJI0yVF2t18c+fRfdtX0d1a+BbygK6YH5P74ej+vRdtYUYy4H6EhhVmQHzj6YRh BfXw== X-Forwarded-Encrypted: i=1; AJvYcCXSQfkoqX4+CQtV56VLcQrvXjOH0JDlR2r8ed1boqF2/pE8xzODPe3OOSZXNBtGL4AMd9UCa0De5WraRv4=@vger.kernel.org X-Gm-Message-State: AOJu0YxpA9oiQCKPxhkmLYmnlXQMz4lODyEZ77VMTlz2w9upgkonuFb0 /0ShAHufU4CA1B8voPwXZBB85ZR2MixCvODGif0a9qbw1fFdWD/NAOjk X-Gm-Gg: ATEYQzwUuB4+IGuCvp3NnMnBotTAunQzDrdHVU9N3+p5RqmakgN76ltI/ZyxhVoBXuZ SF+LsLyW4ZX9nKOnif6QvYa7CuyPFOsm1mlFfiwu7op2fsg7Iv2y0BD6lpNS7EkgXQiPlQH5J9Z Z+IL8rSaxaXZlh6ZyVfUcljmyvMNghKUrRaxcixi96/dgiax9UnbvAPz6ei1DAsQfNTTRMcmDW/ i03kYwExJWARxT38LLjQBjwqj4oAyRnszCJ2AwMjSZSkHL1v4NoJjg7XrzsVIg9ngZy8no/mCCa cuzk2oHNJZROo/5c4t4fE071zJwlK3JbVph1nCxMJZkEkKGLBRKVwo6dOo8Yk+JXoo3U+A3bFPP eVOYnGzoln2DDqYQnX2/Vzvix9rSc+c/QeA7bHXy7fOsLtdLwUQd3zxJtmybMkWOJwXDPbcIvnC sFLa9wEJhRnB/dmK7j7ky03UOTW2WQLg== X-Received: by 2002:a05:6a00:198a:b0:81f:4708:b46e with SMTP id d2e1a72fcca58-826db8c010bmr9648841b3a.20.1771935624430; Tue, 24 Feb 2026 04:20:24 -0800 (PST) Received: from rockpi-5b ([45.112.0.78]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-826dd8ba11bsm10613950b3a.50.2026.02.24.04.20.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Feb 2026 04:20:23 -0800 (PST) From: Anand Moon To: Thierry Reding , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Hunter , Aaron Kling , linux-tegra@vger.kernel.org (open list:PCI DRIVER FOR NVIDIA TEGRA), linux-pci@vger.kernel.org (open list:PCI DRIVER FOR NVIDIA TEGRA), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [PATCH v3 2/5] arm64: dts: tegra: tegra186-p2771: Fix invalid PCIe nvidia,num-lanes Date: Tue, 24 Feb 2026 17:48:58 +0530 Message-ID: <20260224121948.25218-3-linux.amoon@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260224121948.25218-1-linux.amoon@gmail.com> References: <20260224121948.25218-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" NVIDIA Tegra PCIe binding schema (nvidia,tegra-pcie.yaml) defines nvidia,num-lanes with an enum of [1, 2, 4]. The value <0> for the pci@2,0 node is invalid and causes a dtbs_check validation failure. Update the lane count to <1> to comply with the binding constraints. Signed-off-by: Anand Moon --- v3: new patch http://devicetree.org/schemas/pci/nvidia,tegra-pcie.yaml /media/nvme0/mainline/linux-tegra-6.y-devel/arch/arm64/boot/dts/nvidia/tegr= a186-p2771-0000.dtb: pcie@10003000 (nvidia,tegra186-pcie): pci@2,0:nvidia,n= um-lanes: 0 is not one of [1, 2, 4] from schema $id: http://devicetree.org/schemas/pci/nvidia,tegra-pci= e.yaml DTC [C] arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dtb --- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm6= 4/boot/dts/nvidia/tegra186-p2771-0000.dts index 8b3736cee323..b4c6bfb09ce2 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -2433,7 +2433,7 @@ pci@1,0 { }; =20 pci@2,0 { - nvidia,num-lanes =3D <0>; + nvidia,num-lanes =3D <1>; status =3D "disabled"; }; =20 --=20 2.50.1 From nobody Thu Apr 2 20:28:05 2026 Received: from mail-pf1-f172.google.com (mail-pf1-f172.google.com [209.85.210.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4ECC3815D2 for ; Tue, 24 Feb 2026 12:20:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771935639; cv=none; b=bHD24BT4Q/tcJX1r4pM0A5m02YXjuZJirXVY3Fk33JPZezLWSL+WE0WjFWbalZlEYntV6b2u05WWU7flmDJ8AEi8fXg7/+JxthW3Rtvnz3F5Yo+XI9/rAGjjNgDHjWYQ7kLjKi8bHqJoQnoCdCNcBfXpIBZqlud2Q8w6JRVk6l4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771935639; c=relaxed/simple; bh=jdzWYyYQqakXllbhH/zeMWJPPh6SiIY6qluU0wDrWYM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HaWkdxzqkDcMuLJkJHzuiUVgcodao9PHMQS0LrOUnCXIbZOi/dJm0QmrCKT9zpaAkfpOGwEVpdSWCbidDc4IRbwVHyNIfVyzTTEQS0hourZ21gkH6WPs2lzCBBwZLNipiXnJfJZoUWm5yCOYun1/63Nnik5qmr/qSisLIOdOdaA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=h8GWtOFF; arc=none smtp.client-ip=209.85.210.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="h8GWtOFF" Received: by mail-pf1-f172.google.com with SMTP id d2e1a72fcca58-824adc96ad2so5462512b3a.3 for ; Tue, 24 Feb 2026 04:20:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1771935637; x=1772540437; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qNK6vbvi37qs9tkDMjIRAkoSxo6WGQaG2DgYfv4s/Ig=; b=h8GWtOFFo/bfHSI7tEeK29OSTV6fztgiqwg50/ZisrJzJy5nLZxHgb3WADKxkjbKJ5 uGE9Kg4ngyDYjJdDI7doAmmasR+PD+i2KhUiombf8PaPoZlPlJ8ww2IkOa0SLcJuArpa xZTUn27nS/qmE+rATbJ19bKKNPsx7rC9I6vw+A2/YjEsskBw3ZEylLSVni2LIYpJFHzJ rsozP5Jnd94Cw4TZ+3tMOQbGekJgcDCwuir/BCZVaDhZwf67t0fxjJlMFoc4XMoQ41KR tjs+YwuoVv6ms+lTnkq29lYhGa2JAbDRZdAyRwISoVKAUdmmSk0GHtAaSHILQj/B1fxD YsxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771935637; x=1772540437; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=qNK6vbvi37qs9tkDMjIRAkoSxo6WGQaG2DgYfv4s/Ig=; b=qO+ylI9D7i9sGDk55BGm0i7Ed0LJR7lm4vFjQ9CywUeMrqelum/qajC2x8NeSQdEbe Gqz6XU5Xp8aRT6p1u8TrFewtOOgzY6k1vNT+fVkHYGQKnBzfDN6gZ8vZdqH0bCKwSSP+ pjVCoBC7KG/vL8bod2KmLuYcOVOqGbof3WSwBDtZJpjXSQ3aVyT3al2dS8nCFjdteJqm 0PbvCy15L0uvx6y5Yr4sbbntu8nPRlWaZLo8E2Pu8CDLdMmYrwWWVfczocNxzzGhKWkE 9O0SE/n2ijs7aPkKmm+1gIoemCBMLYc8BH8HDsIKsQmWm5zVByCEZMEvIFIirbsgYSUl 1psQ== X-Forwarded-Encrypted: i=1; AJvYcCX5whBShYFIUi8xkUlyaZLkKFAlqHIcdSbNwhhJ9lDno5VdRmqiICB7flGf96VgzX7yYyUNBx7tRQUcWrM=@vger.kernel.org X-Gm-Message-State: AOJu0YzrXQV3BfWEJZhxrURnpIdAybXbF3aYgPJGeWa5gcmX6nnY1ESu uO01H0DoAc6qBoUhXB07BvXJ1qgrm//et6oBCydVzN1IuFJ/oGt5gR1v X-Gm-Gg: ATEYQzwRwDGan/MpxQPH8DDsJoYLDEj1z3iKn7rnYeMHFOJNbZT9bg9jdLX8p9ggEyo lyNlAVmg6sAt/t/X1AHphRI25vzAJKcYXEdLmeVIbjk2G9VGSafWH2dG2rxv5/K6GtaaSLafZoR KYX1515/0vw3bVaeiwYJ9S2dVxGf4mPEP++IPSPbDarg+Pg7V6Ti99DxhHTSnhJrpB2+yYHmzKG dN+eGYjvraqa8cnlMXu62tzsHiwSO389TjYSzXiyMJqXjqnBXYQ0YwQblZYXpjkN92lpwt3N+EB 3zV0YlMOaVLCi0tfkTsSv3iXhelONBYzJSPhuNNTVb1QPtAaKzAqxksVxSxnyP2b1okbdnHe63C BArjDEw5Falvsraw/8qpYj3CPg3CuXDae1349xri9fHTL6YHx6oEbom121D5qzHYH0tAPQAi5Yl YrvYaUQg4zf943yPRpZaOL/nQmEB+/1w== X-Received: by 2002:aa7:88c1:0:b0:824:9a12:deb1 with SMTP id d2e1a72fcca58-826daa81cb6mr12030602b3a.62.1771935637215; Tue, 24 Feb 2026 04:20:37 -0800 (PST) Received: from rockpi-5b ([45.112.0.78]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-826dd8ba11bsm10613950b3a.50.2026.02.24.04.20.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Feb 2026 04:20:36 -0800 (PST) From: Anand Moon To: Thierry Reding , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Hunter , Aaron Kling , linux-tegra@vger.kernel.org (open list:PCI DRIVER FOR NVIDIA TEGRA), linux-pci@vger.kernel.org (open list:PCI DRIVER FOR NVIDIA TEGRA), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [PATCH v3 3/5] PCI: tegra: Simplify clock handling by using clk_bulk*() functions Date: Tue, 24 Feb 2026 17:48:59 +0530 Message-ID: <20260224121948.25218-4-linux.amoon@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260224121948.25218-1-linux.amoon@gmail.com> References: <20260224121948.25218-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, the driver acquires clocks and prepare/enable/disable/unprepare the clocks individually thereby making the driver complex to read. The driver can be simplified by using the clk_bulk*() APIs. Use: - devm_clk_bulk_get_all() API to acquire all the clocks - clk_bulk_prepare_enable() to prepare/enable clocks - clk_bulk_disable_unprepare() APIs to disable/unprepare them in bulk As part of this cleanup: - Remove the legacy has_cml_clk flag - Drop explicit handling of individual clocks (pex, afi, pll_e, cml) - Rely on device tree ordering for clock sequencing, eliminating hardcoded logic and improving readability and maintainability This improves clarity, and makes future changes easier for maintainers. Cc: Thierry Reding Signed-off-by: Anand Moon --- v3: None v2: Switch back to devm_clk_bulk_get_all from devm_clk_bulk_get() Mani - But you are converting it to .yaml, so you can safely use devm_clk_bulk_get_all() v1: Switch from devm_clk_bulk_get_all() -> devm_clk_bulk_get() with fix clks array. nvidia,tegra20-pcie and nvidia,tegra186-pcie uses three clocks pex, afi, pll_e where as nvidia,tegra30-pcie, nvidia,tegra124-pcie, nvidia,tegra210-pcie uses four clks pex, afi, pll_e, cml --- drivers/pci/controller/pci-tegra.c | 71 +++++------------------------- 1 file changed, 12 insertions(+), 59 deletions(-) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pc= i-tegra.c index 512309763d1f..32dc11d95cc9 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -298,7 +298,6 @@ struct tegra_pcie_soc { bool has_pex_clkreq_en; bool has_pex_bias_ctrl; bool has_intr_prsnt_sense; - bool has_cml_clk; bool has_gen2; bool force_pca_enable; bool program_uphy; @@ -331,10 +330,8 @@ struct tegra_pcie { =20 struct resource cs; =20 - struct clk *pex_clk; - struct clk *afi_clk; - struct clk *pll_e; - struct clk *cml_clk; + struct clk_bulk_data *clks; + int num_clks; =20 struct reset_control *pex_rst; struct reset_control *afi_rst; @@ -1154,15 +1151,11 @@ static void tegra_pcie_enable_controller(struct teg= ra_pcie *pcie) static void tegra_pcie_power_off(struct tegra_pcie *pcie) { struct device *dev =3D pcie->dev; - const struct tegra_pcie_soc *soc =3D pcie->soc; int err; =20 reset_control_assert(pcie->afi_rst); =20 - clk_disable_unprepare(pcie->pll_e); - if (soc->has_cml_clk) - clk_disable_unprepare(pcie->cml_clk); - clk_disable_unprepare(pcie->afi_clk); + clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); =20 if (!dev->pm_domain) tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); @@ -1175,7 +1168,6 @@ static void tegra_pcie_power_off(struct tegra_pcie *p= cie) static int tegra_pcie_power_on(struct tegra_pcie *pcie) { struct device *dev =3D pcie->dev; - const struct tegra_pcie_soc *soc =3D pcie->soc; int err; =20 reset_control_assert(pcie->pcie_xrst); @@ -1203,35 +1195,16 @@ static int tegra_pcie_power_on(struct tegra_pcie *p= cie) } } =20 - err =3D clk_prepare_enable(pcie->afi_clk); + err =3D clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); if (err < 0) { - dev_err(dev, "failed to enable AFI clock: %d\n", err); + dev_err(dev, "filed to enable clocks: %d\n", err); goto powergate; } =20 - if (soc->has_cml_clk) { - err =3D clk_prepare_enable(pcie->cml_clk); - if (err < 0) { - dev_err(dev, "failed to enable CML clock: %d\n", err); - goto disable_afi_clk; - } - } - - err =3D clk_prepare_enable(pcie->pll_e); - if (err < 0) { - dev_err(dev, "failed to enable PLLE clock: %d\n", err); - goto disable_cml_clk; - } - reset_control_deassert(pcie->afi_rst); =20 return 0; =20 -disable_cml_clk: - if (soc->has_cml_clk) - clk_disable_unprepare(pcie->cml_clk); -disable_afi_clk: - clk_disable_unprepare(pcie->afi_clk); powergate: if (!dev->pm_domain) tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); @@ -1255,25 +1228,11 @@ static void tegra_pcie_apply_pad_settings(struct te= gra_pcie *pcie) static int tegra_pcie_clocks_get(struct tegra_pcie *pcie) { struct device *dev =3D pcie->dev; - const struct tegra_pcie_soc *soc =3D pcie->soc; - - pcie->pex_clk =3D devm_clk_get(dev, "pex"); - if (IS_ERR(pcie->pex_clk)) - return PTR_ERR(pcie->pex_clk); =20 - pcie->afi_clk =3D devm_clk_get(dev, "afi"); - if (IS_ERR(pcie->afi_clk)) - return PTR_ERR(pcie->afi_clk); - - pcie->pll_e =3D devm_clk_get(dev, "pll_e"); - if (IS_ERR(pcie->pll_e)) - return PTR_ERR(pcie->pll_e); - - if (soc->has_cml_clk) { - pcie->cml_clk =3D devm_clk_get(dev, "cml"); - if (IS_ERR(pcie->cml_clk)) - return PTR_ERR(pcie->cml_clk); - } + pcie->num_clks =3D devm_clk_bulk_get_all(dev, &pcie->clks); + if (pcie->num_clks < 0) + return dev_err_probe(dev, pcie->num_clks, + "failed to get clocks\n"); =20 return 0; } @@ -2344,7 +2303,6 @@ static const struct tegra_pcie_soc tegra20_pcie =3D { .has_pex_clkreq_en =3D false, .has_pex_bias_ctrl =3D false, .has_intr_prsnt_sense =3D false, - .has_cml_clk =3D false, .has_gen2 =3D false, .force_pca_enable =3D false, .program_uphy =3D true, @@ -2373,7 +2331,6 @@ static const struct tegra_pcie_soc tegra30_pcie =3D { .has_pex_clkreq_en =3D true, .has_pex_bias_ctrl =3D true, .has_intr_prsnt_sense =3D true, - .has_cml_clk =3D true, .has_gen2 =3D false, .force_pca_enable =3D false, .program_uphy =3D true, @@ -2394,7 +2351,6 @@ static const struct tegra_pcie_soc tegra124_pcie =3D { .has_pex_clkreq_en =3D true, .has_pex_bias_ctrl =3D true, .has_intr_prsnt_sense =3D true, - .has_cml_clk =3D true, .has_gen2 =3D true, .force_pca_enable =3D false, .program_uphy =3D true, @@ -2417,7 +2373,6 @@ static const struct tegra_pcie_soc tegra210_pcie =3D { .has_pex_clkreq_en =3D true, .has_pex_bias_ctrl =3D true, .has_intr_prsnt_sense =3D true, - .has_cml_clk =3D true, .has_gen2 =3D true, .force_pca_enable =3D true, .program_uphy =3D true, @@ -2458,7 +2413,6 @@ static const struct tegra_pcie_soc tegra186_pcie =3D { .has_pex_clkreq_en =3D true, .has_pex_bias_ctrl =3D true, .has_intr_prsnt_sense =3D true, - .has_cml_clk =3D false, .has_gen2 =3D true, .force_pca_enable =3D false, .program_uphy =3D false, @@ -2642,7 +2596,7 @@ static int tegra_pcie_pm_suspend(struct device *dev) } =20 reset_control_assert(pcie->pex_rst); - clk_disable_unprepare(pcie->pex_clk); + clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); =20 if (IS_ENABLED(CONFIG_PCI_MSI)) tegra_pcie_disable_msi(pcie); @@ -2676,9 +2630,9 @@ static int tegra_pcie_pm_resume(struct device *dev) if (IS_ENABLED(CONFIG_PCI_MSI)) tegra_pcie_enable_msi(pcie); =20 - err =3D clk_prepare_enable(pcie->pex_clk); + err =3D clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); if (err) { - dev_err(dev, "failed to enable PEX clock: %d\n", err); + dev_err(dev, "failed to enable clock: %d\n", err); goto pex_dpd_enable; } =20 @@ -2699,7 +2653,6 @@ static int tegra_pcie_pm_resume(struct device *dev) =20 disable_pex_clk: reset_control_assert(pcie->pex_rst); - clk_disable_unprepare(pcie->pex_clk); pex_dpd_enable: pinctrl_pm_select_idle_state(dev); poweroff: --=20 2.50.1 From nobody Thu Apr 2 20:28:05 2026 Received: from mail-pf1-f174.google.com (mail-pf1-f174.google.com [209.85.210.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0205396D18 for ; Tue, 24 Feb 2026 12:20:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771935650; cv=none; b=SjrU0U4/LGxW80VwhuQnjGeescUb0joP7cdKqxHIevWjHignvzFUycx+ywEBCmqG5vEwu89q6fRdjKboAE1aLiUMaXg7Ikj5Iji+OWdmNs4fzgr2X5CsdOot4uUyy9xKM2rPSTQT81gfqX0FVfkBVAXNJtKP5sjvIPtbGhfGJlc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771935650; c=relaxed/simple; bh=XLbatLTUJXw9A3hBonWnh0l0ZSHoVwD+j7EQZ/FCueU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SPA5WzL7pzMmbvGw0ESX/eIm/qHZ7qYfLa0TG0ehC876NZ4F+QB6xdN389YP3XTCIEbSxly6RZuUTxcBKVePpFDfCpostKNbcQSv0y4NvzR5LowjYyXsx4sKIIPsy5K0vMsUTjgPLz/FmrsYca/l3aHQAWoWF+fNC1aEComQJvM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=LbYgykEp; arc=none smtp.client-ip=209.85.210.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="LbYgykEp" Received: by mail-pf1-f174.google.com with SMTP id d2e1a72fcca58-824a3ba5222so2926143b3a.2 for ; Tue, 24 Feb 2026 04:20:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1771935649; x=1772540449; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QKJ9zh45ZdopaEOQEByGr+CA6Hn9q+QZHG4I18FgvD8=; b=LbYgykEpPFsd+Hn5rQ3PQWzwmKjZzFfEKdVfup3XaJeUQK4/CLnsfRLSYjR6U9Fg9d Jtt84NNJXWzGxK5eymcMonZtRpVPuxTey/Q89YIU70we/nxFV0t1fb9aXMVete0XwnyP xEubDm/68ithFXMF8QHUChZOsOfku18/tWrXraWTZmnxWGrDJPj5IVN0ibGxpQo4M8O3 WMJG4e4DmpF4QWym7ihUYztFL8uUPlCz6pxC4X3tAG0wItKuOwFWpkzeH56TeNkffugq 3xDsD8V0v4AQHQ28N95Bvovp8Py5c+eZvIsG7sR7DIz5ffUoq3p3l/Oc53tfAuM6Bden lcWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771935649; x=1772540449; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=QKJ9zh45ZdopaEOQEByGr+CA6Hn9q+QZHG4I18FgvD8=; b=gTWoo5Zi6prZ20rLk95UUAh+kGaMtSwAjBSomx2ZyPaRiHFQ5JXuH6iklDFf+63pgm QX4gNbh//zXtvMdZTrEOpxVjDPBRyOVBifqxnjW6aeH+RM01V6dhDEOXQhBw1iwqL1iW oWjWI6vu7ovMXjRBZdMFA+eXmPVlNj7HF+xeflb7Tqd9Bb72Te0EoZUlzbfPLFNs+xEB YYX95RHWOJn9f+AZb8vTSXJW6dF69iPttlex9bi7gxBOscMTJ/iO0TdTh6Jf2m5RzE2U +KhuLcc/airiHfNwmiIwkMggqkBpjYEG8VDAX04Sd31r79cm9nizUHaXDIO7UN1gVbRc 7Pfg== X-Forwarded-Encrypted: i=1; AJvYcCVX3rStEBVPFzM9UNwah/l1SbPbqtPK9qiEnW5o85b+uP6+h9aOcUPbyj000qI68wo34mPmuiFNx0DcXm8=@vger.kernel.org X-Gm-Message-State: AOJu0YwcNTSzfA0F1cOzGh2IEAciibLitfGcvj7YtBCeWn5vzOoGosTK SwrMjteR6oSXzKZBFj+PaRFcuvNl0BQEMJ1LWZmnax32XVNovlU7zM+y X-Gm-Gg: ATEYQzzy7tRV4sv1grsRfGjqmC4N2KFsKJbsdxFt9zLObQe+Eh7orwc8PwLo26YM974 5j3v7/X7ug1cG99ORx/ZiOKRscAF1tOsONZkrl5206uIhvJjOyr5Lw4HuH80RN/1hWNXQsSVe2P ZKYrM0dZ2yOoMbJBAlM05XfRXrYRVjIi9wnhzbN28oaC5X6A5fymi8YigYDZIjUSutqWBf2Zmpx gZGujl/E6APmTt/hlgGXHJ6/bJuYu5HPTwjzcZUSsA4BmvREaVPr+lmrR39z1cNFUcONgzrIL/9 8k3Ts/8B5VRL05dBC1/layCwGf/CR3R6aei+TMCbqfkL7eYPtr23v1wUBfA/I29NDAIHEKjvv5t hVicaDnugYkU90mAk7H0o621vPkIt4Oh3F4KqK0cXdNQk989yReyyqSzPVu88JmsCuaO8FKEZBW sNE5i/N54z3SWIHhakeKTfgGXjCqlBDg== X-Received: by 2002:a05:6a00:1d83:b0:823:3056:c2b9 with SMTP id d2e1a72fcca58-826daaf421amr9257126b3a.65.1771935649115; Tue, 24 Feb 2026 04:20:49 -0800 (PST) Received: from rockpi-5b ([45.112.0.78]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-826dd8ba11bsm10613950b3a.50.2026.02.24.04.20.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Feb 2026 04:20:48 -0800 (PST) From: Anand Moon To: Thierry Reding , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Hunter , Aaron Kling , linux-tegra@vger.kernel.org (open list:PCI DRIVER FOR NVIDIA TEGRA), linux-pci@vger.kernel.org (open list:PCI DRIVER FOR NVIDIA TEGRA), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [PATCH v3 4/5] PCI: tegra: Use readl_poll_timeout() for link status polling Date: Tue, 24 Feb 2026 17:49:00 +0530 Message-ID: <20260224121948.25218-5-linux.amoon@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260224121948.25218-1-linux.amoon@gmail.com> References: <20260224121948.25218-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace the manual `do-while` polling loops with the readl_poll_timeout() helper when checking the link DL_UP and DL_LINK_ACTIVE status bits during link bring-up. This simplifies the code by removing the open-coded timeout logic in favor of the standard, more robust iopoll framework. The change improves readability and reduces code duplication. Cc: Thierry Reding Signed-off-by: Anand Moon --- v3: None v2: None v1: dropped the include header file. --- drivers/pci/controller/pci-tegra.c | 37 +++++++++++------------------- 1 file changed, 14 insertions(+), 23 deletions(-) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pc= i-tegra.c index 32dc11d95cc9..459a2bb1a065 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -2156,37 +2156,28 @@ static bool tegra_pcie_port_check_link(struct tegra= _pcie_port *port) value |=3D RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT; writel(value, port->base + RP_PRIV_MISC); =20 - do { - unsigned int timeout =3D TEGRA_PCIE_LINKUP_TIMEOUT; + while (retries--) { + int err; =20 - do { - value =3D readl(port->base + RP_VEND_XP); - - if (value & RP_VEND_XP_DL_UP) - break; - - usleep_range(1000, 2000); - } while (--timeout); - - if (!timeout) { + err =3D readl_poll_timeout(port->base + RP_VEND_XP, value, + value & RP_VEND_XP_DL_UP, + 1000, + TEGRA_PCIE_LINKUP_TIMEOUT * 1000); + if (err) { dev_dbg(dev, "link %u down, retrying\n", port->index); goto retry; } =20 - timeout =3D TEGRA_PCIE_LINKUP_TIMEOUT; - - do { - value =3D readl(port->base + RP_LINK_CONTROL_STATUS); - - if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE) - return true; - - usleep_range(1000, 2000); - } while (--timeout); + err =3D readl_poll_timeout(port->base + RP_LINK_CONTROL_STATUS, + value, + value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE, + 1000, TEGRA_PCIE_LINKUP_TIMEOUT * 1000); + if (!err) + return true; =20 retry: tegra_pcie_port_reset(port); - } while (--retries); + } =20 return false; } --=20 2.50.1 From nobody Thu Apr 2 20:28:05 2026 Received: from mail-pf1-f171.google.com (mail-pf1-f171.google.com [209.85.210.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42A4B396D07 for ; Tue, 24 Feb 2026 12:21:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771935663; cv=none; b=ZQDekcjvtYrabquVjX6kj0l3zYHaNyXDYd8FfVb72ufEEmSu1PPlBF4i7zVdfBxl85zT2fvc9XoLTWfwdqRE8qvqcFgh3CGHTyRUN0yoJc0ud8W5umVeJddiBl8HoufkHgOkVHMw6THA4YDhd+TsjzFxPrjoR/998Lbk0i0yaFo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771935663; c=relaxed/simple; bh=vdq7Dsr0HTGgGV/rEsq86YAWdmr1EZmBQyEUGPlpEFI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=s77jIgJ2FWQnwS8yNU6/WWe2PZrz4hmbbMpDjEBna2od9MkgOXVe1aeDHJ4QLufwN/9vnXYTsQ1gYl0ukPPMx4NJh2kDlyqDVlfc2AzvoSS7fRELadU/O/5H8cztsqonpJhB49KV2NGDHKj99LAAA7viYu5oIqZC3qgrlgFe/o8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=k1dxB29A; arc=none smtp.client-ip=209.85.210.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="k1dxB29A" Received: by mail-pf1-f171.google.com with SMTP id d2e1a72fcca58-823075fed75so2464380b3a.1 for ; Tue, 24 Feb 2026 04:21:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1771935661; x=1772540461; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZNUhGN2cviXrsigAKa0wCXrDKZYvpfYbqun2EtH//ys=; b=k1dxB29AvqAqtwaO/pg/OWLc6yjxI3isb8lHTR+YzVrcr7GzNlO8BuQB80MT6MpjK/ s+cn21f266cTNaCTgLC2azIofpGMn/h9r0OosVy+aZDwRX0do+ERspR7gFl2B7BNB9uK /bPi4Mzpnxeem4cQneLDmlEKd3HBum3Qk77yoyPJCPJYHN+fLRLeCIIkZoFOFEUL3fmV s96GPD8XEgdexLZBZdh3BX1kn66WpE4gyiyfkDXtz2+9HrnvHrgw6kolRMbluKMhZ0xT Cs2qn+efv+ZPFwp12LArkR4QlGPmZe4P4n1jVNoI7F6xRUfDxIUMqnk/7ZfuogrkEqAt cEVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771935661; x=1772540461; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=ZNUhGN2cviXrsigAKa0wCXrDKZYvpfYbqun2EtH//ys=; b=OOtwcGkhxDF5OJxA+z8eMw4qu0HI//ZY85/FIr1xXJLSdbLOqsF4XxJY/kU+ANSTxC Ry2gbK901iNCBSAYmI3YavlrpYQ/EsJqb8D+5CfG/g86EwZZ66hy9f2zfVnAubL3FMlx D6cDQ1ewR31YIgItlw3OJIBCTJPE3W2pwymJYxQpUUixC8GjxDi3T5SzXT9U0iw1GuhF X9DTKXpeGFcTjKzIjE0ox9NKYCbktkHjiq0/byv9a7CtDnOqKLAi+FYa5bFcrWWQ8qso IIurSTWHu3Jv+i8rLZjlSQupprw257w9vxLhOroGxbA13oSHz/79A84ARWOWXw9wMHNW A26w== X-Forwarded-Encrypted: i=1; AJvYcCWI2KPAy0xPXzVqYvrHq302btC9qPOU+lz9zGDgsOm7FzelLcUxrEMruWtKy8jo+QaclluHjHiB8hzerZ4=@vger.kernel.org X-Gm-Message-State: AOJu0YwQE773bVdxk3H6m9EktmvcnHkztpPKQ/frIGyWGBqTIxZc4Qi6 fEIWhh13qdgyv/d7xUneaSnIDQvn2/fxCLoDtbTGOlbrv6AWqhAFT0kX X-Gm-Gg: ATEYQzw6QRHEKG1N5TDDjwhpErlGDtGfJpXsle/l0TkwuKIydB9De+jRDKT64modgEs tGk6k7cmU5FUJnzfWXFQ2k8LthyogPQmYsyuL9h0J+ZJcYeMccdoDtMJrtMKyrOlrvoBOmuaacF Z9aoDCI8719Id17yAvYxSJoHnpWyfOMiBttcAFpDq1E5plaHiWKFe1yCYJGjnaGmYdNrSMwpsp5 cJ6jVKYZG2AkP912eLz3h/5zZxJtEc5cN/Bs+fAqygJqHiyvVy3uRrYMk11led3DdDBeLd4UkGM 5bLHhIcYdso6te7F0mKqI9h/9pFgnPVQHQI8KN/N/NAAP3Im5VPYQ4XyqNpsX4IoWSsyyJMudy6 lk40q7OS6FMT8fNFWNbK1s99BOl6RH0WHQ3bMM7Wh7Q6kJ0JgjhO4SIknFlw99WxIA0VdJUFfPw AdX7kie412KnUwkR4G5WU= X-Received: by 2002:a05:6a00:1150:b0:824:3d5b:3cd3 with SMTP id d2e1a72fcca58-826db59819bmr9505254b3a.0.1771935660653; Tue, 24 Feb 2026 04:21:00 -0800 (PST) Received: from rockpi-5b ([45.112.0.78]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-826dd8ba11bsm10613950b3a.50.2026.02.24.04.20.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Feb 2026 04:20:59 -0800 (PST) From: Anand Moon To: Thierry Reding , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Hunter , Aaron Kling , linux-tegra@vger.kernel.org (open list:PCI DRIVER FOR NVIDIA TEGRA), linux-pci@vger.kernel.org (open list:PCI DRIVER FOR NVIDIA TEGRA), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [PATCH v3 5/5] PCI: tegra: Use BIT() and GENMASK() macros for register definitions Date: Tue, 24 Feb 2026 17:49:01 +0530 Message-ID: <20260224121948.25218-6-linux.amoon@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260224121948.25218-1-linux.amoon@gmail.com> References: <20260224121948.25218-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace manual bit operations with standard BIT() and GENMASK() macros. This eliminates magic numbers, enhances readability, improves maintainability, and resolves checkpatch.pl warnings. Cc: Jon Hunter Signed-off-by: Anand Moon --- v3: None v2: improve the commit message v1: New patch --- drivers/pci/controller/pci-tegra.c | 129 +++++++++++++++-------------- 1 file changed, 65 insertions(+), 64 deletions(-) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pc= i-tegra.c index 459a2bb1a065..2c806404f572 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -13,6 +13,7 @@ * Author: Thierry Reding */ =20 +#include #include #include #include @@ -85,17 +86,17 @@ #define AFI_MSI_EN_VEC(x) (0x8c + ((x) * 4)) =20 #define AFI_CONFIGURATION 0xac -#define AFI_CONFIGURATION_EN_FPCI (1 << 0) -#define AFI_CONFIGURATION_CLKEN_OVERRIDE (1 << 31) +#define AFI_CONFIGURATION_EN_FPCI BIT(0) +#define AFI_CONFIGURATION_CLKEN_OVERRIDE BIT(31) =20 #define AFI_FPCI_ERROR_MASKS 0xb0 =20 #define AFI_INTR_MASK 0xb4 -#define AFI_INTR_MASK_INT_MASK (1 << 0) -#define AFI_INTR_MASK_MSI_MASK (1 << 8) +#define AFI_INTR_MASK_INT_MASK BIT(0) +#define AFI_INTR_MASK_MSI_MASK BIT(8) =20 #define AFI_INTR_CODE 0xb8 -#define AFI_INTR_CODE_MASK 0xf +#define AFI_INTR_CODE_MASK GENMASK(3, 0) #define AFI_INTR_INI_SLAVE_ERROR 1 #define AFI_INTR_INI_DECODE_ERROR 2 #define AFI_INTR_TARGET_ABORT 3 @@ -114,32 +115,32 @@ #define AFI_INTR_SIGNATURE 0xbc #define AFI_UPPER_FPCI_ADDRESS 0xc0 #define AFI_SM_INTR_ENABLE 0xc4 -#define AFI_SM_INTR_INTA_ASSERT (1 << 0) -#define AFI_SM_INTR_INTB_ASSERT (1 << 1) -#define AFI_SM_INTR_INTC_ASSERT (1 << 2) -#define AFI_SM_INTR_INTD_ASSERT (1 << 3) -#define AFI_SM_INTR_INTA_DEASSERT (1 << 4) -#define AFI_SM_INTR_INTB_DEASSERT (1 << 5) -#define AFI_SM_INTR_INTC_DEASSERT (1 << 6) -#define AFI_SM_INTR_INTD_DEASSERT (1 << 7) +#define AFI_SM_INTR_INTA_ASSERT BIT(0) +#define AFI_SM_INTR_INTB_ASSERT BIT(1) +#define AFI_SM_INTR_INTC_ASSERT BIT(2) +#define AFI_SM_INTR_INTD_ASSERT BIT(3) +#define AFI_SM_INTR_INTA_DEASSERT BIT(4) +#define AFI_SM_INTR_INTB_DEASSERT BIT(5) +#define AFI_SM_INTR_INTC_DEASSERT BIT(6) +#define AFI_SM_INTR_INTD_DEASSERT BIT(7) =20 #define AFI_AFI_INTR_ENABLE 0xc8 -#define AFI_INTR_EN_INI_SLVERR (1 << 0) -#define AFI_INTR_EN_INI_DECERR (1 << 1) -#define AFI_INTR_EN_TGT_SLVERR (1 << 2) -#define AFI_INTR_EN_TGT_DECERR (1 << 3) -#define AFI_INTR_EN_TGT_WRERR (1 << 4) -#define AFI_INTR_EN_DFPCI_DECERR (1 << 5) -#define AFI_INTR_EN_AXI_DECERR (1 << 6) -#define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7) -#define AFI_INTR_EN_PRSNT_SENSE (1 << 8) +#define AFI_INTR_EN_INI_SLVERR BIT(0) +#define AFI_INTR_EN_INI_DECERR BIT(1) +#define AFI_INTR_EN_TGT_SLVERR BIT(2) +#define AFI_INTR_EN_TGT_DECERR BIT(3) +#define AFI_INTR_EN_TGT_WRERR BIT(4) +#define AFI_INTR_EN_DFPCI_DECERR BIT(5) +#define AFI_INTR_EN_AXI_DECERR BIT(6) +#define AFI_INTR_EN_FPCI_TIMEOUT BIT(7) +#define AFI_INTR_EN_PRSNT_SENSE BIT(8) =20 #define AFI_PCIE_PME 0xf0 =20 #define AFI_PCIE_CONFIG 0x0f8 -#define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) -#define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe -#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) +#define AFI_PCIE_CONFIG_PCIE_DISABLE(x) BIT((x) + 1) +#define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL GENMASK(3, 1) +#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK GENMASK(23, 20) #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20) #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20) #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20) @@ -150,79 +151,79 @@ #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_211 (0x1 << 20) #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20) #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_111 (0x2 << 20) -#define AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO(x) (1 << ((x) + 29)) -#define AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO_ALL (0x7 << 29) +#define AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO(x) BIT((x) + 29) +#define AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO_ALL GENMASK(31, 29) =20 #define AFI_FUSE 0x104 -#define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) +#define AFI_FUSE_PCIE_T0_GEN2_DIS BIT(2) =20 #define AFI_PEX0_CTRL 0x110 #define AFI_PEX1_CTRL 0x118 -#define AFI_PEX_CTRL_RST (1 << 0) -#define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) -#define AFI_PEX_CTRL_REFCLK_EN (1 << 3) -#define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4) +#define AFI_PEX_CTRL_RST BIT(0) +#define AFI_PEX_CTRL_CLKREQ_EN BIT(1) +#define AFI_PEX_CTRL_REFCLK_EN BIT(3) +#define AFI_PEX_CTRL_OVERRIDE_EN BIT(4) =20 #define AFI_PLLE_CONTROL 0x160 -#define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) -#define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1) +#define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL BIT(9) +#define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN BIT(1) =20 #define AFI_PEXBIAS_CTRL_0 0x168 =20 #define RP_ECTL_2_R1 0x00000e84 -#define RP_ECTL_2_R1_RX_CTLE_1C_MASK 0xffff +#define RP_ECTL_2_R1_RX_CTLE_1C_MASK GENMASK(15, 0) =20 #define RP_ECTL_4_R1 0x00000e8c -#define RP_ECTL_4_R1_RX_CDR_CTRL_1C_MASK (0xffff << 16) +#define RP_ECTL_4_R1_RX_CDR_CTRL_1C_MASK GENMASK(31, 16) #define RP_ECTL_4_R1_RX_CDR_CTRL_1C_SHIFT 16 =20 #define RP_ECTL_5_R1 0x00000e90 -#define RP_ECTL_5_R1_RX_EQ_CTRL_L_1C_MASK 0xffffffff +#define RP_ECTL_5_R1_RX_EQ_CTRL_L_1C_MASK GENMASK(31, 0) =20 #define RP_ECTL_6_R1 0x00000e94 -#define RP_ECTL_6_R1_RX_EQ_CTRL_H_1C_MASK 0xffffffff +#define RP_ECTL_6_R1_RX_EQ_CTRL_H_1C_MASK GENMASK(31, 0) =20 #define RP_ECTL_2_R2 0x00000ea4 #define RP_ECTL_2_R2_RX_CTLE_1C_MASK 0xffff =20 #define RP_ECTL_4_R2 0x00000eac -#define RP_ECTL_4_R2_RX_CDR_CTRL_1C_MASK (0xffff << 16) +#define RP_ECTL_4_R2_RX_CDR_CTRL_1C_MASK GENMASK(31, 16) #define RP_ECTL_4_R2_RX_CDR_CTRL_1C_SHIFT 16 =20 #define RP_ECTL_5_R2 0x00000eb0 -#define RP_ECTL_5_R2_RX_EQ_CTRL_L_1C_MASK 0xffffffff +#define RP_ECTL_5_R2_RX_EQ_CTRL_L_1C_MASK GENMASK(31, 0) =20 #define RP_ECTL_6_R2 0x00000eb4 -#define RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK 0xffffffff +#define RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK GENMASK(31, 0) =20 #define RP_VEND_XP 0x00000f00 -#define RP_VEND_XP_DL_UP (1 << 30) -#define RP_VEND_XP_OPPORTUNISTIC_ACK (1 << 27) -#define RP_VEND_XP_OPPORTUNISTIC_UPDATEFC (1 << 28) -#define RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK (0xff << 18) +#define RP_VEND_XP_DL_UP BIT(30) +#define RP_VEND_XP_OPPORTUNISTIC_ACK BIT(27) +#define RP_VEND_XP_OPPORTUNISTIC_UPDATEFC BIT(28) +#define RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK GENMASK(25, 18) =20 #define RP_VEND_CTL0 0x00000f44 -#define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK (0xf << 12) +#define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK GENMASK(15, 12) #define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH (0x9 << 12) =20 #define RP_VEND_CTL1 0x00000f48 -#define RP_VEND_CTL1_ERPT (1 << 13) +#define RP_VEND_CTL1_ERPT BIT(13) =20 #define RP_VEND_XP_BIST 0x00000f4c -#define RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE (1 << 28) +#define RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE BIT(28) =20 #define RP_VEND_CTL2 0x00000fa8 -#define RP_VEND_CTL2_PCA_ENABLE (1 << 7) +#define RP_VEND_CTL2_PCA_ENABLE BIT(7) =20 #define RP_PRIV_MISC 0x00000fe0 -#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xe << 0) -#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xf << 0) -#define RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_MASK (0x7f << 16) +#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT GENMASK(3, 1) +#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT GENMASK(3, 0) +#define RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_MASK GENMASK(22, 16) #define RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD (0xf << 16) -#define RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE (1 << 23) -#define RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_MASK (0x7f << 24) +#define RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE BIT(23) +#define RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_MASK GENMASK(30, 24) #define RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD (0xf << 24) -#define RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE (1 << 31) +#define RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE BIT(31) =20 #define RP_LINK_CONTROL_STATUS 0x00000090 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 @@ -233,22 +234,22 @@ #define PADS_CTL_SEL 0x0000009c =20 #define PADS_CTL 0x000000a0 -#define PADS_CTL_IDDQ_1L (1 << 0) -#define PADS_CTL_TX_DATA_EN_1L (1 << 6) -#define PADS_CTL_RX_DATA_EN_1L (1 << 10) +#define PADS_CTL_IDDQ_1L BIT(0) +#define PADS_CTL_TX_DATA_EN_1L BIT(6) +#define PADS_CTL_RX_DATA_EN_1L BIT(10) =20 #define PADS_PLL_CTL_TEGRA20 0x000000b8 #define PADS_PLL_CTL_TEGRA30 0x000000b4 -#define PADS_PLL_CTL_RST_B4SM (1 << 1) -#define PADS_PLL_CTL_LOCKDET (1 << 8) -#define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16) +#define PADS_PLL_CTL_RST_B4SM BIT(1) +#define PADS_PLL_CTL_LOCKDET BIT(8) +#define PADS_PLL_CTL_REFCLK_MASK GENMASK(17, 16) #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0 << 16) -#define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (1 << 16) +#define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS BIT(16) #define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16) #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20) #define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20) -#define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20) -#define PADS_PLL_CTL_TXCLKREF_BUF_EN (1 << 22) +#define PADS_PLL_CTL_TXCLKREF_DIV5 BIT(20) +#define PADS_PLL_CTL_TXCLKREF_BUF_EN BIT(22) =20 #define PADS_REFCLK_CFG0 0x000000c8 #define PADS_REFCLK_CFG1 0x000000cc --=20 2.50.1