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charset="utf-8" DS90UB954-Q1 is an FPDLink-III deserializer that is mostly register compatible with DS90UB960-Q1. The main difference is that it supports half of the RX and TX ports, i.e. 2x FPDLink RX ports and 1x CSI TX port. A couple of differences are between the status registers and the strobe setting registers. Hence accommodate these differences in the UB960 driver so that we can reuse a large part of the existing code. Link: https://www.ti.com/lit/gpn/ds90ub954-q1 Reviewed-by: Jai Luthra Reviewed-by: Tomi Valkeinen Signed-off-by: Yemike Abhilash Chandra --- Changelog: Changes in v3: - Rebase on top of next-20260223 drivers/media/i2c/Kconfig | 4 +- drivers/media/i2c/ds90ub960.c | 182 ++++++++++++++++++++++++---------- 2 files changed, 129 insertions(+), 57 deletions(-) diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index c4a5006e8c72..c88b34a1aebf 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -1736,8 +1736,8 @@ config VIDEO_DS90UB960 select V4L2_FWNODE select VIDEO_V4L2_SUBDEV_API help - Device driver for the Texas Instruments DS90UB960 - FPD-Link III Deserializer and DS90UB9702 FPD-Link IV Deserializer. + Device driver for the Texas Instruments DS90UB954, DS90UB960 + FPD-Link III Deserializers and DS90UB9702 FPD-Link IV Deserializer. =20 config VIDEO_MAX96714 tristate "Maxim MAX96714 GMSL2 deserializer" diff --git a/drivers/media/i2c/ds90ub960.c b/drivers/media/i2c/ds90ub960.c index ed4d6f786e15..97c2b9352833 100644 --- a/drivers/media/i2c/ds90ub960.c +++ b/drivers/media/i2c/ds90ub960.c @@ -396,6 +396,13 @@ #define UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY BIT(3) #define UB960_IR_RX_ANA_STROBE_SET_DATA_DELAY_MASK GENMASK(2, 0) =20 +#define UB954_IR_RX_ANA_STROBE_SET_CLK_DATA 0x08 +#define UB954_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY BIT(3) +#define UB954_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY BIT(7) +#define UB954_IR_RX_ANA_STROBE_SET_CLK_DELAY_MASK GENMASK(2, 0) +#define UB954_IR_RX_ANA_STROBE_SET_DATA_DELAY_MASK GENMASK(4, 6) +#define UB954_IR_RX_ANA_STROBE_SET_DATA_DELAY_SHIFT 4 + /* UB9702 Registers */ =20 #define UB9702_SR_CSI_EXCLUSIVE_FWD2 0x3c @@ -455,6 +462,7 @@ #define UB960_NUM_EQ_LEVELS (UB960_MAX_EQ_LEVEL - UB960_MIN_EQ_LEVEL + 1) =20 enum chip_type { + UB954, UB960, UB9702, }; @@ -1001,6 +1009,10 @@ static int ub960_txport_select(struct ub960_data *pr= iv, u8 nport) =20 lockdep_assert_held(&priv->reg_lock); =20 + /* UB954 has only 1 CSI TX. Hence, no need to select */ + if (priv->hw_data->chip_type =3D=3D UB954) + return 0; + if (priv->reg_current.txport =3D=3D nport) return 0; =20 @@ -1425,10 +1437,11 @@ static int ub960_parse_dt_txport(struct ub960_data = *priv, priv->tx_link_freq[0] =3D vep.link_frequencies[0]; priv->tx_data_rate =3D priv->tx_link_freq[0] * 2; =20 - if (priv->tx_data_rate !=3D MHZ(1600) && - priv->tx_data_rate !=3D MHZ(1200) && - priv->tx_data_rate !=3D MHZ(800) && - priv->tx_data_rate !=3D MHZ(400)) { + if ((priv->tx_data_rate !=3D MHZ(1600) && + priv->tx_data_rate !=3D MHZ(1200) && + priv->tx_data_rate !=3D MHZ(800) && + priv->tx_data_rate !=3D MHZ(400)) || + (priv->hw_data->chip_type =3D=3D UB954 && priv->tx_data_rate =3D=3D = MHZ(1200))) { dev_err(dev, "tx%u: invalid 'link-frequencies' value\n", nport); ret =3D -EINVAL; goto err_free_vep; @@ -1552,22 +1565,35 @@ static int ub960_rxport_get_strobe_pos(struct ub960= _data *priv, u8 clk_delay, data_delay; int ret; =20 - ret =3D ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport), - UB960_IR_RX_ANA_STROBE_SET_CLK, &v, NULL); - if (ret) - return ret; + if (priv->hw_data->chip_type =3D=3D UB954) { + ret =3D ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport), + UB954_IR_RX_ANA_STROBE_SET_CLK_DATA, &v, NULL); + if (ret) + return ret; =20 - clk_delay =3D (v & UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY) ? - 0 : UB960_MANUAL_STROBE_EXTRA_DELAY; + clk_delay =3D (v & UB954_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY) ? + 0 : UB960_MANUAL_STROBE_EXTRA_DELAY; =20 - ret =3D ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport), - UB960_IR_RX_ANA_STROBE_SET_DATA, &v, NULL); - if (ret) - return ret; + data_delay =3D (v & UB954_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY) ? + 0 : UB960_MANUAL_STROBE_EXTRA_DELAY; + } else { + ret =3D ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport), + UB960_IR_RX_ANA_STROBE_SET_CLK, &v, NULL); + if (ret) + return ret; =20 - data_delay =3D (v & UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY) ? + clk_delay =3D (v & UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY) ? 0 : UB960_MANUAL_STROBE_EXTRA_DELAY; =20 + ret =3D ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport), + UB960_IR_RX_ANA_STROBE_SET_DATA, &v, NULL); + if (ret) + return ret; + + data_delay =3D (v & UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY) ? + 0 : UB960_MANUAL_STROBE_EXTRA_DELAY; + } + ret =3D ub960_rxport_read(priv, nport, UB960_RR_SFILTER_STS_0, &v, NULL); if (ret) return ret; @@ -1588,26 +1614,49 @@ static int ub960_rxport_get_strobe_pos(struct ub960= _data *priv, static int ub960_rxport_set_strobe_pos(struct ub960_data *priv, unsigned int nport, s8 strobe_pos) { - u8 clk_delay, data_delay; int ret =3D 0; =20 - clk_delay =3D UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY; - data_delay =3D UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY; - - if (strobe_pos < UB960_MIN_AEQ_STROBE_POS) - clk_delay =3D abs(strobe_pos) - UB960_MANUAL_STROBE_EXTRA_DELAY; - else if (strobe_pos > UB960_MAX_AEQ_STROBE_POS) - data_delay =3D strobe_pos - UB960_MANUAL_STROBE_EXTRA_DELAY; - else if (strobe_pos < 0) - clk_delay =3D abs(strobe_pos) | UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_= DELAY; - else if (strobe_pos > 0) - data_delay =3D strobe_pos | UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DEL= AY; - - ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), - UB960_IR_RX_ANA_STROBE_SET_CLK, clk_delay, &ret); - - ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), - UB960_IR_RX_ANA_STROBE_SET_DATA, data_delay, &ret); + if (priv->hw_data->chip_type =3D=3D UB954) { + u8 clk_data_delay; + + clk_data_delay =3D UB954_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY | + UB954_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY; + + if (strobe_pos < UB960_MIN_AEQ_STROBE_POS) + clk_data_delay =3D abs(strobe_pos) - UB960_MANUAL_STROBE_EXTRA_DELAY; + else if (strobe_pos > UB960_MAX_AEQ_STROBE_POS) + clk_data_delay =3D (strobe_pos - UB960_MANUAL_STROBE_EXTRA_DELAY) << + UB954_IR_RX_ANA_STROBE_SET_DATA_DELAY_SHIFT; + else if (strobe_pos < 0) + clk_data_delay =3D abs(strobe_pos) | + UB954_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY; + else if (strobe_pos > 0) + clk_data_delay =3D (strobe_pos | + UB954_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY) << + UB954_IR_RX_ANA_STROBE_SET_DATA_DELAY_SHIFT; + + ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), + UB954_IR_RX_ANA_STROBE_SET_CLK_DATA, clk_data_delay, &ret); + } else { + u8 clk_delay, data_delay; + + clk_delay =3D UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY; + data_delay =3D UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY; + + if (strobe_pos < UB960_MIN_AEQ_STROBE_POS) + clk_delay =3D abs(strobe_pos) - UB960_MANUAL_STROBE_EXTRA_DELAY; + else if (strobe_pos > UB960_MAX_AEQ_STROBE_POS) + data_delay =3D strobe_pos - UB960_MANUAL_STROBE_EXTRA_DELAY; + else if (strobe_pos < 0) + clk_delay =3D abs(strobe_pos) | UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA= _DELAY; + else if (strobe_pos > 0) + data_delay =3D strobe_pos | UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DE= LAY; + + ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), + UB960_IR_RX_ANA_STROBE_SET_CLK, clk_delay, &ret); + ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), + UB960_IR_RX_ANA_STROBE_SET_DATA, data_delay, &ret); + } =20 return ret; } @@ -3643,7 +3692,8 @@ static int ub960_configure_ports_for_streaming(struct= ub960_data *priv, =20 case RXPORT_MODE_CSI2_SYNC: case RXPORT_MODE_CSI2_NONSYNC: - if (priv->hw_data->chip_type =3D=3D UB960) { + if (priv->hw_data->chip_type =3D=3D UB960 || + priv->hw_data->chip_type =3D=3D UB954) { /* Map all VCs from this port to the same VC */ ub960_rxport_write(priv, nport, UB960_RR_CSI_VC_MAP, (vc << UB960_RR_CSI_VC_MAP_SHIFT(3)) | @@ -4177,33 +4227,40 @@ static int ub960_log_status(struct v4l2_subdev *sd) dev_info(dev, "\tsync %u, pass %u\n", v & (u8)BIT(1), v & (u8)BIT(0)); =20 - ret =3D ub960_read16(priv, UB960_SR_CSI_FRAME_COUNT_HI(nport), - &v16, NULL); - if (ret) - return ret; + /* + * Frame counter, frame error counter, line counter and line error count= er + * registers are marked as reserved in the UB954 datasheet. Hence restri= ct + * the following register reads only for UB960 and UB9702. + */ + if (priv->hw_data->chip_type =3D=3D UB960 || priv->hw_data->chip_type = =3D=3D UB9702) { + ret =3D ub960_read16(priv, UB960_SR_CSI_FRAME_COUNT_HI(nport), + &v16, NULL); + if (ret) + return ret; =20 - dev_info(dev, "\tframe counter %u\n", v16); + dev_info(dev, "\tframe counter %u\n", v16); =20 - ret =3D ub960_read16(priv, UB960_SR_CSI_FRAME_ERR_COUNT_HI(nport), - &v16, NULL); - if (ret) - return ret; + ret =3D ub960_read16(priv, UB960_SR_CSI_FRAME_ERR_COUNT_HI(nport), + &v16, NULL); + if (ret) + return ret; =20 - dev_info(dev, "\tframe error counter %u\n", v16); + dev_info(dev, "\tframe error counter %u\n", v16); =20 - ret =3D ub960_read16(priv, UB960_SR_CSI_LINE_COUNT_HI(nport), - &v16, NULL); - if (ret) - return ret; + ret =3D ub960_read16(priv, UB960_SR_CSI_LINE_COUNT_HI(nport), + &v16, NULL); + if (ret) + return ret; =20 - dev_info(dev, "\tline counter %u\n", v16); + dev_info(dev, "\tline counter %u\n", v16); =20 - ret =3D ub960_read16(priv, UB960_SR_CSI_LINE_ERR_COUNT_HI(nport), - &v16, NULL); - if (ret) - return ret; + ret =3D ub960_read16(priv, UB960_SR_CSI_LINE_ERR_COUNT_HI(nport), + &v16, NULL); + if (ret) + return ret; =20 - dev_info(dev, "\tline error counter %u\n", v16); + dev_info(dev, "\tline error counter %u\n", v16); + } } =20 for_each_rxport(priv, it) { @@ -4269,7 +4326,7 @@ static int ub960_log_status(struct v4l2_subdev *sd) =20 dev_info(dev, "\tcsi_err_counter %u\n", v); =20 - if (priv->hw_data->chip_type =3D=3D UB960) { + if (priv->hw_data->chip_type =3D=3D UB960 || priv->hw_data->chip_type = =3D=3D UB954) { ret =3D ub960_log_status_ub960_sp_eq(priv, nport); if (ret) return ret; @@ -5029,6 +5086,11 @@ static int ub960_enable_core_hw(struct ub960_data *p= riv) if (ret) goto err_pd_gpio; =20 + /* + * UB954 REFCLK_FREQ is not synchronized, so multiple reads are recommend= ed + * by the datasheet. However, a single read is practically seen to be + * sufficient and moreover it is only used for a debug print. + */ if (priv->hw_data->chip_type =3D=3D UB9702) ret =3D ub960_read(priv, UB9702_SR_REFCLK_FREQ, &refclk_freq, NULL); @@ -5188,6 +5250,14 @@ static void ub960_remove(struct i2c_client *client) mutex_destroy(&priv->reg_lock); } =20 +static const struct ub960_hw_data ds90ub954_hw =3D { + .model =3D "ub954", + .chip_type =3D UB954, + .chip_family =3D FAMILY_FPD3, + .num_rxports =3D 2, + .num_txports =3D 1, +}; + static const struct ub960_hw_data ds90ub960_hw =3D { .model =3D "ub960", .chip_type =3D UB960, @@ -5205,6 +5275,7 @@ static const struct ub960_hw_data ds90ub9702_hw =3D { }; =20 static const struct i2c_device_id ub960_id[] =3D { + { "ds90ub954-q1", (kernel_ulong_t)&ds90ub954_hw }, { "ds90ub960-q1", (kernel_ulong_t)&ds90ub960_hw }, { "ds90ub9702-q1", (kernel_ulong_t)&ds90ub9702_hw }, {} @@ -5212,6 +5283,7 @@ static const struct i2c_device_id ub960_id[] =3D { MODULE_DEVICE_TABLE(i2c, ub960_id); =20 static const struct of_device_id ub960_dt_ids[] =3D { + { .compatible =3D "ti,ds90ub954-q1", .data =3D &ds90ub954_hw }, { .compatible =3D "ti,ds90ub960-q1", .data =3D &ds90ub960_hw }, { .compatible =3D "ti,ds90ub9702-q1", .data =3D &ds90ub9702_hw }, {} --=20 2.34.1