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charset="utf-8" The current bindings duplicate the port definitions for each FPD-Link RX and CSI-2 TX ports. This results in a large amount of repeated schema blocks and makes it harder to extend the bindings for new devices. Refactor the bindings by introducing shared deftinitions for FPD-Link input ports and CSI-2 output ports. No functional change intended. Reviewed-by: Rob Herring (Arm) Reviewed-by: Tomi Valkeinen Signed-off-by: Yemike Abhilash Chandra --- Changelog: Changes in v3: - Rebase on top of next-20260223 .../bindings/media/i2c/ti,ds90ub960.yaml | 120 +++++++----------- 1 file changed, 44 insertions(+), 76 deletions(-) diff --git a/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml = b/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml index 0539d52de422..cc61604eca37 100644 --- a/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml +++ b/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml @@ -125,102 +125,35 @@ properties: =20 ports: $ref: /schemas/graph.yaml#/properties/ports + description: + Ports represent FPD-Link inputs to the deserializer and CSI TX outpu= ts + from the deserializer. The number of ports is model-dependent. =20 properties: port@0: - $ref: /schemas/graph.yaml#/$defs/port-base - unevaluatedProperties: false + $ref: '#/$defs/FPDLink-input-port' description: FPD-Link input 0 =20 - properties: - endpoint: - $ref: /schemas/media/video-interfaces.yaml# - unevaluatedProperties: false - description: - Endpoint for FPD-Link port. If the RX mode for this port is = RAW, - hsync-active and vsync-active must be defined. - port@1: - $ref: /schemas/graph.yaml#/$defs/port-base - unevaluatedProperties: false + $ref: '#/$defs/FPDLink-input-port' description: FPD-Link input 1 =20 - properties: - endpoint: - $ref: /schemas/media/video-interfaces.yaml# - unevaluatedProperties: false - description: - Endpoint for FPD-Link port. If the RX mode for this port is = RAW, - hsync-active and vsync-active must be defined. - port@2: - $ref: /schemas/graph.yaml#/$defs/port-base - unevaluatedProperties: false + $ref: '#/$defs/FPDLink-input-port' description: FPD-Link input 2 =20 - properties: - endpoint: - $ref: /schemas/media/video-interfaces.yaml# - unevaluatedProperties: false - description: - Endpoint for FPD-Link port. If the RX mode for this port is = RAW, - hsync-active and vsync-active must be defined. - port@3: - $ref: /schemas/graph.yaml#/$defs/port-base - unevaluatedProperties: false + $ref: '#/$defs/FPDLink-input-port' description: FPD-Link input 3 =20 - properties: - endpoint: - $ref: /schemas/media/video-interfaces.yaml# - unevaluatedProperties: false - description: - Endpoint for FPD-Link port. If the RX mode for this port is = RAW, - hsync-active and vsync-active must be defined. - port@4: - $ref: /schemas/graph.yaml#/$defs/port-base - unevaluatedProperties: false + $ref: '#/$defs/CSI2-output-port' description: CSI-2 Output 0 =20 - properties: - endpoint: - $ref: /schemas/media/video-interfaces.yaml# - unevaluatedProperties: false - - properties: - data-lanes: - minItems: 1 - maxItems: 4 - link-frequencies: - maxItems: 1 - - required: - - data-lanes - - link-frequencies - port@5: - $ref: /schemas/graph.yaml#/$defs/port-base - unevaluatedProperties: false + $ref: '#/$defs/CSI2-output-port' description: CSI-2 Output 1 =20 - properties: - endpoint: - $ref: /schemas/media/video-interfaces.yaml# - unevaluatedProperties: false - - properties: - data-lanes: - minItems: 1 - maxItems: 4 - link-frequencies: - maxItems: 1 - - required: - - data-lanes - - link-frequencies - required: - port@0 - port@1 @@ -236,6 +169,41 @@ required: - clock-names - ports =20 +$defs: + FPDLink-input-port: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: FPD-Link input + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + description: + Endpoint for FPD-Link port. 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charset="utf-8" Replace chip-specific boolean flags with chip_type and chip_family enums. This simplifies the process of adding support for newer devices and also improves code readability. Reviewed-by: Tomi Valkeinen Reviewed-by: Jai Luthra Signed-off-by: Yemike Abhilash Chandra --- Changelog: Changes in v3: - Rebase on top of next-20260223 drivers/media/i2c/ds90ub960.c | 38 +++++++++++++++++++++++------------ 1 file changed, 25 insertions(+), 13 deletions(-) diff --git a/drivers/media/i2c/ds90ub960.c b/drivers/media/i2c/ds90ub960.c index f453d96d9e43..ed4d6f786e15 100644 --- a/drivers/media/i2c/ds90ub960.c +++ b/drivers/media/i2c/ds90ub960.c @@ -454,12 +454,22 @@ #define UB960_MAX_EQ_LEVEL 14 #define UB960_NUM_EQ_LEVELS (UB960_MAX_EQ_LEVEL - UB960_MIN_EQ_LEVEL + 1) =20 +enum chip_type { + UB960, + UB9702, +}; + +enum chip_family { + FAMILY_FPD3, + FAMILY_FPD4, +}; + struct ub960_hw_data { const char *model; + enum chip_type chip_type; + enum chip_family chip_family; u8 num_rxports; u8 num_txports; - bool is_ub9702; - bool is_fpdlink4; }; =20 enum ub960_rxport_mode { @@ -1933,7 +1943,7 @@ static int ub960_rxport_wait_locks(struct ub960_data = *priv, if (ret) return ret; =20 - if (priv->hw_data->is_ub9702) { + if (priv->hw_data->chip_type =3D=3D UB9702) { dev_dbg(dev, "\trx%u: locked, freq %llu Hz\n", nport, ((u64)v * HZ_PER_MHZ) >> 8); } else { @@ -2195,7 +2205,7 @@ static int ub960_rxport_add_serializer(struct ub960_d= ata *priv, u8 nport) =20 ser_pdata->port =3D nport; ser_pdata->atr =3D priv->atr; - if (priv->hw_data->is_ub9702) + if (priv->hw_data->chip_type =3D=3D UB9702) ser_pdata->bc_rate =3D ub960_calc_bc_clk_rate_ub9702(priv, rxport); else ser_pdata->bc_rate =3D ub960_calc_bc_clk_rate_ub960(priv, rxport); @@ -2361,7 +2371,7 @@ static int ub960_init_tx_ports(struct ub960_data *pri= v) { int ret; =20 - if (priv->hw_data->is_ub9702) + if (priv->hw_data->chip_type =3D=3D UB9702) ret =3D ub960_init_tx_ports_ub9702(priv); else ret =3D ub960_init_tx_ports_ub960(priv); @@ -3633,7 +3643,7 @@ static int ub960_configure_ports_for_streaming(struct= ub960_data *priv, =20 case RXPORT_MODE_CSI2_SYNC: case RXPORT_MODE_CSI2_NONSYNC: - if (!priv->hw_data->is_ub9702) { + if (priv->hw_data->chip_type =3D=3D UB960) { /* Map all VCs from this port to the same VC */ ub960_rxport_write(priv, nport, UB960_RR_CSI_VC_MAP, (vc << UB960_RR_CSI_VC_MAP_SHIFT(3)) | @@ -4259,7 +4269,7 @@ static int ub960_log_status(struct v4l2_subdev *sd) =20 dev_info(dev, "\tcsi_err_counter %u\n", v); =20 - if (!priv->hw_data->is_ub9702) { + if (priv->hw_data->chip_type =3D=3D UB960) { ret =3D ub960_log_status_ub960_sp_eq(priv, nport); if (ret) return ret; @@ -4417,7 +4427,7 @@ ub960_parse_dt_rxport_link_properties(struct ub960_da= ta *priv, return -EINVAL; } =20 - if (!priv->hw_data->is_fpdlink4 && cdr_mode =3D=3D RXPORT_CDR_FPD4) { + if (priv->hw_data->chip_family !=3D FAMILY_FPD4 && cdr_mode =3D=3D RXPORT= _CDR_FPD4) { dev_err(dev, "rx%u: FPD-Link 4 CDR not supported\n", nport); return -EINVAL; } @@ -5019,7 +5029,7 @@ static int ub960_enable_core_hw(struct ub960_data *pr= iv) if (ret) goto err_pd_gpio; =20 - if (priv->hw_data->is_ub9702) + if (priv->hw_data->chip_type =3D=3D UB9702) ret =3D ub960_read(priv, UB9702_SR_REFCLK_FREQ, &refclk_freq, NULL); else @@ -5038,7 +5048,7 @@ static int ub960_enable_core_hw(struct ub960_data *pr= iv) goto err_pd_gpio; =20 /* release GPIO lock */ - if (priv->hw_data->is_ub9702) { + if (priv->hw_data->chip_type =3D=3D UB9702) { ret =3D ub960_update_bits(priv, UB960_SR_RESET, UB960_SR_RESET_GPIO_LOCK_RELEASE, UB960_SR_RESET_GPIO_LOCK_RELEASE, @@ -5111,7 +5121,7 @@ static int ub960_probe(struct i2c_client *client) if (ret) goto err_free_ports; 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charset="utf-8" DS90UB954-Q1 is an FPDLink-III deserializer that is mostly register compatible with DS90UB960-Q1. The main difference is that it supports half of the RX and TX ports, i.e. 2x FPDLink RX ports and 1x CSI TX port. Therefore, add support for DS90UB954 within the existing bindings. Link: https://www.ti.com/lit/gpn/ds90ub954-q1 Reviewed-by: Rob Herring (Arm) Reviewed-by: Tomi Valkeinen Signed-off-by: Yemike Abhilash Chandra --- Changelog: Changes in v3: - Rebase on top of next-20260223 .../bindings/media/i2c/ti,ds90ub960.yaml | 113 ++++++++++++------ 1 file changed, 77 insertions(+), 36 deletions(-) diff --git a/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml = b/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml index cc61604eca37..8e2b82d6dc81 100644 --- a/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml +++ b/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml @@ -13,12 +13,10 @@ description: The TI DS90UB9XX devices are FPD-Link video deserializers with I2C and G= PIO forwarding. =20 -allOf: - - $ref: /schemas/i2c/i2c-atr.yaml# - properties: compatible: enum: + - ti,ds90ub954-q1 - ti,ds90ub960-q1 - ti,ds90ub9702-q1 =20 @@ -129,39 +127,6 @@ properties: Ports represent FPD-Link inputs to the deserializer and CSI TX outpu= ts from the deserializer. The number of ports is model-dependent. =20 - properties: - port@0: - $ref: '#/$defs/FPDLink-input-port' - description: FPD-Link input 0 - - port@1: - $ref: '#/$defs/FPDLink-input-port' - description: FPD-Link input 1 - - port@2: - $ref: '#/$defs/FPDLink-input-port' - description: FPD-Link input 2 - - port@3: - $ref: '#/$defs/FPDLink-input-port' - description: FPD-Link input 3 - - port@4: - $ref: '#/$defs/CSI2-output-port' - description: CSI-2 Output 0 - - port@5: - $ref: '#/$defs/CSI2-output-port' - description: CSI-2 Output 1 - - required: - - port@0 - - port@1 - - port@2 - - port@3 - - port@4 - - port@5 - required: - compatible - reg @@ -204,6 +169,82 @@ $defs: - data-lanes - link-frequencies =20 +allOf: + - $ref: /schemas/i2c/i2c-atr.yaml# + - if: + properties: + compatible: + contains: + enum: + - ti,ds90ub960-q1 + - ti,ds90ub9702-q1 + then: + properties: + ports: + properties: + port@0: + $ref: '#/$defs/FPDLink-input-port' + description: FPD-Link input 0 + + port@1: + $ref: '#/$defs/FPDLink-input-port' + description: FPD-Link input 1 + + port@2: + $ref: '#/$defs/FPDLink-input-port' + description: FPD-Link input 2 + + port@3: + $ref: '#/$defs/FPDLink-input-port' + description: FPD-Link input 3 + + port@4: + $ref: '#/$defs/CSI2-output-port' + description: CSI-2 Output 0 + + port@5: + $ref: '#/$defs/CSI2-output-port' + description: CSI-2 Output 1 + + required: + - port@0 + - port@1 + - port@2 + - port@3 + - port@4 + - port@5 + + - if: + properties: + compatible: + contains: + const: ti,ds90ub954-q1 + then: + properties: + ports: + properties: + port@0: + $ref: '#/$defs/FPDLink-input-port' + description: FPD-Link input 0 + + port@1: + $ref: '#/$defs/FPDLink-input-port' + description: FPD-Link input 1 + + port@2: + $ref: '#/$defs/CSI2-output-port' + description: CSI-2 Output 0 + + required: + - port@0 + - port@1 + - port@2 + + links: + properties: + link@2: false + link@3: false + unevaluatedProperties: false =20 examples: --=20 2.34.1 From nobody Sun Apr 12 12:54:06 2026 Received: from SN4PR2101CU001.outbound.protection.outlook.com (mail-southcentralusazon11012057.outbound.protection.outlook.com [40.93.195.57]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA34137AA72; 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Tue, 24 Feb 2026 05:40:10 -0600 Received: from DLEE210.ent.ti.com (157.170.170.112) by DLEE205.ent.ti.com (157.170.170.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 24 Feb 2026 05:40:10 -0600 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE210.ent.ti.com (157.170.170.112) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Tue, 24 Feb 2026 05:40:10 -0600 Received: from abhilash-HP.dhcp.ti.com (abhilash-hp.dhcp.ti.com [10.24.51.219]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 61OBdaF32658018; Tue, 24 Feb 2026 05:40:05 -0600 From: Yemike Abhilash Chandra To: , , , , , , , CC: , , , , , , , , , , Subject: [PATCH V4 4/4] media: i2c: ds90ub960: Add support for DS90UB954-Q1 Date: Tue, 24 Feb 2026 17:09:24 +0530 Message-ID: <20260224113925.19983-5-y-abhilashchandra@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260224113925.19983-1-y-abhilashchandra@ti.com> References: <20260224113925.19983-1-y-abhilashchandra@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F66:EE_|CY5PR10MB5914:EE_ X-MS-Office365-Filtering-Correlation-Id: a3a28217-ef31-45cc-86d8-08de739977c5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014|7416014; 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charset="utf-8" DS90UB954-Q1 is an FPDLink-III deserializer that is mostly register compatible with DS90UB960-Q1. The main difference is that it supports half of the RX and TX ports, i.e. 2x FPDLink RX ports and 1x CSI TX port. A couple of differences are between the status registers and the strobe setting registers. Hence accommodate these differences in the UB960 driver so that we can reuse a large part of the existing code. Link: https://www.ti.com/lit/gpn/ds90ub954-q1 Reviewed-by: Jai Luthra Reviewed-by: Tomi Valkeinen Signed-off-by: Yemike Abhilash Chandra --- Changelog: Changes in v3: - Rebase on top of next-20260223 drivers/media/i2c/Kconfig | 4 +- drivers/media/i2c/ds90ub960.c | 182 ++++++++++++++++++++++++---------- 2 files changed, 129 insertions(+), 57 deletions(-) diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index c4a5006e8c72..c88b34a1aebf 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -1736,8 +1736,8 @@ config VIDEO_DS90UB960 select V4L2_FWNODE select VIDEO_V4L2_SUBDEV_API help - Device driver for the Texas Instruments DS90UB960 - FPD-Link III Deserializer and DS90UB9702 FPD-Link IV Deserializer. + Device driver for the Texas Instruments DS90UB954, DS90UB960 + FPD-Link III Deserializers and DS90UB9702 FPD-Link IV Deserializer. =20 config VIDEO_MAX96714 tristate "Maxim MAX96714 GMSL2 deserializer" diff --git a/drivers/media/i2c/ds90ub960.c b/drivers/media/i2c/ds90ub960.c index ed4d6f786e15..97c2b9352833 100644 --- a/drivers/media/i2c/ds90ub960.c +++ b/drivers/media/i2c/ds90ub960.c @@ -396,6 +396,13 @@ #define UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY BIT(3) #define UB960_IR_RX_ANA_STROBE_SET_DATA_DELAY_MASK GENMASK(2, 0) =20 +#define UB954_IR_RX_ANA_STROBE_SET_CLK_DATA 0x08 +#define UB954_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY BIT(3) +#define UB954_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY BIT(7) +#define UB954_IR_RX_ANA_STROBE_SET_CLK_DELAY_MASK GENMASK(2, 0) +#define UB954_IR_RX_ANA_STROBE_SET_DATA_DELAY_MASK GENMASK(4, 6) +#define UB954_IR_RX_ANA_STROBE_SET_DATA_DELAY_SHIFT 4 + /* UB9702 Registers */ =20 #define UB9702_SR_CSI_EXCLUSIVE_FWD2 0x3c @@ -455,6 +462,7 @@ #define UB960_NUM_EQ_LEVELS (UB960_MAX_EQ_LEVEL - UB960_MIN_EQ_LEVEL + 1) =20 enum chip_type { + UB954, UB960, UB9702, }; @@ -1001,6 +1009,10 @@ static int ub960_txport_select(struct ub960_data *pr= iv, u8 nport) =20 lockdep_assert_held(&priv->reg_lock); =20 + /* UB954 has only 1 CSI TX. Hence, no need to select */ + if (priv->hw_data->chip_type =3D=3D UB954) + return 0; + if (priv->reg_current.txport =3D=3D nport) return 0; =20 @@ -1425,10 +1437,11 @@ static int ub960_parse_dt_txport(struct ub960_data = *priv, priv->tx_link_freq[0] =3D vep.link_frequencies[0]; priv->tx_data_rate =3D priv->tx_link_freq[0] * 2; =20 - if (priv->tx_data_rate !=3D MHZ(1600) && - priv->tx_data_rate !=3D MHZ(1200) && - priv->tx_data_rate !=3D MHZ(800) && - priv->tx_data_rate !=3D MHZ(400)) { + if ((priv->tx_data_rate !=3D MHZ(1600) && + priv->tx_data_rate !=3D MHZ(1200) && + priv->tx_data_rate !=3D MHZ(800) && + priv->tx_data_rate !=3D MHZ(400)) || + (priv->hw_data->chip_type =3D=3D UB954 && priv->tx_data_rate =3D=3D = MHZ(1200))) { dev_err(dev, "tx%u: invalid 'link-frequencies' value\n", nport); ret =3D -EINVAL; goto err_free_vep; @@ -1552,22 +1565,35 @@ static int ub960_rxport_get_strobe_pos(struct ub960= _data *priv, u8 clk_delay, data_delay; int ret; =20 - ret =3D ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport), - UB960_IR_RX_ANA_STROBE_SET_CLK, &v, NULL); - if (ret) - return ret; + if (priv->hw_data->chip_type =3D=3D UB954) { + ret =3D ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport), + UB954_IR_RX_ANA_STROBE_SET_CLK_DATA, &v, NULL); + if (ret) + return ret; =20 - clk_delay =3D (v & UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY) ? - 0 : UB960_MANUAL_STROBE_EXTRA_DELAY; + clk_delay =3D (v & UB954_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY) ? + 0 : UB960_MANUAL_STROBE_EXTRA_DELAY; =20 - ret =3D ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport), - UB960_IR_RX_ANA_STROBE_SET_DATA, &v, NULL); - if (ret) - return ret; + data_delay =3D (v & UB954_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY) ? + 0 : UB960_MANUAL_STROBE_EXTRA_DELAY; + } else { + ret =3D ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport), + UB960_IR_RX_ANA_STROBE_SET_CLK, &v, NULL); + if (ret) + return ret; =20 - data_delay =3D (v & UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY) ? + clk_delay =3D (v & UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY) ? 0 : UB960_MANUAL_STROBE_EXTRA_DELAY; =20 + ret =3D ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport), + UB960_IR_RX_ANA_STROBE_SET_DATA, &v, NULL); + if (ret) + return ret; + + data_delay =3D (v & UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY) ? + 0 : UB960_MANUAL_STROBE_EXTRA_DELAY; + } + ret =3D ub960_rxport_read(priv, nport, UB960_RR_SFILTER_STS_0, &v, NULL); if (ret) return ret; @@ -1588,26 +1614,49 @@ static int ub960_rxport_get_strobe_pos(struct ub960= _data *priv, static int ub960_rxport_set_strobe_pos(struct ub960_data *priv, unsigned int nport, s8 strobe_pos) { - u8 clk_delay, data_delay; int ret =3D 0; =20 - clk_delay =3D UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY; - data_delay =3D UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY; - - if (strobe_pos < UB960_MIN_AEQ_STROBE_POS) - clk_delay =3D abs(strobe_pos) - UB960_MANUAL_STROBE_EXTRA_DELAY; - else if (strobe_pos > UB960_MAX_AEQ_STROBE_POS) - data_delay =3D strobe_pos - UB960_MANUAL_STROBE_EXTRA_DELAY; - else if (strobe_pos < 0) - clk_delay =3D abs(strobe_pos) | UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_= DELAY; - else if (strobe_pos > 0) - data_delay =3D strobe_pos | UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DEL= AY; - - ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), - UB960_IR_RX_ANA_STROBE_SET_CLK, clk_delay, &ret); - - ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), - UB960_IR_RX_ANA_STROBE_SET_DATA, data_delay, &ret); + if (priv->hw_data->chip_type =3D=3D UB954) { + u8 clk_data_delay; + + clk_data_delay =3D UB954_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY | + UB954_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY; + + if (strobe_pos < UB960_MIN_AEQ_STROBE_POS) + clk_data_delay =3D abs(strobe_pos) - UB960_MANUAL_STROBE_EXTRA_DELAY; + else if (strobe_pos > UB960_MAX_AEQ_STROBE_POS) + clk_data_delay =3D (strobe_pos - UB960_MANUAL_STROBE_EXTRA_DELAY) << + UB954_IR_RX_ANA_STROBE_SET_DATA_DELAY_SHIFT; + else if (strobe_pos < 0) + clk_data_delay =3D abs(strobe_pos) | + UB954_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY; + else if (strobe_pos > 0) + clk_data_delay =3D (strobe_pos | + UB954_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY) << + UB954_IR_RX_ANA_STROBE_SET_DATA_DELAY_SHIFT; + + ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), + UB954_IR_RX_ANA_STROBE_SET_CLK_DATA, clk_data_delay, &ret); + } else { + u8 clk_delay, data_delay; + + clk_delay =3D UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY; + data_delay =3D UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY; + + if (strobe_pos < UB960_MIN_AEQ_STROBE_POS) + clk_delay =3D abs(strobe_pos) - UB960_MANUAL_STROBE_EXTRA_DELAY; + else if (strobe_pos > UB960_MAX_AEQ_STROBE_POS) + data_delay =3D strobe_pos - UB960_MANUAL_STROBE_EXTRA_DELAY; + else if (strobe_pos < 0) + clk_delay =3D abs(strobe_pos) | UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA= _DELAY; + else if (strobe_pos > 0) + data_delay =3D strobe_pos | UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DE= LAY; + + ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), + UB960_IR_RX_ANA_STROBE_SET_CLK, clk_delay, &ret); + ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), + UB960_IR_RX_ANA_STROBE_SET_DATA, data_delay, &ret); + } =20 return ret; } @@ -3643,7 +3692,8 @@ static int ub960_configure_ports_for_streaming(struct= ub960_data *priv, =20 case RXPORT_MODE_CSI2_SYNC: case RXPORT_MODE_CSI2_NONSYNC: - if (priv->hw_data->chip_type =3D=3D UB960) { + if (priv->hw_data->chip_type =3D=3D UB960 || + priv->hw_data->chip_type =3D=3D UB954) { /* Map all VCs from this port to the same VC */ ub960_rxport_write(priv, nport, UB960_RR_CSI_VC_MAP, (vc << UB960_RR_CSI_VC_MAP_SHIFT(3)) | @@ -4177,33 +4227,40 @@ static int ub960_log_status(struct v4l2_subdev *sd) dev_info(dev, "\tsync %u, pass %u\n", v & (u8)BIT(1), v & (u8)BIT(0)); =20 - ret =3D ub960_read16(priv, UB960_SR_CSI_FRAME_COUNT_HI(nport), - &v16, NULL); - if (ret) - return ret; + /* + * Frame counter, frame error counter, line counter and line error count= er + * registers are marked as reserved in the UB954 datasheet. Hence restri= ct + * the following register reads only for UB960 and UB9702. + */ + if (priv->hw_data->chip_type =3D=3D UB960 || priv->hw_data->chip_type = =3D=3D UB9702) { + ret =3D ub960_read16(priv, UB960_SR_CSI_FRAME_COUNT_HI(nport), + &v16, NULL); + if (ret) + return ret; =20 - dev_info(dev, "\tframe counter %u\n", v16); + dev_info(dev, "\tframe counter %u\n", v16); =20 - ret =3D ub960_read16(priv, UB960_SR_CSI_FRAME_ERR_COUNT_HI(nport), - &v16, NULL); - if (ret) - return ret; + ret =3D ub960_read16(priv, UB960_SR_CSI_FRAME_ERR_COUNT_HI(nport), + &v16, NULL); + if (ret) + return ret; =20 - dev_info(dev, "\tframe error counter %u\n", v16); + dev_info(dev, "\tframe error counter %u\n", v16); =20 - ret =3D ub960_read16(priv, UB960_SR_CSI_LINE_COUNT_HI(nport), - &v16, NULL); - if (ret) - return ret; + ret =3D ub960_read16(priv, UB960_SR_CSI_LINE_COUNT_HI(nport), + &v16, NULL); + if (ret) + return ret; =20 - dev_info(dev, "\tline counter %u\n", v16); + dev_info(dev, "\tline counter %u\n", v16); =20 - ret =3D ub960_read16(priv, UB960_SR_CSI_LINE_ERR_COUNT_HI(nport), - &v16, NULL); - if (ret) - return ret; + ret =3D ub960_read16(priv, UB960_SR_CSI_LINE_ERR_COUNT_HI(nport), + &v16, NULL); + if (ret) + return ret; =20 - dev_info(dev, "\tline error counter %u\n", v16); + dev_info(dev, "\tline error counter %u\n", v16); + } } =20 for_each_rxport(priv, it) { @@ -4269,7 +4326,7 @@ static int ub960_log_status(struct v4l2_subdev *sd) =20 dev_info(dev, "\tcsi_err_counter %u\n", v); =20 - if (priv->hw_data->chip_type =3D=3D UB960) { + if (priv->hw_data->chip_type =3D=3D UB960 || priv->hw_data->chip_type = =3D=3D UB954) { ret =3D ub960_log_status_ub960_sp_eq(priv, nport); if (ret) return ret; @@ -5029,6 +5086,11 @@ static int ub960_enable_core_hw(struct ub960_data *p= riv) if (ret) goto err_pd_gpio; =20 + /* + * UB954 REFCLK_FREQ is not synchronized, so multiple reads are recommend= ed + * by the datasheet. However, a single read is practically seen to be + * sufficient and moreover it is only used for a debug print. + */ if (priv->hw_data->chip_type =3D=3D UB9702) ret =3D ub960_read(priv, UB9702_SR_REFCLK_FREQ, &refclk_freq, NULL); @@ -5188,6 +5250,14 @@ static void ub960_remove(struct i2c_client *client) mutex_destroy(&priv->reg_lock); } =20 +static const struct ub960_hw_data ds90ub954_hw =3D { + .model =3D "ub954", + .chip_type =3D UB954, + .chip_family =3D FAMILY_FPD3, + .num_rxports =3D 2, + .num_txports =3D 1, +}; + static const struct ub960_hw_data ds90ub960_hw =3D { .model =3D "ub960", .chip_type =3D UB960, @@ -5205,6 +5275,7 @@ static const struct ub960_hw_data ds90ub9702_hw =3D { }; =20 static const struct i2c_device_id ub960_id[] =3D { + { "ds90ub954-q1", (kernel_ulong_t)&ds90ub954_hw }, { "ds90ub960-q1", (kernel_ulong_t)&ds90ub960_hw }, { "ds90ub9702-q1", (kernel_ulong_t)&ds90ub9702_hw }, {} @@ -5212,6 +5283,7 @@ static const struct i2c_device_id ub960_id[] =3D { MODULE_DEVICE_TABLE(i2c, ub960_id); =20 static const struct of_device_id ub960_dt_ids[] =3D { + { .compatible =3D "ti,ds90ub954-q1", .data =3D &ds90ub954_hw }, { .compatible =3D "ti,ds90ub960-q1", .data =3D &ds90ub960_hw }, { .compatible =3D "ti,ds90ub9702-q1", .data =3D &ds90ub9702_hw }, {} --=20 2.34.1