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(unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id 2A46D3F7082; Tue, 24 Feb 2026 00:01:35 -0800 (PST) From: Ratheesh Kannoth To: , CC: , , , , , , "Ratheesh Kannoth" Subject: [PATCH net-next v9 12/13] octeontx2-af: npc: cn20k: add debugfs support Date: Tue, 24 Feb 2026 13:30:08 +0530 Message-ID: <20260224080009.4147301-13-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260224080009.4147301-1-rkannoth@marvell.com> References: <20260224080009.4147301-1-rkannoth@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=P7Y3RyAu c=1 sm=1 tr=0 ts=699d5ae5 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=TtqV-g6YmW1Jfm2GSLaY:22 a=M5GUcnROAAAA:8 a=VlSHqinqd2IHOLuXnyEA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-ORIG-GUID: KqFunog52IDyJIRg_BKAw8cS6g8YiOL_ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjI0MDA2OCBTYWx0ZWRfX5QqjXdaouj43 +1YzzaOo5tKE0xNjcdzpRFbPwMpV5VMuzbUc/COzDIu7CIZ/0/6rh9DFZfdtyxTO1Loa9VpF8pj +bto1jd//ztyTUCJzlTH8OcHEakOrF4nMFx/m4zDPpCEMr10+AhSNYHYrC5EX0mKHrhjPmjWKHA AijFGdr+PRwxuAyD4sUo0aCRiLy9gA9cmzJtOZSKPs2yjoEVAuAPTHt35cCgxx/n1zIKLAn0eSk 0zDm1CEVihzBKMwFPL0290iTdtoSTp9mefrDPRG/hLkpBHVZ/YjsBuTSPm6cYXNXiTFvMiEGbaP Z1UcifABWKgNFJIyLiaSLAppfTgXacpi51dipnvr8lweWtBehxYqoRGErcQYSTJkFBv7q3qVN1Q 2AWiDuIKY8TEuL7/c5LeNirLvw7KicH3GLauz3pXmeLQzlBiyJ98h4XOcmi1TWsfx7aUeE9yxNL ZurO4757DwjSe2odGXA== X-Proofpoint-GUID: KqFunog52IDyJIRg_BKAw8cS6g8YiOL_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-24_01,2026-02-23_03,2025-10-01_01 Content-Type: text/plain; charset="utf-8" CN20K silicon divides the NPC MCAM into banks and subbanks, with each subbank configurable for x2 or x4 key widths. This patch adds debugfs entries to expose subbank usage details and their configured key type. A debugfs entry is also added to display the default MCAM indexes allocated for each pcifunc. Additionally, debugfs support is introduced to show the mapping between virtual indexes and real MCAM indexes, and vice versa. Signed-off-by: Ratheesh Kannoth --- .../marvell/octeontx2/af/cn20k/debugfs.c | 261 ++++++++++++++++++ .../marvell/octeontx2/af/rvu_debugfs.c | 41 ++- 2 files changed, 292 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.c b/dr= ivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.c index 0ba123be6643..3debf2fae1a4 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.c @@ -15,8 +15,269 @@ #include "debugfs.h" #include "cn20k/npc.h" =20 +static int npc_mcam_layout_show(struct seq_file *s, void *unused) +{ + int i, j, sbd, idx0, idx1, vidx0, vidx1; + struct npc_priv_t *npc_priv; + char buf0[32], buf1[32]; + struct npc_subbank *sb; + unsigned int bw0, bw1; + bool v0, v1; + int pf1, pf2; + bool e0, e1; + void *map; + + npc_priv =3D s->private; + + sbd =3D npc_priv->subbank_depth; + + for (i =3D npc_priv->num_subbanks - 1; i >=3D 0; i--) { + sb =3D &npc_priv->sb[i]; + mutex_lock(&sb->lock); + + if (sb->flags & NPC_SUBBANK_FLAG_FREE) + goto next; + + bw0 =3D bitmap_weight(sb->b0map, npc_priv->subbank_depth); + if (sb->key_type =3D=3D NPC_MCAM_KEY_X4) { + seq_printf(s, "\n\nsubbank:%u, x4, free=3D%u, used=3D%u\n", + sb->idx, sb->free_cnt, bw0); + + for (j =3D sbd - 1; j >=3D 0; j--) { + if (!test_bit(j, sb->b0map)) + continue; + + idx0 =3D sb->b0b + j; + map =3D xa_load(&npc_priv->xa_idx2pf_map, idx0); + pf1 =3D xa_to_value(map); + + map =3D xa_load(&npc_priv->xa_idx2vidx_map, idx0); + if (map) { + vidx0 =3D xa_to_value(map); + snprintf(buf0, sizeof(buf0), + "v:%u", vidx0); + } + + seq_printf(s, "\t%u(%#x) %s\n", idx0, pf1, + map ? buf0 : " "); + } + goto next; + } + + bw1 =3D bitmap_weight(sb->b1map, npc_priv->subbank_depth); + seq_printf(s, "\n\nsubbank:%u, x2, free=3D%u, used=3D%u\n", + sb->idx, sb->free_cnt, bw0 + bw1); + seq_printf(s, "bank1(%u)\t\tbank0(%u)\n", bw1, bw0); + + for (j =3D sbd - 1; j >=3D 0; j--) { + e0 =3D test_bit(j, sb->b0map); + e1 =3D test_bit(j, sb->b1map); + + if (!e1 && !e0) + continue; + + if (e1 && e0) { + idx0 =3D sb->b0b + j; + map =3D xa_load(&npc_priv->xa_idx2pf_map, idx0); + pf1 =3D xa_to_value(map); + + map =3D xa_load(&npc_priv->xa_idx2vidx_map, idx0); + v0 =3D !!map; + if (v0) { + vidx0 =3D xa_to_value(map); + snprintf(buf0, sizeof(buf0), "v:%05u", + vidx0); + } + + idx1 =3D sb->b1b + j; + map =3D xa_load(&npc_priv->xa_idx2pf_map, idx1); + pf2 =3D xa_to_value(map); + + map =3D xa_load(&npc_priv->xa_idx2vidx_map, idx1); + v1 =3D !!map; + if (v1) { + vidx1 =3D xa_to_value(map); + snprintf(buf1, sizeof(buf1), "v:%05u", + vidx1); + } + + seq_printf(s, "%05u(%#x) %s\t\t%05u(%#x) %s\n", + idx1, pf2, v1 ? buf1 : " ", + idx0, pf1, v0 ? buf0 : " "); + + continue; + } + + if (e0) { + idx0 =3D sb->b0b + j; + map =3D xa_load(&npc_priv->xa_idx2pf_map, idx0); + pf1 =3D xa_to_value(map); + + map =3D xa_load(&npc_priv->xa_idx2vidx_map, idx0); + if (map) { + vidx0 =3D xa_to_value(map); + snprintf(buf0, sizeof(buf0), "v:%05u", + vidx0); + } + + seq_printf(s, "\t\t \t\t%05u(%#x) %s\n", idx0, + pf1, map ? buf0 : " "); + continue; + } + + idx1 =3D sb->b1b + j; + map =3D xa_load(&npc_priv->xa_idx2pf_map, idx1); + pf1 =3D xa_to_value(map); + map =3D xa_load(&npc_priv->xa_idx2vidx_map, idx1); + if (map) { + vidx1 =3D xa_to_value(map); + snprintf(buf1, sizeof(buf1), "v:%05u", vidx1); + } + + seq_printf(s, "%05u(%#x) %s\n", idx1, pf1, + map ? buf1 : " "); + } +next: + mutex_unlock(&sb->lock); + } + return 0; +} + +DEFINE_SHOW_ATTRIBUTE(npc_mcam_layout); + +static int npc_mcam_default_show(struct seq_file *s, void *unused) +{ + struct npc_priv_t *npc_priv; + unsigned long index; + u16 ptr[4], pcifunc; + struct rvu *rvu; + int rc, i; + void *map; + + npc_priv =3D npc_priv_get(); + rvu =3D s->private; + + seq_puts(s, "\npcifunc\tBcast\tmcast\tpromisc\tucast\n"); + + xa_for_each(&npc_priv->xa_pf_map, index, map) { + pcifunc =3D index; + + for (i =3D 0; i < ARRAY_SIZE(ptr); i++) + ptr[i] =3D USHRT_MAX; + + rc =3D npc_cn20k_dft_rules_idx_get(rvu, pcifunc, &ptr[0], + &ptr[1], &ptr[2], &ptr[3]); + if (rc) + continue; + + seq_printf(s, "%#x\t", pcifunc); + for (i =3D 0; i < ARRAY_SIZE(ptr); i++) { + if (ptr[i] !=3D USHRT_MAX) + seq_printf(s, "%u\t", ptr[i]); + else + seq_puts(s, "\t"); + } + seq_puts(s, "\n"); + } + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(npc_mcam_default); + +static int npc_vidx2idx_map_show(struct seq_file *s, void *unused) +{ + struct npc_priv_t *npc_priv; + unsigned long index, start; + struct xarray *xa; + void *map; + + npc_priv =3D s->private; + start =3D npc_priv->bank_depth * 2; + xa =3D &npc_priv->xa_vidx2idx_map; + + seq_puts(s, "\nvidx\tmcam_idx\n"); + + xa_for_each_start(xa, index, map, start) + seq_printf(s, "%lu\t%lu\n", index, xa_to_value(map)); + return 0; +} +DEFINE_SHOW_ATTRIBUTE(npc_vidx2idx_map); + +static int npc_idx2vidx_map_show(struct seq_file *s, void *unused) +{ + struct npc_priv_t *npc_priv; + unsigned long index; + struct xarray *xa; + void *map; + + npc_priv =3D s->private; + xa =3D &npc_priv->xa_idx2vidx_map; + + seq_puts(s, "\nmidx\tvidx\n"); + + xa_for_each(xa, index, map) + seq_printf(s, "%lu\t%lu\n", index, xa_to_value(map)); + return 0; +} +DEFINE_SHOW_ATTRIBUTE(npc_idx2vidx_map); + +static int npc_defrag_show(struct seq_file *s, void *unused) +{ + struct npc_defrag_show_node *node; + struct npc_priv_t *npc_priv; + u16 sbd, bdm; + + npc_priv =3D s->private; + bdm =3D npc_priv->bank_depth - 1; + sbd =3D npc_priv->subbank_depth; + + seq_puts(s, "\nold(sb) -> new(sb)\t\tvidx\n"); + + mutex_lock(&npc_priv->lock); + list_for_each_entry(node, &npc_priv->defrag_lh, list) + seq_printf(s, "%u(%u)\t%u(%u)\t%u\n", node->old_midx, + (node->old_midx & bdm) / sbd, + node->new_midx, + (node->new_midx & bdm) / sbd, + node->vidx); + mutex_unlock(&npc_priv->lock); + return 0; +} + +DEFINE_SHOW_ATTRIBUTE(npc_defrag); + int npc_cn20k_debugfs_init(struct rvu *rvu) { + struct npc_priv_t *npc_priv =3D npc_priv_get(); + struct dentry *npc_dentry; + + npc_dentry =3D debugfs_create_file("mcam_layout", 0444, rvu->rvu_dbg.npc, + npc_priv, &npc_mcam_layout_fops); + + if (!npc_dentry) + return -EFAULT; + + npc_dentry =3D debugfs_create_file("mcam_default", 0444, rvu->rvu_dbg.npc, + rvu, &npc_mcam_default_fops); + + if (!npc_dentry) + return -EFAULT; + + npc_dentry =3D debugfs_create_file("vidx2idx", 0444, rvu->rvu_dbg.npc, + npc_priv, &npc_vidx2idx_map_fops); + if (!npc_dentry) + return -EFAULT; + + npc_dentry =3D debugfs_create_file("idx2vidx", 0444, rvu->rvu_dbg.npc, + npc_priv, &npc_idx2vidx_map_fops); + if (!npc_dentry) + return -EFAULT; + + npc_dentry =3D debugfs_create_file("defrag", 0444, rvu->rvu_dbg.npc, + npc_priv, &npc_defrag_fops); + if (!npc_dentry) + return -EFAULT; + return 0; } =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c b/driv= ers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c index 620724dad093..413f9fa40b33 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c @@ -23,6 +23,7 @@ =20 #include "cn20k/reg.h" #include "cn20k/debugfs.h" +#include "cn20k/npc.h" =20 #define DEBUGFS_DIR_NAME "octeontx2" =20 @@ -3197,7 +3198,9 @@ static void rvu_print_npc_mcam_info(struct seq_file *= s, static int rvu_dbg_npc_mcam_info_display(struct seq_file *filp, void *unsu= ed) { struct rvu *rvu =3D filp->private; + int x4_free, x2_free, sb_free; int pf, vf, numvfs, blkaddr; + struct npc_priv_t *npc_priv; struct npc_mcam *mcam; u16 pcifunc, counters; u64 cfg; @@ -3211,16 +3214,34 @@ static int rvu_dbg_npc_mcam_info_display(struct seq= _file *filp, void *unsued) =20 seq_puts(filp, "\nNPC MCAM info:\n"); /* MCAM keywidth on receive and transmit sides */ - cfg =3D rvu_read64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(NIX_INTF_RX)); - cfg =3D (cfg >> 32) & 0x07; - seq_printf(filp, "\t\t RX keywidth \t: %s\n", (cfg =3D=3D NPC_MCAM_KEY_X1= ) ? - "112bits" : ((cfg =3D=3D NPC_MCAM_KEY_X2) ? - "224bits" : "448bits")); - cfg =3D rvu_read64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(NIX_INTF_TX)); - cfg =3D (cfg >> 32) & 0x07; - seq_printf(filp, "\t\t TX keywidth \t: %s\n", (cfg =3D=3D NPC_MCAM_KEY_X1= ) ? - "112bits" : ((cfg =3D=3D NPC_MCAM_KEY_X2) ? - "224bits" : "448bits")); + if (is_cn20k(rvu->pdev)) { + npc_priv =3D npc_priv_get(); + seq_printf(filp, "\t\t RX keywidth \t: %s\n", + (npc_priv->kw =3D=3D NPC_MCAM_KEY_X1) ? + "256bits" : "512bits"); + + npc_cn20k_subbank_calc_free(rvu, &x2_free, &x4_free, &sb_free); + seq_printf(filp, "\t\t free x4 slots\t: %d\n", x4_free); + + seq_printf(filp, "\t\t free x2 slots\t: %d\n", x2_free); + + seq_printf(filp, "\t\t free subbanks\t: %d\n", sb_free); + } else { + cfg =3D rvu_read64(rvu, blkaddr, + NPC_AF_INTFX_KEX_CFG(NIX_INTF_RX)); + cfg =3D (cfg >> 32) & 0x07; + seq_printf(filp, "\t\t RX keywidth \t: %s\n", + (cfg =3D=3D NPC_MCAM_KEY_X1) ? + "112bits" : ((cfg =3D=3D NPC_MCAM_KEY_X2) ? + "224bits" : "448bits")); + cfg =3D rvu_read64(rvu, blkaddr, + NPC_AF_INTFX_KEX_CFG(NIX_INTF_TX)); + cfg =3D (cfg >> 32) & 0x07; + seq_printf(filp, "\t\t TX keywidth \t: %s\n", + (cfg =3D=3D NPC_MCAM_KEY_X1) ? + "112bits" : ((cfg =3D=3D NPC_MCAM_KEY_X2) ? + "224bits" : "448bits")); + } =20 mutex_lock(&mcam->lock); /* MCAM entries */ --=20 2.43.0