From nobody Sun Apr 5 19:42:18 2026 Received: from mail-qv1-f46.google.com (mail-qv1-f46.google.com [209.85.219.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 439E72343BE for ; Tue, 24 Feb 2026 02:38:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771900705; cv=none; b=jha/dmHArs+fCEdbbG9WIwBkRZdUWV57Wnj1oT/6IT1kLpi8Bybld1Dh96LCBSvAwwVXed9fxJN7X35rXqsCQv/FZZv6entrC9PAWOtsaN/rsACVJCZtCeIdn7EBExL8Ssqf2acL8CTzWvZlXkPK+mwjSJqRy07GFbIG6AiV6CA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771900705; c=relaxed/simple; bh=fn2u73mBSTbAd/EdpQfH9E2MCEctzADYuwz366K+YQY=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=goyDP5kpbsF522gN3JtN9z71dRUUSHyF2b50KKoWu97diVFbo3CghPWk2D5lTpfWRZrNLiw/imkUq9LyxA/bl/bFwzuY4O8l6pidaWboqnpsxxqvF6LLqyQiEJvaYEUg2k2yX+WPtBJGMgKdTry2MiWd2zfFp9w19B57+GkccQw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=jst2vhew; arc=none smtp.client-ip=209.85.219.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jst2vhew" Received: by mail-qv1-f46.google.com with SMTP id 6a1803df08f44-8947404b367so59186566d6.3 for ; Mon, 23 Feb 2026 18:38:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1771900702; x=1772505502; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=uHi4kGutlHIiCP5G7IafBayijdH0c6FDLs2gsnvP6Rc=; b=jst2vhewThOnLiMiXBgE4suG6tMMKaYmHbaDifof2ujJzbh9QS3pNJjIckoULbXkLN Ax6INe+0l4GDsvJIAtSrbV9Dl1xC7m7gMtyJkI8aOLeIgbBovVI+LwIZuptnYQ/g7BG5 Hvr61z1eJ0KujUToVGylGWe34R+mNIjN3XlIQLfe/UnelW0jctstp69cJ+SKlU2soneK XEvWNFOAIu66JfvrkmrjJglOl1llSHocTesJHNsFqxJ6/Guwnm0iyaYwsQI020Tx3hTR h92V4LSZ6LwH6x+13qyaEPeFcb5MINDSHdWQ73m4dsODsblMmVKm6b7HyZ7dP7kQasCv KfbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771900702; x=1772505502; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=uHi4kGutlHIiCP5G7IafBayijdH0c6FDLs2gsnvP6Rc=; b=KOK91o3M2HO7F76jDE6iQ6mn4Ai1KWsp3lyrEYtR0Kfy2NlmqoFXkyxluLeoLjmXi7 29ihvXY/YqaAch9livZP4J7zJBzxr5ES2Zh83QQVyKvTfQwfT1kgwggJDQ53rdWpdHu1 2MTlrSw6FuhckZ1SMvvbGHO4cp24pzxnqWRJoPS5ADGyHW3mPSjeHwmcvFxVn7e4lzsH tYNrd2WkSyoLe2/kmrckXGi61zo0GJkqyyP+UIsQwWq1rumJZol8if77tsm3CjE3z2SD 9vk7YGzzb0YxwII29QCEjy2Jm+ThoaCXEkoDgZq7H/Gd02knYOpaLK+1Fj8YeySv6OAS UvZw== X-Forwarded-Encrypted: i=1; AJvYcCVC7tlMRYkwRiCix/m2QtZiM+M/sYkHwRft/cNdtCIZfSVfeR701mMcMZQJ4ljQoUl9pCpey7zre0MEo/8=@vger.kernel.org X-Gm-Message-State: AOJu0YwtVcQq+26XHyEyel7pYp1rD3594I4e7DNMOaf7T5zkzYP3uzvX V3iyccVspk4EALRArcTpgN1OESVr5nRMo8nPU8OOGBCZ9AlNHbpT2mgRsRxuCg== X-Gm-Gg: ATEYQzx0SegjyOvsnuxb34LbVRYfmVTM1spyEV7Ng7C/peAkmGtF6C5466zLN+bIru5 khwt7S46YP+Nr9qVOpQ4FbsU1yssOXpdtOkkvo38Wq2n72qQkoZSkhoDISNHsjV/0STF8pRlaBd yGNFNt6mK28jWcZfKWCpemtuWI5/0AIgP7nOcoki3XSItAr31EsOlvWVfTo6F6KOqq2DUuTolYU msuiRB/AUKMx5S6QtFn0NBfIYSSLfhO3l8Le/+q8YZXiLo8Tdwo7nha7UedhPxxlLpQB9N7IwoO zt7qaBS7cPbulDXYwArImHUUspp6beeDsD7x2uRp+fPQVd9alCL4HaHdnAkiUvV9k3k3coqKCwv EaW8hX4/RrzUoblihi5E1ygYxh5OaSR/PiGWCMc8xb/5VydjaKX4qJaipuxM4FR3oX5ZLpJGebf 9dAPTs/UI8yV33uuZbm3wcZZBhj4Qw2WDhtCHIbDxYJRYpVDLuE0hFpX9LcY9jFky43Bn4yLsBW d8= X-Received: by 2002:ad4:5942:0:b0:895:5dd:3d48 with SMTP id 6a1803df08f44-89979d85395mr168711276d6.59.1771900702162; Mon, 23 Feb 2026 18:38:22 -0800 (PST) Received: from localhost.localdomain (modemcable231.2-131-66.mc.videotron.ca. [66.131.2.231]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8997c691243sm82072666d6.3.2026.02.23.18.38.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Feb 2026 18:38:21 -0800 (PST) From: Serhii Pievniev To: lenb@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Serhii Pievniev Subject: [PATCH] tools/turbostat: fix microcode patch level reading for AMD/Hygon Date: Mon, 23 Feb 2026 21:37:19 -0500 Message-ID: <20260224023719.65165-1-spevnev16@gmail.com> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" turbostat always used the same logic to read the microcode patch level, which is correct for Intel but not for AMD/Hygon. While Intel stores the patch level in the upper 32 bits of MSR, AMD stores it in the lower 32 bits, which previously caused turbostat to report the microcode version as 0x0 on AMD/Hygon. Split the logic into two paths, using upper bits of MSR_IA32_UCODE_REV for Intel and lower bits of MSR_AMD64_PATCH_LEVEL for AMD/Hygon. Although both MSRs share the same address (0x8b), separate constants make this semantic difference explicit. Signed-off-by: Serhii Pievniev --- tools/power/x86/turbostat/turbostat.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbos= tat/turbostat.c index 1a2671c2820..2698ac89376 100644 --- a/tools/power/x86/turbostat/turbostat.c +++ b/tools/power/x86/turbostat/turbostat.c @@ -9122,10 +9122,21 @@ void process_cpuid() cpuid_has_hv =3D ecx_flags & (1 << 31); =20 if (!no_msr) { - if (get_msr(sched_getcpu(), MSR_IA32_UCODE_REV, &ucode_patch)) - warnx("get_msr(UCODE)"); - else - ucode_patch_valid =3D true; + if (authentic_amd || hygon_genuine) { + if (get_msr(sched_getcpu(), MSR_AMD64_PATCH_LEVEL, &ucode_patch)) { + warnx("get_msr(UCODE)"); + } else { + ucode_patch_valid =3D true; + ucode_patch &=3D 0xFFFFFFFF; + } + } else { + if (get_msr(sched_getcpu(), MSR_IA32_UCODE_REV, &ucode_patch)) { + warnx("get_msr(UCODE)"); + } else { + ucode_patch_valid =3D true; + ucode_patch =3D (ucode_patch >> 32) & 0xFFFFFFFF; + } + } } =20 /* @@ -9139,7 +9150,7 @@ void process_cpuid() if (!quiet) { fprintf(outf, "CPUID(1): family:model:stepping 0x%x:%x:%x (%d:%d:%d)", f= amily, model, stepping, family, model, stepping); if (ucode_patch_valid) - fprintf(outf, " microcode 0x%x", (unsigned int)((ucode_patch >> 32) & 0= xFFFFFFFF)); + fprintf(outf, " microcode 0x%llx", ucode_patch); fputc('\n', outf); =20 fprintf(outf, "CPUID(0x80000000): max_extended_levels: 0x%x\n", max_exte= nded_level); --=20 2.53.0