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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7d52d038dcdsm11711730a34.16.2026.02.24.23.20.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Feb 2026 23:20:34 -0800 (PST) From: Jingyi Wang Date: Tue, 24 Feb 2026 23:19:24 -0800 Subject: [PATCH v6 09/10] arm64: dts: qcom: kaanapali: Add support for MM clock controllers for Kaanapali Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260224-knp-dts-misc-v6-9-79d20dab8a60@oss.qualcomm.com> References: <20260224-knp-dts-misc-v6-0-79d20dab8a60@oss.qualcomm.com> In-Reply-To: <20260224-knp-dts-misc-v6-0-79d20dab8a60@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jingyi Wang , 20260114-knp-remoteproc-v4-0-fcf0b04d01af@oss.qualcomm.com, Taniya Das , Konrad Dybcio , Abel Vesa X-Mailer: b4 0.15-dev-3d134 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772004019; l=4559; i=jingyi.wang@oss.qualcomm.com; s=20250911; h=from:subject:message-id; bh=nsYZEEXXsjI4so4Na/T/SEdJ96D+J8BKnk0ZTfIBIXw=; b=TfBj9DIkEMRmRuI40yrrnUVy+NrYGVadVDZypwl6ydfXxa2XvshFnFd9tvliq5LH+/qhJ8rRJ 4oVnng1P/ZeDPdi16Pxp5Q2X/iEQb5w3ajdaY3tIhrnozPy6TMPs0w7 X-Developer-Key: i=jingyi.wang@oss.qualcomm.com; a=ed25519; pk=PSoHZ6KbUss3IW8FPRVMHMK0Jkkr/jV347mBYJO3iLo= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjI1MDA3MCBTYWx0ZWRfX1ad8a1gLe8+Q T5uk9G0tVrLmUJ0sY0Sh/ueKs+hb1loBQJUWT0yR7FywsY5b0UtyGVOgUNvP4orts2UUF1lzmjF izmampjKy7yDa7iHqyqBQdvOhmNc+l1DagWEx4/Nxi+A0HYPfjbDym1jw52glf4VtWbOYyOmLmX BjLW+IqULFiLCw6F+k/crFDQA5HZmqERLOAKbTpAtPhAix7qY+N9zIXut5lIRNipJYy3ptij0FX nZPf4YFMxJOl1kl4tZ5xcVk2cvOrUMFtg1C/V9J4C6hDgODpHyI0P82q6ciJ8YUgXjUbUHklXYg WP6J/wpU00LtwulaV8TP6BNYMv5rtCuTwsrxxknijmYfUfPCqP8AbTFeiyP9ziyhctNvX8+Lp4z pZadRR6rCy0Jcj0A7zlEfeVLXav0FjSbCskBL7h/nYFv+LFXvqKigQ1y/b7nMoVqxeBFSit8iXu 1Pf38yxEso0P46H9nxA== X-Proofpoint-ORIG-GUID: 0zNvjm2PI1lYCWGioakMdvtIdrLzrLzD X-Authority-Analysis: v=2.4 cv=Ro7I7SmK c=1 sm=1 tr=0 ts=699ea2c4 cx=c_pps a=7uPEO8VhqeOX8vTJ3z8K6Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=Y3HLYP14RHR0fgYgac8A:9 a=QEXdDO2ut3YA:10 a=EXS-LbY8YePsIyqnH6vw:22 X-Proofpoint-GUID: 0zNvjm2PI1lYCWGioakMdvtIdrLzrLzD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-24_03,2026-02-23_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 spamscore=0 bulkscore=0 adultscore=0 impostorscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602250070 From: Taniya Das Add the device nodes for the multimedia clock controllers (cambistmclkcc, camcc, dispcc, videocc, gpucc and gxclkctl). Signed-off-by: Taniya Das Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 111 ++++++++++++++++++++++++++++= ++++ 1 file changed, 111 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/= qcom/kaanapali.dtsi index d9880a87a928..54d6c235e1b1 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -3,7 +3,13 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 +#include +#include +#include #include +#include +#include +#include #include #include #include @@ -1557,6 +1563,24 @@ aggre_noc: interconnect@16e0000 { <&rpmhcc RPMH_IPA_CLK>; }; =20 + cambistmclkcc: clock-controller@1760000 { + compatible =3D "qcom,kaanapali-cambistmclkcc"; + reg =3D <0x0 0x01760000 0x0 0x8000>; + + clocks =3D <&gcc GCC_CAM_BIST_MCLK_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MX>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + mmss_noc: interconnect@1780000 { compatible =3D "qcom,kaanapali-mmss-noc"; reg =3D <0x0 0x01780000 0x0 0x5b800>; @@ -2532,6 +2556,46 @@ tcsr: clock-controller@1fc0000 { #reset-cells =3D <1>; }; =20 + videocc: clock-controller@20f0000 { + compatible =3D "qcom,kaanapali-videocc"; + reg =3D <0x0 0x020f0000 0x0 0x10000>; + clocks =3D <&bi_tcxo_div2>, + <&gcc GCC_VIDEO_AHB_CLK>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + gxclkctl: clock-controller@3d64000 { + compatible =3D "qcom,kaanapali-gxclkctl"; + reg =3D <0x0 0x03d64000 0x0 0x6000>; + + power-domains =3D <&rpmhpd RPMHPD_GFX>, + <&rpmhpd RPMHPD_GMXC>, + <&gpucc GPU_CC_CX_GDSC>; + + #power-domain-cells =3D <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible =3D "qcom,kaanapali-gpucc"; + reg =3D <0x0 0x03d90000 0x0 0x9800>; + + clocks =3D <&bi_tcxo_div2>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + remoteproc_adsp: remoteproc@6800000 { compatible =3D "qcom,kaanapali-adsp-pas", "qcom,sm8550-adsp-pas"; reg =3D <0x0 0x06800000 0x0 0x10000>; @@ -3073,6 +3137,53 @@ opp-202000000 { }; }; =20 + camcc: clock-controller@956d000 { + compatible =3D "qcom,kaanapali-camcc"; + reg =3D <0x0 0x0956d000 0x0 0x80000>; + + clocks =3D <&gcc GCC_CAMERA_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + dispcc: clock-controller@9ba2000 { + compatible =3D "qcom,kaanapali-dispcc"; + reg =3D <0x0 0x09ba2000 0x0 0x20000>; + clocks =3D <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + + #clock-cells =3D <1>; + #power-domain-cells =3D <1>; + #reset-cells =3D <1>; + }; + pdc: interrupt-controller@b220000 { compatible =3D "qcom,kaanapali-pdc", "qcom,pdc"; reg =3D <0x0 0x0b220000 0x0 0x10000>, --=20 2.25.1