From nobody Thu Apr 2 07:43:57 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6292D2F290A for ; Wed, 25 Feb 2026 07:20:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772004027; cv=none; b=Yo5X9au+uS808JpWhB4MPLLjUmZ7j5j6by+8HK3JuqDoJTN4TGBr61AT0M3bAKeUjNF/zuO/0RYn4GcVohgQcInBb+zKJXJyn7jokyH6GZcZcVgGR2Dv7pKhl+VQnztqPz1Qg8udKnmhwMATRCkcykWEX7l+A5lNdR69txmdryg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772004027; c=relaxed/simple; bh=kis3v3C4nt56BQx6xUh4uIxkHwEc/Uiuo+OqAzr1aDA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FjT+zwgwZfo8QpZMWUxgbXuw6kBHy13UHc9QDMqu0pV67T8FtYVgnAEsgV8SkXKepADTAItSWvOR+UQXKmnKD/mUWrwmr4ZCEoFvseY0nOTw5k/PyMDHjtgf7TVcyPyjAoHUn7xnlVeDCRwhERsNNGiHLWsFhl7+aO8w+UQAwwA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=h4yuxfm9; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=Fvl7sCHS; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="h4yuxfm9"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="Fvl7sCHS" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 61P2TPrf583293 for ; Wed, 25 Feb 2026 07:20:24 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= kE1rjB/lsvoFa7tCLLzzkKUQ38cbbk46rGHBjoQOA5s=; b=h4yuxfm9RscZCyMA hYQzKoe53cXOd2+rTKcYVZjyZ3D09Fbr+WdaDmuaOngN7HLwSI0de/3ctw9d6NtL GSbP+cjsL+rh3hYo23XDycd1PdWSeuIdLhyceXUSf4gNpmg14l5lG/DUfeJC+gAr EmdC80sMCzpUOfIOO/L+kajaIz+qBBcyJ7owFvJDXCpqeMv4858R15Qt1xpTP7a2 aQrG29NrjzXqkqtk3GkujiyaHWHnS/jGMDdaMc6rm1JAxmycHg7XhsojToJhuErt nKniGnGCFIVuQ4WOZaM5ZsTRM9LFhywCdZoJFYKHp5hn+UXPhlIGJ9lZK1SlY0jT wAdvzg== Received: from mail-ot1-f71.google.com (mail-ot1-f71.google.com [209.85.210.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4chg2gt9pm-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 25 Feb 2026 07:20:24 +0000 (GMT) Received: by mail-ot1-f71.google.com with SMTP id 46e09a7af769-7d4cf783c73so108955362a34.3 for ; Tue, 24 Feb 2026 23:20:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1772004024; x=1772608824; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=kE1rjB/lsvoFa7tCLLzzkKUQ38cbbk46rGHBjoQOA5s=; b=Fvl7sCHS7rirs5fNg4DQZk+InAkvKFme/gNzhoodfIKaiZxawFyZM7BTrQXRte7ZNx BuOyhNoqN0Y+uDConSMxuhn/QtFCWZ6131lsOynmAZ84Zhx39PhIdNyOmBy+oJY1qMYN 4dsVvB4xvmpVnZd+8apDSVIQYVtw0Tm616mTqI8QqIOEODrYPfDU2HfxAMppvgrKFtgB y4sM92jy35FrXCT1N2Cq15tZDIp1q5n50YnlyG/N0P8x912++9RBbROw8KUknpzicIaG a6OHdKHVJjC3fF0S0wclz827LW4nnM8EUtCy7L01EodGY4YvCJhGDC+1r1gyxqOZ3YMv Q4sQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772004024; x=1772608824; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=kE1rjB/lsvoFa7tCLLzzkKUQ38cbbk46rGHBjoQOA5s=; b=SyVdqU1zu4GCW1w2ThScZJF+6kdH3IHSSHnH65Mzwp3g7EeWrwkqpoqrsDwtGvX20W FhQ0O8mGTpZ5qy3W8o1uOUouMICps1QqGpF3Ub03+NmgwVLiLym4ZPMspawZx8fQ/mzK 7VmxaI4Wj7RKK+Dd/lUcHslvoNCVQMcGJSTemccI85yx9UKIdQgCuvpqmboPDiiLIoTv dn2iTwDgVWplrC7G8qeEHhOptwInojVVtKpw131wAxZCBQI1ALf0DNgbzRVqWCrtSAFo 43AclsXkPf+oqm7I8LPoQU5T7XxG1Er8Z8M4enqFErXbEZOQ1ydZsOqNVQJjc+wK4g86 74ew== X-Forwarded-Encrypted: i=1; AJvYcCU36HO/Q2/BBY6I6PdpCoLM0McKxVJu6wibikiAQ8kxmy0dR+nL7h3YG+hh5hWSiIYCJpVsWEIyCmTcN7Y=@vger.kernel.org X-Gm-Message-State: AOJu0Yx6Dl0V3cPc5qlXK4cq8DsALgRSeWNNWAV7hKWS3jkyMr3jXXIP AKggyTOEMVkGPsOBjn0mmR7gN1neFwMc/dBzI3dhKsS7SU19yx+qi92Fy66vtVM237tec1GXpDW IfEFLtXaOhy7/vodiLfqKJHMyuHSBL81BKS6hrm/hVyRGInp8kuW7PPsiNnDEjg7RiQg= X-Gm-Gg: ATEYQzyT9pDWLqo0Qu93ep633rOpHQvx6kBCi0HcqDwdPe8HyE8XilmNDQHiKdpBJrR lByUYt5jgGcSeY55jzUrKl/x1WzHbm+m96Jd/mL9kN+qhVndJBYh60A6HjxPcjVWf+yXW19TXky 3eBroW9N7Iqd7JVy8ei+WW3SluleYhg0u+d2Pw4LzpvWZwI9ypdrJ3KY+owjvJ/8k02vz1X0Yjq f1fXdZ4SG4mf93AYK/3h6epFS1m5OIHWQTdaXYAKXI7rk5QnzaBilABjys2p3N4JO+ux1sn1klo veNuUASgRsEYgM0bUAAbNNo5dojeIcPCeQPlL1JaaJx+hW+iQJ9vhHt8Vx34xXXfE45zKyVg/PQ 3TMHeHNv2DY3ByG6fT5laNOI25YIYR1KsCliQuOaBf7QOd5h/t8GuGDTU/i6DECQLpt3AIHq9 X-Received: by 2002:a05:6830:4908:b0:7c7:3402:7d74 with SMTP id 46e09a7af769-7d52bf20168mr12269309a34.18.1772004023429; Tue, 24 Feb 2026 23:20:23 -0800 (PST) X-Received: by 2002:a05:6830:4908:b0:7c7:3402:7d74 with SMTP id 46e09a7af769-7d52bf20168mr12269292a34.18.1772004022966; Tue, 24 Feb 2026 23:20:22 -0800 (PST) Received: from hu-jingyw-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7d52d038dcdsm11711730a34.16.2026.02.24.23.20.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Feb 2026 23:20:22 -0800 (PST) From: Jingyi Wang Date: Tue, 24 Feb 2026 23:19:16 -0800 Subject: [PATCH v6 01/10] arm64: dts: qcom: kaanapali: add coresight nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260224-knp-dts-misc-v6-1-79d20dab8a60@oss.qualcomm.com> References: <20260224-knp-dts-misc-v6-0-79d20dab8a60@oss.qualcomm.com> In-Reply-To: <20260224-knp-dts-misc-v6-0-79d20dab8a60@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jingyi Wang , 20260114-knp-remoteproc-v4-0-fcf0b04d01af@oss.qualcomm.com, Jie Gan , Konrad Dybcio , Abel Vesa X-Mailer: b4 0.15-dev-3d134 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772004019; l=23499; i=jingyi.wang@oss.qualcomm.com; s=20250911; h=from:subject:message-id; bh=prYMCbFhtJWKvpHLod3UOeIGs03j5Ip2+BricOoj6iE=; b=TUysr7ZbxAEdK0o32oW1oNovLee21Sdk5VV4r/pRCtHnQZgekrzj9l0PLKF3TfZz8fOp5F9+C PmBtQvKGfnTAzfOpFYtgY173yFM+m85gUMvCrCfJQMr5kSYE/WH5dK8 X-Developer-Key: i=jingyi.wang@oss.qualcomm.com; a=ed25519; pk=PSoHZ6KbUss3IW8FPRVMHMK0Jkkr/jV347mBYJO3iLo= X-Proofpoint-ORIG-GUID: wTAO9mBE1ZhXoAEfvY5E4l15WQZg0-ae X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjI1MDA3MCBTYWx0ZWRfX81hKYTAC5FwD qN4vV4JTHik8I1z/cJGX2H/u6Lzs/EGFBs8ND+HxpN1hEn5mh69kgkxQ8+HNLMFYeb7yIqBnTIf RVTKUe0qMlUPJVB2zt2Q8CBWqhDSOX+q8kWLRcjX+j1RB/A4drPdWtmc0LpJ5IBRztnizV+Wuwq FwPk6x1RXxDlW6kCwbt3kaxflwtIfI6bCNnkgUNMRNwgKoPZZ2Xayz9f9MFpMe1aJFp6Z04yCrG eJPnyAFHwWlKVwddFzaHK+bvgR1B5naIR9uDgkdHxR9TLWj7wXEP1VVDmgQXxYASZpy9Kx/2D1u D7y1Xot8Hq2X1oikwgpxykVVANXGKrs2Z8S2VQfhjN7/ne0fw1zSZ0kTl2Jfbvz0BJa7Vz6qrQ4 uSBwFQL4deQKeDdHo9g1JQreWZA3XjPw3AIgIYy2DCasx6dnwj3adiOITBcOkDyTGrsHFBdfzR7 KInE097EuGyWzKhJWqA== X-Authority-Analysis: v=2.4 cv=ftHRpV4f c=1 sm=1 tr=0 ts=699ea2b8 cx=c_pps a=OI0sxtj7PyCX9F1bxD/puw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=7UlbJtpOWuNyX1kucuYA:9 a=QEXdDO2ut3YA:10 a=Z1Yy7GAxqfX1iEi80vsk:22 X-Proofpoint-GUID: wTAO9mBE1ZhXoAEfvY5E4l15WQZg0-ae X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-24_03,2026-02-23_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 clxscore=1015 spamscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602250070 From: Jie Gan Add CoreSight nodes to enable trace paths such as TPDM->ETF and STM->ETF. These devices are part of the AOSS, CDSP, QDSS, modem and some small subsystems, such as DCC, GCC, ipcc and so on. Signed-off-by: Jie Gan Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 1160 +++++++++++++++++++++++++++= ++++ 1 file changed, 1160 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/= qcom/kaanapali.dtsi index 9ef57ad0ca71..6e231850d5d6 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -1080,6 +1080,1114 @@ card-detect-pins { }; }; =20 + stm@10002000 { + compatible =3D "arm,coresight-stm", "arm,primecell"; + reg =3D <0x0 0x10002000 0x0 0x1000>, + <0x0 0x16280000 0x0 0x180000>; + reg-names =3D "stm-base", + "stm-stimulus-base"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint =3D <&funnel_in0_in7>; + }; + }; + }; + }; + + tpdm@10003000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x10003000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <32>; + + out-ports { + port { + tpdm_dcc_out: endpoint { + remote-endpoint =3D <&tpda_qdss_in0>; + }; + }; + }; + }; + + tpda@10004000 { + compatible =3D "qcom,coresight-tpda", "arm,primecell"; + reg =3D <0x0 0x10004000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + tpda_qdss_in0: endpoint { + remote-endpoint =3D <&tpdm_dcc_out>; + }; + }; + + port@1 { + reg =3D <1>; + + tpda_qdss_in1: endpoint { + remote-endpoint =3D <&tpdm_spdm_out>; + }; + }; + }; + + out-ports { + port { + tpda_qdss_out: endpoint { + remote-endpoint =3D <&funnel_in0_in6>; + }; + }; + }; + }; + + tpdm@1000f000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1000f000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <32>; + + out-ports { + port { + tpdm_spdm_out: endpoint { + remote-endpoint =3D <&tpda_qdss_in1>; + }; + }; + }; + }; + + funnel@10041000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0x0 0x10041000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + funnel_in0_in0: endpoint { + remote-endpoint =3D <&tn_ag_out>; + }; + }; + + port@6 { + reg =3D <6>; + + funnel_in0_in6: endpoint { + remote-endpoint =3D <&tpda_qdss_out>; + }; + }; + + port@7 { + reg =3D <7>; + + funnel_in0_in7: endpoint { + remote-endpoint =3D <&stm_out>; + }; + }; + }; + + out-ports { + port { + funnel_in0_out: endpoint { + remote-endpoint =3D <&funnel_aoss_in6>; + }; + }; + }; + }; + + tpdm@11000000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11000000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-element-bits =3D <32>; + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + tpdm_modem0_out: endpoint { + remote-endpoint =3D <&tpda_modem_in0>; + }; + }; + }; + }; + + tpda@11004000 { + compatible =3D "qcom,coresight-tpda", "arm,primecell"; + reg =3D <0x0 0x11004000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + tpda_modem_in0: endpoint { + remote-endpoint =3D <&tpdm_modem0_out>; + }; + }; + + port@1 { + reg =3D <1>; + + tpda_modem_in1: endpoint { + remote-endpoint =3D <&tpdm_modem1_out>; + }; + }; + + port@2 { + reg =3D <2>; + + tpda_modem_in2: endpoint { + remote-endpoint =3D <&tpdm_modem2_out>; + }; + }; + }; + + out-ports { + port { + tpda_modem_out: endpoint { + remote-endpoint =3D <&funnel_modem_dl_in0>; + }; + }; + }; + }; + + funnel@11005000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0x0 0x11005000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + port { + funnel_modem_dl_in0: endpoint { + remote-endpoint =3D <&tpda_modem_out>; + }; + }; + }; + + out-ports { + port { + funnel_modem_dl_out: endpoint { + remote-endpoint =3D <&tn_ag_in13>; + }; + }; + }; + }; + + tpdm@1102c000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1102c000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + tpdm_gcc_out: endpoint { + remote-endpoint =3D <&tn_ag_in17>; + }; + }; + }; + }; + + tpdm@11180000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11180000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-element-bits =3D <32>; + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + tpdm_cdsp_out: endpoint { + remote-endpoint =3D <&tpda_cdsp_in0>; + }; + }; + }; + }; + + tpdm@11183000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11183000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-element-bits =3D <32>; + qcom,cmb-element-bits =3D <32>; + + out-ports { + port { + tpdm_cdsp_cmsr1_out: endpoint { + remote-endpoint =3D <&tpda_cdsp_in3>; + }; + }; + }; + }; + + tpdm@11184000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11184000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-element-bits =3D <32>; + qcom,cmb-element-bits =3D <32>; + + out-ports { + port { + tpdm_cdsp_cmsr2_out: endpoint { + remote-endpoint =3D <&tpda_cdsp_in4>; + }; + }; + }; + }; + + tpdm@11185000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11185000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <64>; + + out-ports { + port { + tpdm_cdsp_dpm1_out: endpoint { + remote-endpoint =3D <&tpda_cdsp_in5>; + }; + }; + }; + }; + + tpdm@11186000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11186000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <64>; + + out-ports { + port { + tpdm_cdsp_dpm2_out: endpoint { + remote-endpoint =3D <&tpda_cdsp_in6>; + }; + }; + }; + }; + + tpda@11188000 { + compatible =3D "qcom,coresight-tpda", "arm,primecell"; + reg =3D <0x0 0x11188000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + tpda_cdsp_in0: endpoint { + remote-endpoint =3D <&tpdm_cdsp_out>; + }; + }; + + port@1 { + reg =3D <1>; + + tpda_cdsp_in1: endpoint { + remote-endpoint =3D <&tpdm_cdsp_llm_out>; + }; + }; + + port@2 { + reg =3D <2>; + + tpda_cdsp_in2: endpoint { + remote-endpoint =3D <&tpdm_cdsp_llm2_out>; + }; + }; + + port@3 { + reg =3D <3>; + + tpda_cdsp_in3: endpoint { + remote-endpoint =3D <&tpdm_cdsp_cmsr1_out>; + }; + }; + + port@4 { + reg =3D <4>; + + tpda_cdsp_in4: endpoint { + remote-endpoint =3D <&tpdm_cdsp_cmsr2_out>; + }; + }; + + port@5 { + reg =3D <5>; + + tpda_cdsp_in5: endpoint { + remote-endpoint =3D <&tpdm_cdsp_dpm1_out>; + }; + }; + + port@6 { + reg =3D <6>; + + tpda_cdsp_in6: endpoint { + remote-endpoint =3D <&tpdm_cdsp_dpm2_out>; + }; + }; + }; + + out-ports { + port { + tpda_cdsp_out: endpoint { + remote-endpoint =3D <&funnel_cdsp_in0>; + }; + }; + }; + }; + + funnel@11189000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0x0 0x11189000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + port { + funnel_cdsp_in0: endpoint { + remote-endpoint =3D <&tpda_cdsp_out>; + }; + }; + }; + + out-ports { + port { + funnel_cdsp_out: endpoint { + remote-endpoint =3D <&tn_ag_in16>; + }; + }; + }; + }; + + tpdm@111a3000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111a3000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + tpdm_pmu_out: endpoint { + remote-endpoint =3D <&tn_ag_in29>; + }; + }; + }; + }; + + tpdm@111a4000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111a4000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + tpdm_qrng_out: endpoint { + remote-endpoint =3D <&tn_ag_in18>; + }; + }; + }; + }; + + tpdm@111a5000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111a5000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + tpdm_dlmm_out: endpoint { + remote-endpoint =3D <&tn_ag_in25>; + }; + }; + }; + }; + + tpdm@111a6000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111a6000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + tpdm_north_dsb_out: endpoint { + remote-endpoint =3D <&tn_ag_in26>; + }; + }; + }; + }; + + tpdm@111a7000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111a7000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + tpdm_south_dsb_out: endpoint { + remote-endpoint =3D <&tn_ag_in27>; + }; + }; + }; + }; + + tpdm@111a8000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111a8000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + tpdm_rdpm_cmb0_out: endpoint { + remote-endpoint =3D <&tn_ag_in30>; + }; + }; + }; + }; + + tpdm@111a9000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111a9000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + tpdm_rdpm_cmb1_out: endpoint { + remote-endpoint =3D <&tn_ag_in31>; + }; + }; + }; + }; + + tpdm@111aa000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111aa000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + tpdm_rdpm_cmb2_out: endpoint { + remote-endpoint =3D <&tn_ag_in32>; + }; + }; + }; + }; + + tpdm@111ab000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111ab000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_cmb0_out: endpoint { + remote-endpoint =3D <&tn_ag_in36>; + }; + }; + }; + }; + + tpdm@111ac000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111ac000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_cmb1_out: endpoint { + remote-endpoint =3D <&tn_ag_in28>; + }; + }; + }; + }; + + tpdm@111ad000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111ad000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_cmb2_out: endpoint { + remote-endpoint =3D <&tn_ag_in34>; + }; + }; + }; + }; + + tpdm@111ae000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111ae000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_cmb3_out: endpoint { + remote-endpoint =3D <&tn_ag_in37>; + }; + }; + }; + }; + + tpdm@111af000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111af000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_cmb4_out: endpoint { + remote-endpoint =3D <&tn_ag_in35>; + }; + }; + }; + }; + + tpdm@111b3000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111b3000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + tpdm_pcie_rscc_out: endpoint { + remote-endpoint =3D <&tn_ag_in8>; + }; + }; + }; + }; + + tn@111b8000 { + compatible =3D "qcom,coresight-tnoc", "arm,primecell"; + reg =3D <0x0 0x111b8000 0x0 0x4200>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@8 { + reg =3D <8>; + + tn_ag_in8: endpoint { + remote-endpoint =3D <&tpdm_pcie_rscc_out>; + }; + }; + + port@d { + reg =3D <0xd>; + + tn_ag_in13: endpoint { + remote-endpoint =3D <&funnel_modem_dl_out>; + }; + }; + + port@10 { + reg =3D <0x10>; + + tn_ag_in16: endpoint { + remote-endpoint =3D <&funnel_cdsp_out>; + }; + }; + + port@11 { + reg =3D <0x11>; + + tn_ag_in17: endpoint { + remote-endpoint =3D <&tpdm_gcc_out>; + }; + }; + + port@12 { + reg =3D <0x12>; + + tn_ag_in18: endpoint { + remote-endpoint =3D <&tpdm_qrng_out>; + }; + }; + + port@13 { + reg =3D <0x13>; + + tn_ag_in19: endpoint { + remote-endpoint =3D <&tpdm_qm_out>; + }; + }; + + port@15 { + reg =3D <0x15>; + + tn_ag_in21: endpoint { + remote-endpoint =3D <&tpdm_ipa_out>; + }; + }; + + port@19 { + reg =3D <0x19>; + + tn_ag_in25: endpoint { + remote-endpoint =3D <&tpdm_dlmm_out>; + }; + }; + + port@1a { + reg =3D <0x1a>; + + tn_ag_in26: endpoint { + remote-endpoint =3D <&tpdm_north_dsb_out>; + }; + }; + + port@1b { + reg =3D <0x1b>; + + tn_ag_in27: endpoint { + remote-endpoint =3D <&tpdm_south_dsb_out>; + }; + }; + + port@1c { + reg =3D <0x1c>; + + tn_ag_in28: endpoint { + remote-endpoint =3D <&tpdm_ipcc_cmb1_out>; + }; + }; + + port@1d { + reg =3D <0x1d>; + + tn_ag_in29: endpoint { + remote-endpoint =3D <&tpdm_pmu_out>; + }; + }; + + port@1e { + reg =3D <0x1e>; + + tn_ag_in30: endpoint { + remote-endpoint =3D <&tpdm_rdpm_cmb0_out>; + }; + }; + + port@1f { + reg =3D <0x1f>; + + tn_ag_in31: endpoint { + remote-endpoint =3D <&tpdm_rdpm_cmb1_out>; + }; + }; + + port@20 { + reg =3D <0x20>; + + tn_ag_in32: endpoint { + remote-endpoint =3D <&tpdm_rdpm_cmb2_out>; + }; + }; + + port@22 { + reg =3D <0x22>; + + tn_ag_in34: endpoint { + remote-endpoint =3D <&tpdm_ipcc_cmb2_out>; + }; + }; + + port@23 { + reg =3D <0x23>; + + tn_ag_in35: endpoint { + remote-endpoint =3D <&tpdm_ipcc_cmb4_out>; + }; + }; + + port@24 { + reg =3D <0x24>; + + tn_ag_in36: endpoint { + remote-endpoint =3D <&tpdm_ipcc_cmb0_out>; + }; + }; + + port@25 { + reg =3D <37>; + + tn_ag_in37: endpoint { + remote-endpoint =3D <&tpdm_ipcc_cmb3_out>; + }; + }; + }; + + out-ports { + port { + tn_ag_out: endpoint { + remote-endpoint =3D <&funnel_in0_in0>; + }; + }; + }; + }; + + tpdm@111d0000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111d0000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + tpdm_qm_out: endpoint { + remote-endpoint =3D <&tn_ag_in19>; + }; + }; + }; + }; + + tpdm@11303000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11303000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <64>; + + out-ports { + port { + tpdm_swao_prio4_out: endpoint { + remote-endpoint =3D <&tpda_aoss_in4>; + }; + }; + }; + }; + + funnel@11304000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0x0 0x11304000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@5 { + reg =3D <5>; + + funnel_aoss_in5: endpoint { + remote-endpoint =3D <&tpda_aoss_out>; + }; + }; + + port@6 { + reg =3D <6>; + + funnel_aoss_in6: endpoint { + remote-endpoint =3D <&funnel_in0_out>; + }; + }; + + }; + + out-ports { + port { + funnel_aoss_out: endpoint { + remote-endpoint =3D <&tmc_etf_in>; + }; + }; + }; + }; + + tmc@11305000 { + compatible =3D "arm,coresight-tmc", "arm,primecell"; + reg =3D <0x0 0x11305000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + port { + tmc_etf_in: endpoint { + remote-endpoint =3D <&funnel_aoss_out>; + }; + }; + }; + }; + + tpda@11308000 { + compatible =3D "qcom,coresight-tpda", "arm,primecell"; + reg =3D <0x0 0x11308000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + tpda_aoss_in0: endpoint { + remote-endpoint =3D <&tpdm_swao_prio0_out>; + }; + }; + + port@1 { + reg =3D <1>; + + tpda_aoss_in1: endpoint { + remote-endpoint =3D <&tpdm_swao_prio1_out>; + }; + }; + + port@2 { + reg =3D <2>; + + tpda_aoss_in2: endpoint { + remote-endpoint =3D <&tpdm_swao_prio2_out>; + }; + }; + + port@3 { + reg =3D <3>; + + tpda_aoss_in3: endpoint { + remote-endpoint =3D <&tpdm_swao_prio3_out>; + }; + }; + + port@4 { + reg =3D <4>; + + tpda_aoss_in4: endpoint { + remote-endpoint =3D <&tpdm_swao_prio4_out>; + }; + }; + + port@5 { + reg =3D <5>; + + tpda_aoss_in5: endpoint { + remote-endpoint =3D <&tpdm_swao_out>; + }; + }; + }; + + out-ports { + port { + tpda_aoss_out: endpoint { + remote-endpoint =3D <&funnel_aoss_in5>; + }; + }; + }; + }; + + tpdm@11309000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11309000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <64>; + + out-ports { + port { + tpdm_swao_prio0_out: endpoint { + remote-endpoint =3D <&tpda_aoss_in0>; + }; + }; + }; + }; + + tpdm@1130a000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1130a000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <64>; + + out-ports { + port { + tpdm_swao_prio1_out: endpoint { + remote-endpoint =3D <&tpda_aoss_in1>; + }; + }; + }; + }; + + tpdm@1130b000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1130b000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <64>; + + out-ports { + port { + tpdm_swao_prio2_out: endpoint { + remote-endpoint =3D <&tpda_aoss_in2>; + }; + }; + }; + }; + + tpdm@1130c000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1130c000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <64>; + + out-ports { + port { + tpdm_swao_prio3_out: endpoint { + remote-endpoint =3D <&tpda_aoss_in3>; + }; + }; + }; + }; + + tpdm@1130d000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1130d000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-element-bits =3D <32>; + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + tpdm_swao_out: endpoint { + remote-endpoint =3D <&tpda_aoss_in5>; + }; + }; + }; + }; + + tpdm@11422000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11422000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + tpdm_ipa_out: endpoint { + remote-endpoint =3D <&tn_ag_in21>; + }; + }; + }; + }; + sram@14680000 { compatible =3D "qcom,kaanapali-imem", "mmio-sram"; reg =3D <0x0 0x14680000 0x0 0x1000>; @@ -1603,4 +2711,56 @@ timer { , ; }; + + tpdm-cdsp-llm { + compatible =3D "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits =3D <32>; + + out-ports { + port { + tpdm_cdsp_llm_out: endpoint { + remote-endpoint =3D <&tpda_cdsp_in1>; + }; + }; + }; + }; + + tpdm-cdsp-llm2 { + compatible =3D "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits =3D <32>; + + out-ports { + port { + tpdm_cdsp_llm2_out: endpoint { + remote-endpoint =3D <&tpda_cdsp_in2>; + }; + }; + }; + }; + + tpdm-modem1 { + compatible =3D "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits =3D <32>; + + out-ports { + port { + tpdm_modem1_out: endpoint { + remote-endpoint =3D <&tpda_modem_in1>; + }; + }; + }; + }; + + tpdm-modem2 { + compatible =3D "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits =3D <64>; + + out-ports { + port { + tpdm_modem2_out: endpoint { + remote-endpoint =3D <&tpda_modem_in2>; + }; + }; + }; + }; }; --=20 2.25.1 From nobody Thu Apr 2 07:43:57 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 741002E8B81 for ; Wed, 25 Feb 2026 07:20:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772004031; cv=none; b=YEIaUDZb/FHt7/B66aXNuJk3KuQ4tC1K+nMZJRjqQFA5H85uGKh7+0xC/ShVN3iZKeqAwqLBynejpVOJ5LiJdAQLsY1yMQPA4b4+FZOIJFo2hZsRiI33jGeNyC/9EzDLEY6qxFhCqFUdlt1ExGewwTcH4pP/41xJnJtOKKpi0qc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772004031; c=relaxed/simple; bh=TwKM/iiZBc1hjmr0XFokc7xHd/LSEj0p3Bif+EobwI8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Ggnh9dARKZnnWSc3Hx0FyskPj4/fsHMQKPk3WYPalGtjbq9PPVcSnCxHxyp7kl2St/6GcK5aSCOQ99ib6xQE2dCLG3HVTz3KKiF7Q/IIVcxRS+098VHf44EFymsE4WI+duem0Qnw3IAC4LlwqejZYwGjPiKsQyOo+ZiUW4tue/I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=eMKsKXSw; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=V5o2FYB+; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="eMKsKXSw"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="V5o2FYB+" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 61P17xeo4148697 for ; Wed, 25 Feb 2026 07:20:26 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= ae/JLaDJtVNIUI6HViu8SLk8O1F+gXZDZFTW9ereLNg=; b=eMKsKXSwdZsAYA49 O+CLucf2/aGL9zIHtv0gxiye0jh0XePbsQNBTG9lJKe6OSqqUdVqzs/OeM8GYHnY KOX5BqYCWEgZViuzRD/E+eoUJnk3lnvZsvv3eDMPGpKmWeEYpKuYxFqSqmrUbLrO cvqz7jCVmUBwpKc/OndaFf0KeXl1AKhTZxMzdro8NLWQ/LH6XfaMwY0zZRNHa7lH w1GCzC0xPS6XNbrCC3cUgVoLMBO9+YZtHPgw7lYkeUpwUQ9/f0tbvgPXobpICS7E TnoJ5cFb6FayWxvMCGOMTYnfOG8EfiBacyg3/WubX3bBqDfkx+Cz/tOQBSODZ48N q0WWxA== Received: from mail-ot1-f71.google.com (mail-ot1-f71.google.com [209.85.210.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4chq57ruwc-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 25 Feb 2026 07:20:26 +0000 (GMT) Received: by mail-ot1-f71.google.com with SMTP id 46e09a7af769-7d18e95c658so87419660a34.2 for ; Tue, 24 Feb 2026 23:20:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1772004026; x=1772608826; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ae/JLaDJtVNIUI6HViu8SLk8O1F+gXZDZFTW9ereLNg=; b=V5o2FYB+Ra/+dxDn68vGEqMGz0GjjN65lQahU25MFfFgT5N2CdI8n/zYduKKDr3j2z w5TmzP0mflw39vTUSJqOQdscvAClIaeQoxH6OZFEHAB++jGaE7h8jczcfRMCTbbXns/N XCt4GSIrdeaTZAKl4j6rPEawCXQ+V4PtxzH3AgFgfGc0ulXyUL18NNs/OTxzhRgHZ8Tm kDcgtHDczIgCk9jawlxjeilYcKetGNuHOrc90ODrsjoZvqmYQBJMj8NIDmyUhHGOGxtu +AaMcK+thTgVUMV8rn+boXBGWf/eh52nR/bQUE1gL/SFlqbah59Wx0I0DkmK1/HL1v2M ZPfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772004026; x=1772608826; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=ae/JLaDJtVNIUI6HViu8SLk8O1F+gXZDZFTW9ereLNg=; b=CIcCVvmk2mpuFKcArJjcYX8iWQBvaaTMFSXqGKGi5FGIAO//BGkctxIc6fvp2wu2Gj fbmVkym/Lo2QCyES615AC4Ucxs1ABls+YQ4rppuQIZ0vnD6pWlatxuwXO68pjp9WbqO4 H230afKP+luR+NPnMCcBDqiFeHc1Dx/ha1PFO4QYqMT0sog4cLuoraP78Ho9QvHs3EmP 6Yu0y7rySZqLA/h9l9F5ncpiQUgkJNH60dOC4Fi9wkavARMBV4h4oa6US1XVdgbTgbDh iFeMfNuAIXFvuGFMeA6H4aVts3hO5xzHvJR84F2ELhMJ+LqYAV9+8GGAFSZcLvmgJvXA UQOw== X-Forwarded-Encrypted: i=1; AJvYcCWiFN09plrqMFSgYb//SzpgvtiLkE1cuZomVfYJqVXa0LP0twCLoi37dPErCaLJURqSPso3BYQ1NBBu3Kk=@vger.kernel.org X-Gm-Message-State: AOJu0YzwoX9y2SyvtS/O1M45uD9VvQ9RnfR4JUYCh6nARcR/qt7rCFq5 jHXKw1Y61aEXH7tX8EXwfQUIMl7hS1sSjyM1yL59YaKddWNXSIiCWeo0LvrFZ32zqS1euJmrXtK aTLYYnlPxx9wyORL0DIiwt28XFy2irdPYMRRPiH/BSuVfsevfy4SmBWyyJ8RGwG7AGaA= X-Gm-Gg: ATEYQzyywsI5vrsWZClHrfSiZf4SXLduy85R94iQjQRbAC0bAhp6Mi+heNvETYpuxpL kQ1tZi9H10H55uxRXxEK+sMonGhh6Ve/u+48L1DQjO5YLs4/OopvdHE0jCaP6rtE1Woqr2Xfyjt X3wOjrTeptu7XWt3ScMGWFQZ30Z2RO7f7sCvn//EiEWUal/tsnqO5EG7v9r4sRsG9Uv1+fZyIPP Awy6kFF6MO0mYopWh2pwNFEc4hiBQWxix+yfrtaD+YewipmsH8eWQ1Us3r2bkTTIubE8G/GtIaz zubkXDQYqN1HGnhRELbjoHD4/jH83kQHYcS/m0F83hoxZDVql/EyDGjQuyngWU8gsNoZA+SUVzU lkOoZHjl3CbAHvD2WRCAzxN745PEBHhwp+oRlYl/kR3N8l7nv0oycHO8OgeOYVjXFdithFSec X-Received: by 2002:a05:6830:82c5:b0:7cf:e32f:de72 with SMTP id 46e09a7af769-7d52be03d53mr9829346a34.6.1772004025140; Tue, 24 Feb 2026 23:20:25 -0800 (PST) X-Received: by 2002:a05:6830:82c5:b0:7cf:e32f:de72 with SMTP id 46e09a7af769-7d52be03d53mr9829326a34.6.1772004024556; Tue, 24 Feb 2026 23:20:24 -0800 (PST) Received: from hu-jingyw-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7d52d038dcdsm11711730a34.16.2026.02.24.23.20.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Feb 2026 23:20:24 -0800 (PST) From: Jingyi Wang Date: Tue, 24 Feb 2026 23:19:17 -0800 Subject: [PATCH v6 02/10] arm64: dts: qcom: kaanapali: Add QUPv3 configuration for serial engines Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260224-knp-dts-misc-v6-2-79d20dab8a60@oss.qualcomm.com> References: <20260224-knp-dts-misc-v6-0-79d20dab8a60@oss.qualcomm.com> In-Reply-To: <20260224-knp-dts-misc-v6-0-79d20dab8a60@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jingyi Wang , 20260114-knp-remoteproc-v4-0-fcf0b04d01af@oss.qualcomm.com, Jyothi Kumar Seerapu , Dmitry Baryshkov X-Mailer: b4 0.15-dev-3d134 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772004019; l=61224; i=jingyi.wang@oss.qualcomm.com; s=20250911; h=from:subject:message-id; bh=uqrR+N5hI7kegH3rPB05hIysz5u+V5crPFurBE7Hjak=; b=jvtc6x8yxmLzH9yWR3spWnPTpRF9hS3kbWr4hhtTM0iv3rSh3icbaR8ak4heSL2w2/HYQojMq lv/PRgqr79sAjhza7GLN/YwnRUmWAiGXluJ/bIe1giRppavLAJVsDHA X-Developer-Key: i=jingyi.wang@oss.qualcomm.com; a=ed25519; pk=PSoHZ6KbUss3IW8FPRVMHMK0Jkkr/jV347mBYJO3iLo= X-Authority-Analysis: v=2.4 cv=faOgCkQF c=1 sm=1 tr=0 ts=699ea2ba cx=c_pps a=OI0sxtj7PyCX9F1bxD/puw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=ejbl41xVDxFUV4oecBwA:9 a=QEXdDO2ut3YA:10 a=Z1Yy7GAxqfX1iEi80vsk:22 X-Proofpoint-ORIG-GUID: x4euLAAAdRcCcXlEmBVh9HoeK9XnexoF X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjI1MDA3MCBTYWx0ZWRfXzLmyEnL2uFMU awAYkzUmZ30HoXf/R4+BFiRTKmhiRchrUEaRq/IHjRulEcVBV27tVH4GMyAfb4Gs4sm2dc0s2EL 6/UjVViIdqPgNPfVHE3dYUQ330yIQFCE3xzcKE+sOFZZAoWt7DMAX1+4WH4L3GkRf/qOeQB7O9I pFjLzstgEWNvQPUp5ctKPkYhWlY0ahV51I5dsnuArOpLww00bPQUd4tzDQJfoXzAydN3Np/RKsG gyWQWT97NqLUAwxDLXThYguia8R2KQvRPxmYP+EOmgM8UgHQT/lhun3vg7aTOQkn0lZo6cGRFLm TZjTDgJ4LGLfxZUzSq2dHlSHaDMJCWMtjg9d/iYVKDzr7ZeAc/jN9j3VTI4EfKpswiHsJzQVhJ9 8gi4d4Af8ehQF4JwmN3l06OwIDW6MGZFVrPOlrCnDYkAd0Cta1qCgoH3Cr4UWYp5qPRTj7M7fmn mBq/ivdpUVLiir/qljg== X-Proofpoint-GUID: x4euLAAAdRcCcXlEmBVh9HoeK9XnexoF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-24_03,2026-02-23_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 impostorscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 malwarescore=0 spamscore=0 bulkscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602250070 From: Jyothi Kumar Seerapu Add device tree support for QUPv3 serial engine protocols on Kaanapali. Kaanapali has 24 QUP serial engines across 4 QUP wrappers, each with support of GPI DMA engines, and it also includes 5 I2C hubs. Signed-off-by: Jyothi Kumar Seerapu Reviewed-by: Dmitry Baryshkov Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 2092 +++++++++++++++++++++++++++= ++++ 1 file changed, 2092 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/= qcom/kaanapali.dtsi index 6e231850d5d6..df05d204ed41 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -468,6 +469,508 @@ gcc: clock-controller@100000 { #power-domain-cells =3D <1>; }; =20 + gpi_dma2: dma-controller@800000 { + compatible =3D "qcom,kaanapali-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0x0 0x00800000 0x0 0x60000>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels =3D <12>; + dma-channel-mask =3D <0x1f>; + #dma-cells =3D <3>; + + iommus =3D <&apps_smmu 0x436 0x0>; + dma-coherent; + }; + + qupv3_2: geniqup@8c0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x008c0000 0x0 0x2000>; + + clocks =3D <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + clock-names =3D "m-ahb", + "s-ahb"; + + iommus =3D <&apps_smmu 0x423 0x0>; + + dma-coherent; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + i2c8: i2c@880000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00880000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c8_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi8: spi@880000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00880000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi8_data_clk>, <&qup_spi8_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c9: i2c@884000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00884000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c9_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi9: spi@884000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00884000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi9_data_clk>, <&qup_spi9_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c10: i2c@888000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00888000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c10_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi10: spi@888000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00888000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi10_data_clk>, <&qup_spi10_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c11: i2c@88c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x0088c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c11_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi11: spi@88c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x0088c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma2 0 3 QCOM_GPI_SPI>, + <&gpi_dma2 1 3 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi11_data_clk>, <&qup_spi11_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c12: i2c@890000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00890000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c12_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + }; + + i2c_master_hub: geniqup@9c0000 { + compatible =3D "qcom,geni-se-i2c-master-hub"; + reg =3D <0x0 0x009c0000 0x0 0x2000>; + + clocks =3D <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; + clock-names =3D "s-ahb"; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + i2c_hub_0: i2c@980000 { + compatible =3D "qcom,geni-i2c-master-hub"; + reg =3D <0x0 0x00980000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_I2C_S0_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names =3D "se", + "core"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&hub_i2c0_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c_hub_1: i2c@984000 { + compatible =3D "qcom,geni-i2c-master-hub"; + reg =3D <0x0 0x00984000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_I2C_S1_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names =3D "se", + "core"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&hub_i2c1_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c_hub_2: i2c@988000 { + compatible =3D "qcom,geni-i2c-master-hub"; + reg =3D <0x0 0x00988000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_I2C_S2_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names =3D "se", + "core"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&hub_i2c2_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c_hub_3: i2c@98c000 { + compatible =3D "qcom,geni-i2c-master-hub"; + reg =3D <0x0 0x0098c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_I2C_S3_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names =3D "se", + "core"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&hub_i2c3_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c_hub_4: i2c@990000 { + compatible =3D "qcom,geni-i2c-master-hub"; + reg =3D <0x0 0x00990000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_I2C_S4_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names =3D "se", + "core"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&hub_i2c4_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + }; + + gpi_dma1: dma-controller@a00000 { + compatible =3D "qcom,kaanapali-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0x0 0x00a00000 0x0 0x60000>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels =3D <12>; + dma-channel-mask =3D <0x1f>; + #dma-cells =3D <3>; + + iommus =3D <&apps_smmu 0xb6 0x0>; + dma-coherent; + }; + qupv3_1: geniqup@ac0000 { compatible =3D "qcom,geni-se-qup"; reg =3D <0x0 0x00ac0000 0x0 0x2000>; @@ -485,6 +988,447 @@ qupv3_1: geniqup@ac0000 { #size-cells =3D <2>; ranges; =20 + i2c0: i2c@a80000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a80000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c0_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi0: spi@a80000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a80000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c1: i2c@a84000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a84000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c1_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi1: spi@a84000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a84000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi1_data_clk>, <&qup_spi1_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c2: i2c@a88000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a88000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c2_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi2: spi@a88000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a88000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi2_data_clk>, <&qup_spi2_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c3: i2c@a8c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a8c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c3_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi3: spi@a8c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a8c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi3_data_clk>, <&qup_spi3_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c4: i2c@a90000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a90000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c4_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi4: spi@a90000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a90000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi4_data_clk>, <&qup_spi4_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c5: i2c@a94000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a94000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c5_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi5: spi@a94000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a94000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi5_data_clk>, <&qup_spi5_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c6: i2c@a98000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a98000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c6_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi6: spi@a98000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a98000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma1 0 6 QCOM_GPI_SPI>, + <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi6_data_clk>, <&qup_spi6_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + uart7: serial@a9c000 { compatible =3D "qcom,geni-debug-uart"; reg =3D <0x0 0x00a9c000 0x0 0x4000>; @@ -566,6 +1510,653 @@ mmss_noc: interconnect@1780000 { #interconnect-cells =3D <2>; }; =20 + gpi_dma3: dma-controller@1900000 { + compatible =3D "qcom,kaanapali-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0x0 0x01900000 0x0 0x60000>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels =3D <12>; + dma-channel-mask =3D <0x1e>; + #dma-cells =3D <3>; + + iommus =3D <&apps_smmu 0x4d6 0x0>; + dma-coherent; + }; + + qupv3_3: geniqup@19c0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x019c0000 0x0 0x2000>; + + clocks =3D <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; + clock-names =3D "m-ahb", + "s-ahb"; + + iommus =3D <&apps_smmu 0x4c3 0x0>; + + dma-coherent; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + i2c13: i2c@1980000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x01980000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma3 0 0 QCOM_GPI_I2C>, + <&gpi_dma3 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c13_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c14: i2c@1984000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x01984000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma3 0 1 QCOM_GPI_I2C>, + <&gpi_dma3 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c14_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi14: spi@1984000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x01984000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma3 0 1 QCOM_GPI_SPI>, + <&gpi_dma3 1 1 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi14_data_clk>, <&qup_spi14_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c15: i2c@1988000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x01988000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma3 0 2 QCOM_GPI_I2C>, + <&gpi_dma3 1 2 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c15_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi15: spi@1988000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x01988000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma3 0 2 QCOM_GPI_SPI>, + <&gpi_dma3 1 2 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi15_data_clk>, <&qup_spi15_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c16: i2c@198c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x0198c000 0x0 0x4000>; + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma3 0 3 QCOM_GPI_I2C>, + <&gpi_dma3 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c16_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi16: spi@198c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x198c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma3 0 3 QCOM_GPI_SPI>, + <&gpi_dma3 1 3 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi16_data_clk>, <&qup_spi16_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c17: i2c@1990000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x01990000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S4_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma3 0 4 QCOM_GPI_I2C>, + <&gpi_dma3 1 4 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c17_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi17: spi@1990000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x01990000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S4_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma3 0 4 QCOM_GPI_SPI>, + <&gpi_dma3 1 4 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi17_data_clk>, <&qup_spi17_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart18: serial@1994000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x01994000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S5_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart18_default>, <&qup_uart18_cts_rts>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + }; + + gpi_dma4: dma-controller@1a00000 { + compatible =3D "qcom,kaanapali-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0x0 0x01a00000 0x0 0x60000>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels =3D <12>; + dma-channel-mask =3D <0x1e>; + #dma-cells =3D <3>; + + iommus =3D <&apps_smmu 0x536 0x0>; + dma-coherent; + }; + + qupv3_4: geniqup@1ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x01ac0000 0x0 0x2000>; + + clocks =3D <&gcc GCC_QUPV3_WRAP_4_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_4_S_AHB_CLK>; + clock-names =3D "m-ahb", + "s-ahb"; + + iommus =3D <&apps_smmu 0x523 0x0>; + + dma-coherent; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + i2c19: i2c@1a80000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x01a80000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP4_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma4 0 0 QCOM_GPI_I2C>, + <&gpi_dma4 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c19_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi19: spi@1a80000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x01a80000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP4_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma4 0 0 QCOM_GPI_SPI>, + <&gpi_dma4 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi19_data_clk>, <&qup_spi19_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c20: i2c@1a84000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x01a84000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP4_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma4 0 1 QCOM_GPI_I2C>, + <&gpi_dma4 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c20_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi20: spi@1a84000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x01a84000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP4_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma4 0 1 QCOM_GPI_SPI>, + <&gpi_dma4 1 1 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi20_data_clk>, <&qup_spi20_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c21: i2c@1a88000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x01a88000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP4_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma4 0 2 QCOM_GPI_I2C>, + <&gpi_dma4 1 2 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c21_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi21: spi@1a88000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x01a88000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP4_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma4 0 2 QCOM_GPI_SPI>, + <&gpi_dma4 1 2 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi21_data_clk>, <&qup_spi21_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c22: i2c@1a8c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x01a8c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP4_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma4 0 3 QCOM_GPI_I2C>, + <&gpi_dma4 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c22_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c23: i2c@1a90000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x01a90000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP4_S4_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma4 0 4 QCOM_GPI_I2C>, + <&gpi_dma4 1 4 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c23_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + }; + pcie0: pcie@1c00000 { device_type =3D "pci"; compatible =3D "qcom,kaanapali-pcie", "qcom,pcie-sm8550"; @@ -1017,6 +2608,491 @@ tlmm: pinctrl@f100000 { #interrupt-cells =3D <2>; wakeup-parent =3D <&pdc>; =20 + hub_i2c0_data_clk: hub-i2c0-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio66", "gpio67"; + function =3D "i2chub0_se0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + hub_i2c1_data_clk: hub-i2c1-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio78", "gpio79"; + function =3D "i2chub0_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + hub_i2c2_data_clk: hub-i2c2-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio68", "gpio69"; + function =3D "i2chub0_se2"; + drive-strength =3D <2>; + bias-pull-up; + }; + + hub_i2c3_data_clk: hub-i2c3-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio70", "gpio71"; + function =3D "i2chub0_se3"; + drive-strength =3D <2>; + bias-pull-up; + }; + + hub_i2c4_data_clk: hub-i2c4-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio72", "gpio73"; + function =3D "i2chub0_se4"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c0_data_clk: qup-i2c0-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio80", "gpio83"; + function =3D "qup1_se0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio74", "gpio75"; + function =3D "qup1_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio40", "gpio41"; + function =3D "qup1_se2"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio44", "gpio45"; + function =3D "qup1_se3"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio36", "gpio37"; + function =3D "qup1_se4"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio52", "gpio53"; + function =3D "qup1_se5"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio56", "gpio57"; + function =3D "qup1_se6"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c8_data_clk: qup-i2c8-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio0", "gpio1"; + function =3D "qup2_se0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio4", "gpio5"; + function =3D "qup2_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c10_data_clk: qup-i2c10-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio117", "gpio118"; + function =3D "qup2_se2"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c11_data_clk: qup-i2c11-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio122", "gpio123"; + function =3D "qup2_se3"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c12_data_clk: qup-i2c12-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio208", "gpio209"; + function =3D "qup2_se4"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c13_data_clk: qup-i2c13-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio64", "gpio65"; + function =3D "qup3_se0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c14_data_clk: qup-i2c14-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio8", "gpio9"; + function =3D "qup3_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c15_data_clk: qup-i2c15-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio12", "gpio13"; + function =3D "qup3_se2"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c16_data_clk: qup-i2c16-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio16", "gpio17"; + function =3D "qup3_se3"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c17_data_clk: qup-i2c17-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio20", "gpio21"; + function =3D "qup3_se4"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c19_data_clk: qup-i2c19-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio48", "gpio49"; + function =3D "qup4_se0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c20_data_clk: qup-i2c20-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio28", "gpio29"; + function =3D "qup4_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c21_data_clk: qup-i2c21-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio32", "gpio33"; + function =3D "qup4_se2"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c22_data_clk: qup-i2c22-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio121", "gpio84"; + function =3D "qup4_se3"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c23_data_clk: qup-i2c23-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio161", "gpio162"; + function =3D "qup4_se4"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi0_cs: qup-spi0-cs-state { + pins =3D "gpio81"; + function =3D "qup1_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi0_data_clk: qup-spi0-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio80", "gpio83", "gpio82"; + function =3D "qup1_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi1_cs: qup-spi1-cs-state { + pins =3D "gpio77"; + function =3D "qup1_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi1_data_clk: qup-spi1-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio74", "gpio75", "gpio76"; + function =3D "qup1_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi2_cs: qup-spi2-cs-state { + pins =3D "gpio43"; + function =3D "qup1_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi2_data_clk: qup-spi2-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio40", "gpio41", "gpio42"; + function =3D "qup1_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi3_cs: qup-spi3-cs-state { + pins =3D "gpio47"; + function =3D "qup1_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi3_data_clk: qup-spi3-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio44", "gpio45", "gpio46"; + function =3D "qup1_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi4_cs: qup-spi4-cs-state { + pins =3D "gpio39"; + function =3D "qup1_se4"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi4_data_clk: qup-spi4-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio36", "gpio37", "gpio38"; + function =3D "qup1_se4"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi5_cs: qup-spi5-cs-state { + pins =3D "gpio55"; + function =3D "qup1_se5"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi5_data_clk: qup-spi5-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio52", "gpio53", "gpio54"; + function =3D "qup1_se5"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi6_cs: qup-spi6-cs-state { + pins =3D "gpio59"; + function =3D "qup1_se6"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi6_data_clk: qup-spi6-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio56", "gpio57", "gpio58"; + function =3D "qup1_se6"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi8_cs: qup-spi8-cs-state { + pins =3D "gpio3"; + function =3D "qup2_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi8_data_clk: qup-spi8-data-clk-state { + /* MISO, MOSI, CLK */pins =3D "gpio0", "gpio1", "gpio2"; + function =3D "qup2_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi9_cs: qup-spi9-cs-state { + pins =3D "gpio7"; + function =3D "qup2_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi9_data_clk: qup-spi9-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio4", "gpio5", "gpio6"; + function =3D "qup2_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi10_cs: qup-spi10-cs-state { + pins =3D "gpio120"; + function =3D "qup2_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi10_data_clk: qup-spi10-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio117", "gpio118", "gpio119"; + function =3D "qup2_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi11_cs: qup-spi11-cs-state { + pins =3D "gpio125"; + function =3D "qup2_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi11_data_clk: qup-spi11-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio122", "gpio123", "gpio124"; + function =3D "qup2_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi14_cs: qup-spi14-cs-state { + pins =3D "gpio11"; + function =3D "qup3_se1"; + drive-strength =3D <6>; + bias-pull-up; + }; + + qup_spi14_data_clk: qup-spi14-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio8", "gpio9", "gpio10"; + function =3D "qup3_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi15_cs: qup-spi15-cs-state { + pins =3D "gpio15"; + function =3D "qup3_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi15_data_clk: qup-spi15-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio12", "gpio13", "gpio14"; + function =3D "qup3_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi16_cs: qup-spi16-cs-state { + pins =3D "gpio19"; + function =3D "qup3_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi16_data_clk: qup-spi16-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio16", "gpio17", "gpio18"; + function =3D "qup3_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi17_cs: qup-spi17-cs-state { + pins =3D "gpio23"; + function =3D "qup3_se4"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi17_data_clk: qup-spi17-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio20", "gpio21", "gpio22"; + function =3D "qup3_se4"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi19_cs: qup-spi19-cs-state { + pins =3D "gpio51"; + function =3D "qup4_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi19_data_clk: qup-spi19-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio48", "gpio49", "gpio50"; + function =3D "qup4_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi20_cs: qup-spi20-cs-state { + pins =3D "gpio31"; + function =3D "qup4_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi20_data_clk: qup-spi20-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio28", "gpio29", "gpio30"; + function =3D "qup4_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi21_cs: qup-spi21-cs-state { + pins =3D "gpio35"; + function =3D "qup4_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi21_data_clk: qup-spi21-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio32", "gpio33", "gpio34"; + function =3D "qup4_se2"; + drive-strength =3D <6>; + bias-disable; + }; + qup_uart7_default: qup-uart7-state { /* TX, RX */ pins =3D "gpio62", "gpio63"; @@ -1025,6 +3101,22 @@ qup_uart7_default: qup-uart7-state { bias-disable; }; =20 + qup_uart18_default: qup-uart18-default-state { + /* TX, RX */ + pins =3D "gpio26", "gpio27"; + function =3D "qup3_se5"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_uart18_cts_rts: qup-uart18-cts-rts-state { + /* CTS, RTS */ + pins =3D "gpio24", "gpio25"; + function =3D "qup3_se5"; + drive-strength =3D <2>; + bias-pull-down; + }; + sdc2_default: sdc2-default-state { clk-pins { pins =3D "sdc2_clk"; --=20 2.25.1 From nobody Thu Apr 2 07:43:57 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 715C42FF669 for ; Wed, 25 Feb 2026 07:20:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772004032; cv=none; b=DKlMtB2Za8ZpCpuokDms2JgGmNmmtzu/eLRCLtC4q+5207cvnbZqXJkW2ve/ZS+k1RlZPJMhUSplnxD5g8XsVPZxJO7ao7FYscRWwQsg1U3S8uIS+k5wV6IPvKJGVK9hvOm7h/HJvzV0T8CeicHK9tbu6NfchZkpcWARmYr9X3A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772004032; c=relaxed/simple; bh=QeXv5QhcjW9e3PGF26jUwAAbWZlI9ybpYMc7vtWT8Zc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=isSI9Z0quB5QidfwuOYYk/30pNC7KJUzIMZ3mYgmXZfr6ACnx8KGUmNHOVt5ka9a1N/m6chiQrOEOS1EbzVwyIQnYv0cErQP6tMUE2FdRnCqGY58zMHzQRpnPybD6+5fck0YswU+tEGkRfPN+wLD9wlhlhgBR+UbccFVfCJFFHs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=cMEkYUoW; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=fUp4nUQM; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="cMEkYUoW"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="fUp4nUQM" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 61OLbphw2432436 for ; Wed, 25 Feb 2026 07:20:27 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= A+sm4Pd2kREBN9DxViiBfCb5Y7V/sx8AZjzpaQtUY+w=; b=cMEkYUoWCHf2Jhtg gSz6x6IgZuVQB1Tt8pF/EUBptP8lTBzFj3CAwrYrUO4PU5w5EaKrJHxsbOAhVtAj VJoKebFwHgi5qlPcrkluT+N1LR6KZscXrP4ZdvwsxMXHu1B4mo9tXz2E145cc8IV EVdZKXWZbJ/UpY8OdFCAZI74KOmJ/cbF5SW702ebVaFr2Cm8LZAWuzlx3Q0ygAsb c5WkKYurUs4R7tgZOfe4Hl0mmWpgbqBA8lGrKIOp5ZjOj+v7xOv4wxNap1s3/K6h a8GOJ9ED9jM9jJQWTutRwKVDCBKk1aWcMryQhXVhNq1D7Qmp1P6AHtuJQJi9Jozu X3MF5g== Received: from mail-ot1-f71.google.com (mail-ot1-f71.google.com [209.85.210.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4chekjaqen-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 25 Feb 2026 07:20:27 +0000 (GMT) Received: by mail-ot1-f71.google.com with SMTP id 46e09a7af769-7d4be1dee67so109002034a34.1 for ; Tue, 24 Feb 2026 23:20:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1772004027; x=1772608827; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=A+sm4Pd2kREBN9DxViiBfCb5Y7V/sx8AZjzpaQtUY+w=; b=fUp4nUQMCaYYxMjMxer6YTgTBTmB6jkLmIEIf8LeITDUTbFzhNiirCGaqTKVCID0gV RhXneztpWSZLzKlscmsX2Cqoy1bvAOXb57TIBojYhhS82UWJ2kRy96CaR56GsDDNQJC8 uRNw9rt/JiFXlqyyI5gkilYQ9Ut/lE8iFb2Tg7jR84/zSt4nGrFduSI7U+x7LZNXc6zJ uHXFRfbsVQpxfzXq8bJ6TvihLDlse7wZ/VHfmuVuSIc+lRiwKpOY1JpPA6QVFEVomURF NyYtjG8n1Wn76Yo4ziMZHtESv0VTKEX3lEL+HNFWn/RB5bQw8oLrSI/zu9BHk+WO9NWA /7sA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772004027; x=1772608827; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=A+sm4Pd2kREBN9DxViiBfCb5Y7V/sx8AZjzpaQtUY+w=; b=V2esjH3bKI78CtNVqF9oXVLj+r4m3K2grOXiIMA1Jxt9rvcxaupLEnr62D0pCJ5ND1 9XmJgbSVNOK8aflIfL0UujFuVAwi9xiCt7+wdwU7vEY328SAwcE7b5C9tiVY8jRVyILh tVhiaY5/rafDUj16MtXOpAlhE3l2k2ioioCUH7WgSE8VdkkVuyI06b8A9hpZP8PCRKLl DefRDNHGj9D3MMFvlhBr0ji5ezLOhLnPteMDnU8OUbLoOHOdw+6yA+TtFAXm0Z7ObK1N iqJR+UCZNtIAuY8ol/mmsO28Pr3wwLpBPwOYxi26JQMJSjinneVimUkqdnPM4mBfs6us ZhAg== X-Forwarded-Encrypted: i=1; AJvYcCUU/xA8nZEB2BEWacq/D0iQyUxeFa1WLgZEyesM5IITawF62pNvVd4fnvQTJ9Xc8MY+1O4ogWdrFS1bo2s=@vger.kernel.org X-Gm-Message-State: AOJu0YzppurBwg6GgGS3iKjbyn4JVxxJcSd0IY/hXSphhNkNXhjdXHz9 Svxh3X/tntI48SbgZ0LSgNSRzD0xQbsMFxBF+gIcmZf4LpdXBj9Oz6icDuxSr5n4pvBWHA7wqWh +1EEuy4OsbPWMaVQjDmi4nc5eWkv3r7rQ9omJ6tBYcTtOkawNm+aDE9/o/r01M1gRsw8= X-Gm-Gg: ATEYQzxmInToJxZpRiianpXIaUrPkXESdWJqmaMbKHuRRjhkydxKwB8RFahtrAKd7ye oVfRpn0dMlHCpK3maGlL3vVt7+No9D+Z4oJmt5o9ENQygHhWeAdD4qRqWvMomekNAHmfN2xzAnv OG0v+7v5byaKKDtRlSBsYjFg/U2DA7m0jwWsMv3cufwWlxC2rk9DYMDMdLLXGnaJ02qxsJGTW9J xoxxnkuqe7lVMoJRPTXu/8LfxSS8RYEWs/GMcaTyY/gRzpTe/bjv8qnzNEllLr0/XKxh0C+0hR+ L9ApznWAYWXyu2ra63XDZdL3ML//sM0nemyQl+CnCV9vzyNN4VWlxHCMlAH3bwyy1e5Aq/6k/OL zKAFutE5UVsLSO5jJmaTC7AFHxU6ojCE0tXZU/b7bnZh0YXy0UzzXwcP+UsrtVLyGs1dY51hT X-Received: by 2002:a05:6830:2a04:b0:7c7:b4e:edb4 with SMTP id 46e09a7af769-7d52bedf29dmr8946483a34.8.1772004026603; Tue, 24 Feb 2026 23:20:26 -0800 (PST) X-Received: by 2002:a05:6830:2a04:b0:7c7:b4e:edb4 with SMTP id 46e09a7af769-7d52bedf29dmr8946466a34.8.1772004026129; Tue, 24 Feb 2026 23:20:26 -0800 (PST) Received: from hu-jingyw-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7d52d038dcdsm11711730a34.16.2026.02.24.23.20.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Feb 2026 23:20:25 -0800 (PST) From: Jingyi Wang Date: Tue, 24 Feb 2026 23:19:18 -0800 Subject: [PATCH v6 03/10] arm64: dts: qcom: kaanapali: Add TSENS and thermal zones Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260224-knp-dts-misc-v6-3-79d20dab8a60@oss.qualcomm.com> References: <20260224-knp-dts-misc-v6-0-79d20dab8a60@oss.qualcomm.com> In-Reply-To: <20260224-knp-dts-misc-v6-0-79d20dab8a60@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jingyi Wang , 20260114-knp-remoteproc-v4-0-fcf0b04d01af@oss.qualcomm.com, Manaf Meethalavalappu Pallikunhi , Konrad Dybcio X-Mailer: b4 0.15-dev-3d134 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772004019; l=21820; i=jingyi.wang@oss.qualcomm.com; s=20250911; h=from:subject:message-id; bh=57BK10vrSKxDmNIb15WOBEDGWrb50WLKstLYTMBM8Qg=; b=k2DR4fXM935d55nFj6EGV8vtleStbV5gADduNH9msw8f+ZG4Db+WTjcxLFVmKrFilBfuIv089 nfZRt5JNMxkBqFPGAifjb8nXhlU6vxeNc8fKX2C0G3bvlbXxgonKglJ X-Developer-Key: i=jingyi.wang@oss.qualcomm.com; a=ed25519; pk=PSoHZ6KbUss3IW8FPRVMHMK0Jkkr/jV347mBYJO3iLo= X-Authority-Analysis: v=2.4 cv=RNe+3oi+ c=1 sm=1 tr=0 ts=699ea2bb cx=c_pps a=OI0sxtj7PyCX9F1bxD/puw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=gpPq06xVYaF9EkK19g8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=Z1Yy7GAxqfX1iEi80vsk:22 X-Proofpoint-ORIG-GUID: b_zdJul4WuB0VXpnYnlGLvInNdp-jlOn X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjI1MDA3MCBTYWx0ZWRfX8lq7rdoGtnFx Yjk+sVGAXkUuaGKw+M88tiIXXoIrc3S5eZt8OtWzpWheq4V6fsyzmMGHtyL1jCFW5fG+Xbk4rBl aTsmVZ2KuSInhfMRseWA5Wkd8zAFTat8167i/jmzP+ioL080axhBGYnCqU3E7WQSo30NPuTsn/l bZF9/i2XhjIcPzVblQtJfBZ47L/cv+wD2I0mWZ6EgEIfrHgrtGCSicd4dNvM0KO79R6mHOnA4k/ IKCzGWffJfmMquUMoVlPcelsiIRblXUQG4Wyc04hcYr8zjqx+h0VXVCbhAaohGlZuwva73vgovi nJsmNpLr1Muo3pTsjD+fnhqzSKIsEstynLfgucJpJ+MUFLml70qOp8Q/33b6Gv+107vsEsMAZBm ZAGTvvXL6/1MPeLBHA8vN+p76yYYjDZ5QDM/p7reZt1s12MI3CwfmwLH/HBapPpmf4NEJeWn1js YvFIWbfZeKyfeAZEJfw== X-Proofpoint-GUID: b_zdJul4WuB0VXpnYnlGLvInNdp-jlOn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-24_03,2026-02-23_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 phishscore=0 clxscore=1015 spamscore=0 impostorscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602250070 From: Manaf Meethalavalappu Pallikunhi The Kaanapali includes seven TSENS instances, with a total of 55 thermal sensors distributed across various locations on the SoC. The TSENS max/reset threshold is configured to 130=C2=B0C in the hardware. Enable all TSENS instances, and define the thermal zones with a hot trip at 120=C2=B0C and critical trip at 125=C2=B0C. Signed-off-by: Manaf Meethalavalappu Pallikunhi Reviewed-by: Konrad Dybcio Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 1075 +++++++++++++++++++++++++++= ++++ 1 file changed, 1075 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/= qcom/kaanapali.dtsi index df05d204ed41..251e36cf7477 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -2583,6 +2583,90 @@ pdc: interrupt-controller@b220000 { interrupt-controller; }; =20 + tsens0: thermal-sensor@c229000 { + compatible =3D "qcom,kaanapali-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c229000 0x0 0x1000>, + <0x0 0x0c222000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <5>; + #thermal-sensor-cells =3D <1>; + }; + + tsens1: thermal-sensor@c22a000 { + compatible =3D "qcom,kaanapali-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c22a000 0x0 0x1000>, + <0x0 0x0c223000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <12>; + #thermal-sensor-cells =3D <1>; + }; + + tsens2: thermal-sensor@c22b000 { + compatible =3D "qcom,kaanapali-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c22b000 0x0 0x1000>, + <0x0 0x0c224000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <7>; + #thermal-sensor-cells =3D <1>; + }; + + tsens3: thermal-sensor@c22c000 { + compatible =3D "qcom,kaanapali-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c22c000 0x0 0x1000>, + <0x0 0x0c225000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <4>; + #thermal-sensor-cells =3D <1>; + }; + + tsens4: thermal-sensor@c22d000 { + compatible =3D "qcom,kaanapali-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c22d000 0x0 0x1000>, + <0x0 0x0c226000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <8>; + #thermal-sensor-cells =3D <1>; + }; + + tsens5: thermal-sensor@c22e000 { + compatible =3D "qcom,kaanapali-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c22e000 0x0 0x1000>, + <0x0 0x0c227000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <12>; + #thermal-sensor-cells =3D <1>; + }; + + tsens6: thermal-sensor@c22f000 { + compatible =3D "qcom,kaanapali-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c22f000 0x0 0x1000>, + <0x0 0x0c228000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <7>; + #thermal-sensor-cells =3D <1>; + }; + aoss_qmp: power-management@c300000 { compatible =3D "qcom,kaanapali-aoss-qmp", "qcom,aoss-qmp"; reg =3D <0x0 0x0c300000 0x0 0x400>; @@ -4795,6 +4879,997 @@ pdp_tx: scp-sram-section@100 { }; }; =20 + thermal-zones { + cpullc-0-0-thermal { + thermal-sensors =3D <&tsens0 0>; + + trips { + cpullc-0-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpullc-0-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpullc-0-1-thermal { + thermal-sensors =3D <&tsens0 1>; + + trips { + cpullc-0-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpullc-0-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + qmx-0-0-thermal { + thermal-sensors =3D <&tsens0 2>; + + trips { + qmx-0-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + qmx-0-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + qmx-0-1-thermal { + thermal-sensors =3D <&tsens0 3>; + + trips { + qmx-0-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + qmx-0-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + qmx-0-2-thermal { + thermal-sensors =3D <&tsens0 4>; + + trips { + qmx-0-2-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + qmx-0-2-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-0-0-0-thermal { + thermal-sensors =3D <&tsens1 0>; + + trips { + cpu-0-0-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-0-0-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-0-0-1-thermal { + thermal-sensors =3D <&tsens1 1>; + + trips { + cpu-0-0-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-0-0-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-0-1-0-thermal { + thermal-sensors =3D <&tsens1 2>; + + trips { + cpu-0-1-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-0-1-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-0-1-1-thermal { + thermal-sensors =3D <&tsens1 3>; + + trips { + cpu-0-1-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-0-1-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-0-2-0-thermal { + thermal-sensors =3D <&tsens1 4>; + + trips { + cpu-0-2-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-0-2-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-0-2-1-thermal { + thermal-sensors =3D <&tsens1 5>; + + trips { + cpu-0-2-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-0-2-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-0-3-0-thermal { + thermal-sensors =3D <&tsens1 6>; + + trips { + cpu-0-3-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-0-3-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-0-3-1-thermal { + thermal-sensors =3D <&tsens1 7>; + + trips { + cpu-0-3-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-0-3-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-0-4-0-thermal { + thermal-sensors =3D <&tsens1 8>; + + trips { + cpu-0-4-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-0-4-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-0-4-1-thermal { + thermal-sensors =3D <&tsens1 9>; + + trips { + cpu-0-4-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-0-4-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-0-5-0-thermal { + thermal-sensors =3D <&tsens1 10>; + + trips { + cpu-0-5-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-0-5-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-0-5-1-thermal { + thermal-sensors =3D <&tsens1 11>; + + trips { + cpu-0-5-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-0-5-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpullc-1-0-thermal { + thermal-sensors =3D <&tsens2 0>; + + trips { + cpullc-1-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpullc-1-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpullc-1-1-thermal { + thermal-sensors =3D <&tsens2 1>; + + trips { + cpullc-1-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpullc-1-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + qmx-1-0-thermal { + thermal-sensors =3D <&tsens2 2>; + + trips { + qmx-1-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + qmx-1-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + qmx-1-1-thermal { + thermal-sensors =3D <&tsens2 3>; + + trips { + qmx-1-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + qmx-1-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + qmx-1-2-thermal { + thermal-sensors =3D <&tsens2 4>; + + trips { + qmx-1-2-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + qmx-1-2-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + qmx-1-3-thermal { + thermal-sensors =3D <&tsens2 5>; + + trips { + qmx-1-3-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + qmx-1-3-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + qmx-1-4-thermal { + thermal-sensors =3D <&tsens2 6>; + + trips { + qmx-1-4-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + qmx-1-4-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-1-0-0-thermal { + thermal-sensors =3D <&tsens3 0>; + + trips { + cpu-1-0-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-1-0-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-1-0-1-thermal { + thermal-sensors =3D <&tsens3 1>; + + trips { + cpu-1-0-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-1-0-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-1-1-0-thermal { + thermal-sensors =3D <&tsens3 2>; + + trips { + cpu-1-1-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-1-1-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-1-1-1-thermal { + thermal-sensors =3D <&tsens3 3>; + + trips { + cpu-1-1-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-1-1-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nsphvx-0-thermal { + thermal-sensors =3D <&tsens4 0>; + + trips { + nsphvx-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nsphvx-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nsphvx-1-thermal { + thermal-sensors =3D <&tsens4 1>; + + trips { + nsphvx-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nsphvx-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nsphvx-2-thermal { + thermal-sensors =3D <&tsens4 2>; + + trips { + nsphvx-2-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nsphvx-2-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nsphvx-3-thermal { + thermal-sensors =3D <&tsens4 3>; + + trips { + nsphvx-3-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nsphvx-3-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nsphmx-0-thermal { + thermal-sensors =3D <&tsens4 4>; + + trips { + nsphmx-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nsphmx-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nsphmx-1-thermal { + thermal-sensors =3D <&tsens4 5>; + + trips { + nsphmx-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nsphmx-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nsphmx-2-thermal { + thermal-sensors =3D <&tsens4 6>; + + trips { + nsphmx-2-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nsphmx-2-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nsphmx-3-thermal { + thermal-sensors =3D <&tsens4 7>; + + trips { + nsphmx-3-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nsphmx-3-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpuss-0-thermal { + thermal-sensors =3D <&tsens5 0>; + + trips { + gpuss-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpuss-1-thermal { + thermal-sensors =3D <&tsens5 1>; + + trips { + gpuss-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpuss-2-thermal { + thermal-sensors =3D <&tsens5 2>; + + trips { + gpuss-2-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-2-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpuss-3-thermal { + thermal-sensors =3D <&tsens5 3>; + + trips { + gpuss-3-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-3-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpuss-4-thermal { + thermal-sensors =3D <&tsens5 4>; + + trips { + gpuss-4-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-4-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpuss-5-thermal { + thermal-sensors =3D <&tsens5 5>; + + trips { + gpuss-5-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-5-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpuss-6-thermal { + thermal-sensors =3D <&tsens5 6>; + + trips { + gpuss-6-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-6-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpuss-7-thermal { + thermal-sensors =3D <&tsens5 7>; + + trips { + gpuss-7-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-7-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpuss-8-thermal { + thermal-sensors =3D <&tsens5 8>; + + trips { + gpuss-8-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-8-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpuss-9-thermal { + thermal-sensors =3D <&tsens5 9>; + + trips { + gpuss-9-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-9-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpuss-10-thermal { + thermal-sensors =3D <&tsens5 10>; + + trips { + gpuss-10-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-10-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + ddr-thermal { + thermal-sensors =3D <&tsens5 11>; + + trips { + ddr-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + ddr-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + mdmss-0-thermal { + thermal-sensors =3D <&tsens6 0>; + + trips { + mdmss-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + mdmss-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + mdmss-1-thermal { + thermal-sensors =3D <&tsens6 1>; + trips { + mdmss-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + mdmss-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + mdmss-2-thermal { + thermal-sensors =3D <&tsens6 2>; + + trips { + mdmss-2-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + mdmss-2-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + mdmss-3-thermal { + thermal-sensors =3D <&tsens6 3>; + + trips { + mdmss-3-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + mdmss-3-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + camera-0-thermal { + thermal-sensors =3D <&tsens6 4>; + + trips { + camera-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + camera-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + camera-1-thermal { + thermal-sensors =3D <&tsens6 5>; + + trips { + camera-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + camera-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + video-thermal { + thermal-sensors =3D <&tsens6 6>; + + trips { + video-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + video-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + }; + timer { compatible =3D "arm,armv8-timer"; =20 --=20 2.25.1 From nobody Thu Apr 2 07:43:57 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B933B2D876A for ; Wed, 25 Feb 2026 07:20:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772004031; cv=none; b=KcyF+nhTd+uUYIZs0PlpnTWcJhDztE9X+CD0uEseP1LK8FOms1iq2TaBxnCoa+Lox9D7kw6WvjWXmIoSexlN2rNscZq0lAmwvtsb9tDNVKBdU8QT6yJvHmJ4fvk+O2wMgF9L4kgDO+upyKtcFNwJsF69/2hMRgxBSbLSKHxRw/0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772004031; c=relaxed/simple; bh=uUBE3lTqLTzvbb91gqNdaKq9CEjQg0KFuOf7KF+AA3A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=selmTu/WXpI4uYnRHAM06ycuBLPPYapoRLCeTfINe8/I+FtD5kRoFiZ9V2tnxOyBuvDiTHPHXEExLjykPIM4rFS72BKxPdF1Vo4ZRWrYKLmYL1rDKu4jMMlvP0NKpXlT7HoKyEe3A9C+qC9KweHUnBwoYTehSocRrt9+2oN5JRM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=PMYvD/If; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=QMsMim6u; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="PMYvD/If"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="QMsMim6u" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 61P2ah4E2334688 for ; Wed, 25 Feb 2026 07:20:29 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= kD7qqbzSjecWLJSXY1U9bCqCQaTvsPLiVeUYq53PXOE=; b=PMYvD/IfyDpHyVUs qoFFxOsw+Cxr1YNLA+01R0Dgs6G3vyPFURV3VC2YyM5Dwzljnq7JsytIadYaQuvO wPYqkkOo2DmVBfNHI8E7DbtY3VEBFXXrqKA1lbsmizc+S7NxZJckv6Cb+RVRgjpr Php3sm3AW8n68832n4OVs2UA+yBYp6O3F+E7Hzwn8CdLE5z+1IwXP+zXwIS8ejOX 46YXuTEwe7BtDWZTqhMFT9dH5xGUZkHV5lkxzAiyxHMHUiWeQbfgvKoLVETyClbv IOwlbSlWeY6QsLwKEe7DGp3u1VcmVME01x4pJHictETZc8l6geJ9qkh5cH4ur0Ar v0bolg== Received: from mail-ot1-f71.google.com (mail-ot1-f71.google.com [209.85.210.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4chg37tanw-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 25 Feb 2026 07:20:29 +0000 (GMT) Received: by mail-ot1-f71.google.com with SMTP id 46e09a7af769-7d4c6bb79a5so28384626a34.0 for ; Tue, 24 Feb 2026 23:20:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1772004028; x=1772608828; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=kD7qqbzSjecWLJSXY1U9bCqCQaTvsPLiVeUYq53PXOE=; b=QMsMim6u93U9RDAyE0677qEfhgjrROTL3A/x9oxA9P2z3tjqE8gTO57/6t+t1RryAY NYVj44/FEHjlKTCT0t/0hiaR9Eh2hcONceBW0zRHYoQ5/ERjWo6VY9YwuMPcvg7wmWmP oQ6AMoVvt2/Xie1E/Z9EL+hPwQkXtXeAWxcwuT7YEC5MqzTCDK1KXfZJcgqy3I9AHNEU hwYrz74jt+VPMP6aPQ3Dpddft5ymXlHcPjyz46KjEQyD1j4dpFdJ8c26p7WnbPRg2CJu 3bba+niy159JNm0Q+ISNF0QYuLpzQjqSoEv3lzopx1TiJh+aafQ6nfI1SArseC7bmFdJ SJBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772004028; x=1772608828; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=kD7qqbzSjecWLJSXY1U9bCqCQaTvsPLiVeUYq53PXOE=; b=VxZFpAjiPk73LMm0yFjecD7kq7wH6dEcZX/UED9EP9oe+6St4Gi+2qINyhnU/6qSZ/ q4YBxFHSo5HkPLnUoRrcoGdxWgdeQ6iwmlclvPERkOKPZ5JmOGdf4i83rXobu6jJNKG6 PmyGndPElh0FU87vQdp2CIRiZiMptkMmCgkaJSttN3MKvDf2F1tpueaKuFW96/M1PCgi vtcvba7oKvbN1hcDmjSZ4vnkwoLQB6fc+Z2e5ZtzYesuQe5wPaiqsgMi3bSFpitjtkv6 QhjqNztedimj55/gACrv2CjRTU96HHaIlAh9JVC8CMaVjUbzynHAPYzP5vCjrha78Ggp Zliw== X-Forwarded-Encrypted: i=1; AJvYcCWe7RyagZJW9OTQvlD9KctYvGf/iQDfu1yphXITCEj99G0yEfL30Ov366x+Mx1dbAR6aEBB+UfVm2dZVpg=@vger.kernel.org X-Gm-Message-State: AOJu0YySg5gQmW/0qyGDUOTXKXQrdAjxpRAddr7IircdiqrYkRlVnNQs lq26MzMXVmjH/qVukZKRvPYjlVe5LQ60BPo1Vc0b7TAZL/RaIxW2xIf7td+XqfZyndqMtkBdERa 2JIBh7dwjJHbYj14PtGKnTN1WNi8TATxFKL/EsoaZtaiJAalQhOCGT0Yu/F6okNRtftI= X-Gm-Gg: ATEYQzwHCpfoicBCThRanofAzYXUNnl9JfT3dQzHjgoElrf7oWb4iW0Kokota1yVZis oG2PuUmuDbPFhfIrp1ZPyZPS51XtUYC5PBrNwnd1SDdVzDxn1yVfhnmAIlsfRpbRlYha8CVh/Jn bRQCH8r98d3o+qxQN/E/zcAwVxq17wjgZ0U+IOsvj2fnpAOh8lm93LN+EbbT8oW0Q6/YNsdOaKC FqfC/ufJsx2wmJhd+hgO0xlcQS4oEZc1rmKYiUSaUIjEu2CYgFXp8BhtcIyxVGZLjNgBgoYngpb zXh/Z/MKPSXbimpikmTc2uhUL+uEhyJzR57oEq8fXnswavNBlRFLlrtMiVRteohumFWwtyONrEq WILtunbB6dRFoYAuHyYyOVSUiIS6SHYxzY60RYwqtiTAV+WOnj7L1KUEmUQNlDA470/hhl0ip X-Received: by 2002:a05:6830:82cb:b0:7d1:94d0:e8f1 with SMTP id 46e09a7af769-7d57a17dfd2mr759841a34.15.1772004028234; Tue, 24 Feb 2026 23:20:28 -0800 (PST) X-Received: by 2002:a05:6830:82cb:b0:7d1:94d0:e8f1 with SMTP id 46e09a7af769-7d57a17dfd2mr759827a34.15.1772004027862; Tue, 24 Feb 2026 23:20:27 -0800 (PST) Received: from hu-jingyw-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7d52d038dcdsm11711730a34.16.2026.02.24.23.20.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Feb 2026 23:20:27 -0800 (PST) From: Jingyi Wang Date: Tue, 24 Feb 2026 23:19:19 -0800 Subject: [PATCH v6 04/10] arm64: dts: qcom: kaanapali: Add ADSP and CDSP for Kaanapali SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260224-knp-dts-misc-v6-4-79d20dab8a60@oss.qualcomm.com> References: <20260224-knp-dts-misc-v6-0-79d20dab8a60@oss.qualcomm.com> In-Reply-To: <20260224-knp-dts-misc-v6-0-79d20dab8a60@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jingyi Wang , 20260114-knp-remoteproc-v4-0-fcf0b04d01af@oss.qualcomm.com, Kumari Pallavi , Dmitry Baryshkov X-Mailer: b4 0.15-dev-3d134 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772004019; l=9654; i=jingyi.wang@oss.qualcomm.com; s=20250911; h=from:subject:message-id; bh=uUBE3lTqLTzvbb91gqNdaKq9CEjQg0KFuOf7KF+AA3A=; b=TPhEdC8PRlMbzpvA6gpew8SsCmAEDEi8Jkkv8I+YgCXGtIoh19U++/cGBbiWdlUbclFPb3inK ivNwrcBZNmSCybj5fK2DT6i0hMPmjkUUL/RvTIy7Gwrkz4oVc6fM/Nv X-Developer-Key: i=jingyi.wang@oss.qualcomm.com; a=ed25519; pk=PSoHZ6KbUss3IW8FPRVMHMK0Jkkr/jV347mBYJO3iLo= X-Authority-Analysis: v=2.4 cv=br1BxUai c=1 sm=1 tr=0 ts=699ea2bd cx=c_pps a=OI0sxtj7PyCX9F1bxD/puw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=vejemSqAVpqrvhYTndAA:9 a=QEXdDO2ut3YA:10 a=Z1Yy7GAxqfX1iEi80vsk:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjI1MDA3MCBTYWx0ZWRfX3Z910WW24oAJ T509Dy0x0f0P2YcC3sv9icrA4mc8dmUMK981tvEpYekwiXZS+7sDHqKpGP67sbaB7XjXCW2Hqlw BrOKzi93Ogf+eUq+fYNSK7YA78686sZVRW4wXl+ntcn/lz45GVLESPZ0G50HqIWBe322rGSuiMK zxTRYGNl9BRI+1+tUdk4y+7fV+tzL07bgYwsCRbIwDIwNBhYM+jJ0OqLMsG2WYvGk5XBOO2Z2e7 CtBN3PI8xExZ43dn5Kz+3m6ot1HORswVwJzc8Jm1p4B6iAto91egdMa6YKnvUNQ+k0U+Er0l6vB 2DhNJgli2N6yQAJrXwuXLhFlPaxjaSRn9vC9a6e5HldkpFgvXUnzhy1sP/JQr+am5UR4JRnMk4z BuDiZDoFbLZhVdJjEb1OadbUxy7H6LEiM606rBEMXglGwNcguJE+kOmDPagcEVgN4x6oaLS0OEA dKRP5YZT345s+QGAVzw== X-Proofpoint-ORIG-GUID: sc8IWhceCXkeESagiD7qE3zpLYxogWN0 X-Proofpoint-GUID: sc8IWhceCXkeESagiD7qE3zpLYxogWN0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-24_03,2026-02-23_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 clxscore=1015 impostorscore=0 adultscore=0 bulkscore=0 phishscore=0 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602250070 Add remoteproc PAS loader for ADSP and CDSP with its SMP2P and fastrpc nodes. Co-developed-by: Kumari Pallavi Signed-off-by: Kumari Pallavi Reviewed-by: Dmitry Baryshkov Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 314 ++++++++++++++++++++++++++++= ++++ 1 file changed, 314 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/= qcom/kaanapali.dtsi index 251e36cf7477..c8f61200f261 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -443,6 +443,58 @@ rmtfs_mem: rmtfs@d7c00000 { }; }; =20 + smp2p-adsp { + compatible =3D "qcom,smp2p"; + + interrupts-extended =3D <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes =3D <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem =3D <443>, <429>; + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-cdsp { + compatible =3D "qcom,smp2p"; + + interrupts-extended =3D <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes =3D <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem =3D <94>, <432>; + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + soc: soc@0 { compatible =3D "simple-bus"; =20 @@ -2478,6 +2530,111 @@ tcsr: clock-controller@1fc0000 { #reset-cells =3D <1>; }; =20 + remoteproc_adsp: remoteproc@6800000 { + compatible =3D "qcom,kaanapali-adsp-pas", "qcom,sm8550-adsp-pas"; + reg =3D <0x0 0x06800000 0x0 0x10000>; + + interrupts-extended =3D <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + interconnects =3D <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWA= YS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + power-domains =3D <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; + power-domain-names =3D "lcx", + "lmx"; + + memory-region =3D <&adspslpi_mem>, <&q6_adsp_dtb_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_adsp_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts-extended =3D <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes =3D <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + qcom,remote-pid =3D <2>; + + label =3D "lpass"; + + fastrpc { + compatible =3D "qcom,kaanapali-fastrpc"; + qcom,glink-channels =3D "fastrpcglink-apps-dsp"; + label =3D "adsp"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + compute-cb@3 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <3>; + + iommus =3D <&apps_smmu 0x1003 0x80>, + <&apps_smmu 0x1043 0x20>; + dma-coherent; + }; + + compute-cb@4 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <4>; + + iommus =3D <&apps_smmu 0x1004 0x80>, + <&apps_smmu 0x1044 0x20>; + dma-coherent; + }; + + compute-cb@5 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <5>; + + iommus =3D <&apps_smmu 0x1005 0x80>, + <&apps_smmu 0x1045 0x20>; + dma-coherent; + }; + + compute-cb@6 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <6>; + + iommus =3D <&apps_smmu 0x1006 0x80>, + <&apps_smmu 0x1046 0x20>; + dma-coherent; + }; + + compute-cb@7 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <7>; + + iommus =3D <&apps_smmu 0x1007 0x40>, + <&apps_smmu 0x1067 0x0>, + <&apps_smmu 0x1087 0x0>; + dma-coherent; + }; + }; + }; + }; + lpass_lpiaon_noc: interconnect@7400000 { compatible =3D "qcom,kaanapali-lpass-lpiaon-noc"; reg =3D <0x0 0x07400000 0x0 0x19080>; @@ -4760,6 +4917,163 @@ nsp_noc: interconnect@260c0000 { #interconnect-cells =3D <2>; }; =20 + remoteproc_cdsp: remoteproc@26300000 { + compatible =3D "qcom,kaanapali-cdsp-pas", "qcom,sm8550-cdsp-pas"; + reg =3D <0x0 0x26300000 0x0 0x10000>; + + interrupts-extended =3D <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + interconnects =3D <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + power-domains =3D <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_NSP>; + power-domain-names =3D "cx", + "mxc", + "nsp"; + + memory-region =3D <&cdsp_mem>, <&q6_cdsp_dtb_mem>; + qcom,qmp =3D <&aoss_qmp>; + qcom,smem-states =3D <&smp2p_cdsp_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + qcom,remote-pid =3D <5>; + label =3D "cdsp"; + + fastrpc { + compatible =3D "qcom,kaanapali-fastrpc"; + qcom,glink-channels =3D "fastrpcglink-apps-dsp"; + label =3D "cdsp"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + compute-cb@1 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <1>; + iommus =3D <&apps_smmu 0x19c1 0x0>, + <&apps_smmu 0x1961 0x0>, + <&apps_smmu 0x0c21 0x0>, + <&apps_smmu 0x0c01 0x40>; + dma-coherent; + }; + + compute-cb@2 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <2>; + iommus =3D <&apps_smmu 0x1962 0x0>, + <&apps_smmu 0x0c02 0x20>, + <&apps_smmu 0x0c42 0x0>, + <&apps_smmu 0x19c2 0x0>; + dma-coherent; + }; + + compute-cb@3 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <3>; + iommus =3D <&apps_smmu 0x1963 0x0>, + <&apps_smmu 0x0c23 0x0>, + <&apps_smmu 0x0c03 0x40>, + <&apps_smmu 0x19c3 0x0>; + dma-coherent; + }; + + compute-cb@4 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <4>; + iommus =3D <&apps_smmu 0x1964 0x0>, + <&apps_smmu 0x0c44 0x0>, + <&apps_smmu 0x0c04 0x20>, + <&apps_smmu 0x19c4 0x0>; + dma-coherent; + }; + + compute-cb@5 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <5>; + iommus =3D <&apps_smmu 0x1965 0x0>, + <&apps_smmu 0x0c45 0x0>, + <&apps_smmu 0x0c05 0x20>, + <&apps_smmu 0x19c5 0x0>; + dma-coherent; + }; + + compute-cb@6 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <6>; + iommus =3D <&apps_smmu 0x1966 0x0>, + <&apps_smmu 0x0c06 0x20>, + <&apps_smmu 0x0c46 0x0>, + <&apps_smmu 0x19c6 0x0>; + dma-coherent; + }; + + compute-cb@7 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <7>; + iommus =3D <&apps_smmu 0x1967 0x0>, + <&apps_smmu 0x0c27 0x0>, + <&apps_smmu 0x0c07 0x40>, + <&apps_smmu 0x19c7 0x0>; + dma-coherent; + }; + + compute-cb@8 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <8>; + iommus =3D <&apps_smmu 0x1968 0x0>, + <&apps_smmu 0x0c08 0x20>, + <&apps_smmu 0x0c48 0x0>, + <&apps_smmu 0x19c8 0x0>; + dma-coherent; + }; + + compute-cb@12 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <12>; + iommus =3D <&apps_smmu 0x196c 0x0>, + <&apps_smmu 0x0c2c 0x00>, + <&apps_smmu 0x0c0c 0x40>, + <&apps_smmu 0x19cc 0x0>; + dma-coherent; + }; + + compute-cb@13 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <13>; + iommus =3D <&apps_smmu 0x196d 0x0>, + <&apps_smmu 0x0c0d 0x40>, + <&apps_smmu 0x0c2e 0x0>, + <&apps_smmu 0x0c2d 0x0>, + <&apps_smmu 0x19cd 0x0>; + dma-coherent; + }; + }; + }; + }; + /* Cluster 0 */ pmu@310b3400 { compatible =3D "qcom,kaanapali-cpu-bwmon", "qcom,sdm845-bwmon"; --=20 2.25.1 From nobody Thu Apr 2 07:43:57 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D46762FF161 for ; Wed, 25 Feb 2026 07:20:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772004033; cv=none; b=XTxXhyan6LC93MdGIuopMGMnfkQITOnQZ3wvm67SnvJKsrNFFu+BK9BNd2tf4D+8NCsyw/UXjfRoAqHgHNadsHDFn6MWxS8E0EXgfv9uGKxDl5+LXJtE0ai6PuKo0FVsasCW6L8UlG9LhmdQCycNJpF1ot7VQB/1nIuFxk55/og= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772004033; c=relaxed/simple; bh=MApLqBKXhXejmcG94AbTIvG69J2wT1WnPrYiSd9DCOI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iBc+VcLpsptP9ZdgaF67d9LuB4rRu6uBAck4gUMh0+pnbR+lurA2u4LFG0C0IOcT25liDP/VUFXRJhEz9y/AEVQRwaQsF0A2iXluVhFtzdzd+fmH2HQE5bkYbBzBTx7O8V37XdEMPKwRBTZzLn9RkAp5feAuPJFJyMGwnsGsQ9U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Y2gLCmHS; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=JwkSym3l; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Y2gLCmHS"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="JwkSym3l" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 61P02GLE4044338 for ; Wed, 25 Feb 2026 07:20:31 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= POR2/I/DB9Wo/nCazWio07fbKXwg21zl4yZCSev6rYk=; b=Y2gLCmHSBzIwwfVr VUVailUoQEELFRH2tACQmU4PyvCAsrNq7PW09FnXNyZI5MYuY9jvgheQBM4lEKM3 9y/9rAo+QP4jdMHTuVzc1pixEOgo9HKoRxGyphldxjygTpXS4lTOIIeVaoFAQs4k NWPCo5Z9eHtrArg13MC7FGvjk2spccSJVDN/zh39CtVQfhO3+i5fct6LZo5mXeYo t0fe+/a9N7ozlzxSeeYQrKo2POe9/aaQrp/Ok+jol8H/NJ9ArKSy2vD8YPoK96pI sQQqvshXksKbH4wpRnwrQUUn6wBMTaD2SlyUSCF2qTLXd/9IMud5IpSV0nbjyZcn rWejiA== Received: from mail-ot1-f71.google.com (mail-ot1-f71.google.com [209.85.210.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4chexejjm5-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 25 Feb 2026 07:20:30 +0000 (GMT) Received: by mail-ot1-f71.google.com with SMTP id 46e09a7af769-7d195fe3eb4so95081717a34.3 for ; Tue, 24 Feb 2026 23:20:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1772004030; x=1772608830; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=POR2/I/DB9Wo/nCazWio07fbKXwg21zl4yZCSev6rYk=; b=JwkSym3lcWg6XSw0w28PyEFnHNEwxY0iSTsARgcVOo6xv+qTNdjPoMABxC8UvcAGqS WY5Hlo/1Kx+bB4XhLTjY3DEsmOsCTBoux8MlHgAA+p6B8CG5SbLgxQoM4niry6RLXOHa pIn6qnqM3BBMJR1aLM7nzoOsWWArdvZ51+9SQCReTh6YQy9yigdUYeaQbVrzMbrOULla /chf/OPQp7+WvLBjEXEUgAdUeJ9jU8VZxK62ZJpNHYrIVtRa5MEhSviaKs9/mYrBeYnc cqB0bFXtFXrfDQOiw2oUHW91L/oJAyqLfl6bNQJ7MOVTJmXfPt0ycDbcpAcQGZ9/Lkx0 vrvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772004030; x=1772608830; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=POR2/I/DB9Wo/nCazWio07fbKXwg21zl4yZCSev6rYk=; b=cyoMYe2dA4Hz0x+7GOXjQhXJwbaHZHSlhqtpnx46byszx0D8SpiwHjtycv1jRzE+wO YBtZzc3mU/BIVj96BPqTQ9mlGZqXRtJ5LdQxSAF7OVm5MrWzXea49n+ARfx/pMVK3hxA NzSWrEhvfBGpA6CKJmdB2waAqJnABhF9p2+UmSmsmAuFvwCEfyYXQvMFN2wM/OFZ/19M lXEI30kZz+hqcN0+GQgK+fPOLw2P+sJOf+TlUlPWKlmgK8nnTJD/RXDQHJGneGGrtZvJ ZDCxwcSulFhFPrbxF0S7EIq+dkfZK4g+tFu+7F5j8azog9KLNQvhVtyMkVSwso5v4IAs TBvw== X-Forwarded-Encrypted: i=1; AJvYcCWLlfHnG78nm+nYGqptMe0l8wlVgFUi+/Jeb5uaHT0nAYecNwg4uhcKx1uMzYHmyLOk8mYuTrGKGLR7JEM=@vger.kernel.org X-Gm-Message-State: AOJu0YypoBq5qpKc9oZBYVdJ/VXKQIiJ9Z+Rd4yvkOFQHeJJN6EUvlHY ybt9ZFkROozMpTymuql5Ceo/H9MCJkF0KmjPAgnhFwmQG7e4Fxhhddq1FPm46FYt9Cib84ZqCEG gzlKJOCf6im4OBTaQebucU53F+HgM+6UEzKUpc6hJv5VFTetwxtJlMa89/ObOfw+LEERypSVDAN OMpA== X-Gm-Gg: ATEYQzyEbVGZDrmoaJNzy3DmC0SNAGAIqCJaa+8ioAd7AKVwwcTxvtzVATSIU9eCXek y+u2imfnvQr/m9ROfZtLBleGmX5G9kSySh+owQOTXG3aDuHwel5GG0YwI2NizFj4S4UAkWOqkGG is4UDy/skj5yjtHLfocJshGqenAkumyMH5fspddUUwq9K/3Zf3/mUA+fxEkGNkI5PaQycz2kaxq IO30HZMk1I/10UTUElV3iqZcFjA92+ayjiYnAZ7QtXnVym5MJIK9CqSs9OPLOma0sEYI6y79YH9 iINT4rOnBINAN0wGL9nRd2EuuiGonoLcCfsFqlWqQpzEUDPM+887PgSDitmO+K6Abt466g64KGY 8RnJqBoSKWMg+abzIo+f7YpGFgbJO8wU1Zdlv0K0nZZppDVRw/bWB4r7idyDFhLUZTgmMnruh X-Received: by 2002:a05:6830:81d6:b0:7cf:d4b2:d679 with SMTP id 46e09a7af769-7d52be381dbmr10186925a34.12.1772004029912; Tue, 24 Feb 2026 23:20:29 -0800 (PST) X-Received: by 2002:a05:6830:81d6:b0:7cf:d4b2:d679 with SMTP id 46e09a7af769-7d52be381dbmr10186905a34.12.1772004029460; Tue, 24 Feb 2026 23:20:29 -0800 (PST) Received: from hu-jingyw-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7d52d038dcdsm11711730a34.16.2026.02.24.23.20.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Feb 2026 23:20:28 -0800 (PST) From: Jingyi Wang Date: Tue, 24 Feb 2026 23:19:20 -0800 Subject: [PATCH v6 05/10] arm64: dts: qcom: kaanapali: Add support for audio Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260224-knp-dts-misc-v6-5-79d20dab8a60@oss.qualcomm.com> References: <20260224-knp-dts-misc-v6-0-79d20dab8a60@oss.qualcomm.com> In-Reply-To: <20260224-knp-dts-misc-v6-0-79d20dab8a60@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jingyi Wang , 20260114-knp-remoteproc-v4-0-fcf0b04d01af@oss.qualcomm.com, Prasad Kumpatla , Konrad Dybcio , Abel Vesa X-Mailer: b4 0.15-dev-3d134 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772004019; l=13947; i=jingyi.wang@oss.qualcomm.com; s=20250911; h=from:subject:message-id; bh=ZsxbnrrxiiXQ8Ww+LXrKoImfngj3dqkfI9eUHCQCys0=; b=ONFMdb5YIsS9VqY7rOWFYBoKQ8ZAhLcQnuXDhcQOG70Af2pZLFcG+MYb0QZCmdCVvO9QW7dsj lKJVRfVx3a0BgKhteTQR2fadc5Z5Wjdo0ru7eKBCzKOy8yuxEhNrE+m X-Developer-Key: i=jingyi.wang@oss.qualcomm.com; a=ed25519; pk=PSoHZ6KbUss3IW8FPRVMHMK0Jkkr/jV347mBYJO3iLo= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjI1MDA3MCBTYWx0ZWRfX71Y9pJnh6xA5 B3/c7oR7c/eMoYtW9TOrzMvp/0evNnhclXPuTvJ43KT4rYPV9gNjHhb7YTReKZUd0LErgogNNOr c2IbY9bBsGZgjm6ZI1oOrkB8lve4B9gjw+o1aaNLJsytkFCO+9Q6bZc6OGov413C2VLBfBoWf99 2m2AnUP2I/s+MYVFuTjrDuQ/bVqm64xx5v1ZB+zwRMH2/igKhuwkShGnCCrVZ6mABlEwzriTZkL j3kqEW/8G0k2nQqFarMcOKWanAtRFObJFJU1XAnr/zClDgDBtEVXKo2NiUiIOV9hvyT5Rja6Nqc BzgcCvzwYEJagadTFftDmtp3kDOJGjl+DgYHnFNqUgGDAgOpoFlQcEQ8VdleWoHesodmc8TzPVM aM/l4oHKwZLANmqOfrQpCeUpsD4oyuxWG+F0YogCL14PNqI+qZ9DGqopp0VUH8iCp4/JchGXyEc Ju0d992x7hyJyizQT8w== X-Authority-Analysis: v=2.4 cv=V85wEOni c=1 sm=1 tr=0 ts=699ea2be cx=c_pps a=OI0sxtj7PyCX9F1bxD/puw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=fOvlSJoLLuNaJOMVFRMA:9 a=QEXdDO2ut3YA:10 a=Z1Yy7GAxqfX1iEi80vsk:22 X-Proofpoint-GUID: agAA6u_B1sDRVQvu-a7N3erAebynJQbc X-Proofpoint-ORIG-GUID: agAA6u_B1sDRVQvu-a7N3erAebynJQbc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-24_03,2026-02-23_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 spamscore=0 suspectscore=0 phishscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602250070 From: Prasad Kumpatla Introduce audio support for Kaanapali SoC by adding LPASS macro codecs, TLMM pin controller and SoundWire controller with similar hardware implementation to SM8750 platform. Also add GPR (Generic Pack Router) node along with support for APM (Audio Process Manager) and PRM (Proxy Resource Manager) audio services. Signed-off-by: Prasad Kumpatla Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 367 ++++++++++++++++++++++++++++= ++++ 1 file changed, 367 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/= qcom/kaanapali.dtsi index c8f61200f261..d9880a87a928 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -16,7 +16,9 @@ #include #include #include +#include #include +#include =20 #include "kaanapali-ipcc.h" =20 @@ -2632,9 +2634,212 @@ compute-cb@7 { dma-coherent; }; }; + + gpr { + compatible =3D "qcom,gpr"; + qcom,glink-channels =3D "adsp_apps"; + qcom,domain =3D ; + qcom,intents =3D <512 20>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + q6apm: service@1 { + compatible =3D "qcom,q6apm"; + reg =3D ; + #sound-dai-cells =3D <0>; + qcom,protection-domain =3D "avs/audio", + "msm/adsp/audio_pd"; + + q6apmbedai: bedais { + compatible =3D "qcom,q6apm-lpass-dais"; + #sound-dai-cells =3D <1>; + }; + + q6apmdai: dais { + compatible =3D "qcom,q6apm-dais"; + iommus =3D <&apps_smmu 0x1001 0x80>, + <&apps_smmu 0x1041 0x20>; + }; + }; + + q6prm: service@2 { + compatible =3D "qcom,q6prm"; + reg =3D ; + qcom,protection-domain =3D "avs/audio", + "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible =3D "qcom,q6prm-lpass-clocks"; + #clock-cells =3D <2>; + }; + }; + }; }; }; =20 + lpass_wsa2macro: codec@6aa0000 { + compatible =3D "qcom,kaanapali-lpass-wsa-macro", + "qcom,sm8550-lpass-wsa-macro"; + reg =3D <0x0 0x06aa0000 0x0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "wsa2-mclk"; + #sound-dai-cells =3D <1>; + }; + + swr3: soundwire@6ab0000 { + compatible =3D "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0"; + reg =3D <0 0x06ab0000 0 0x10000>; + interrupts =3D ; + clocks =3D <&lpass_wsa2macro>; + clock-names =3D "iface"; + label =3D "WSA2"; + + pinctrl-0 =3D <&wsa2_swr_active>; + pinctrl-names =3D "default"; + + qcom,din-ports =3D <4>; + qcom,dout-ports =3D <9>; + + qcom,ports-sinterval =3D /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18= f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; + qcom,ports-offset1 =3D /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x= ff 0xff 0x06 0x0d 0xff 0x00>; + qcom,ports-offset2 =3D /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0x= ff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xf= f 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff= 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-word-length =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08= 0xff 0xff 0xff 0xff 0xff 0x18>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 = 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + status =3D "disabled"; + }; + + lpass_rxmacro: codec@6ac0000 { + compatible =3D "qcom,kaanapali-lpass-rx-macro", "qcom,sm8550-lpass-rx-m= acro"; + reg =3D <0x0 0x06ac0000 0x0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + }; + + swr1: soundwire@6ad0000 { + compatible =3D "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0"; + reg =3D <0 0x06ad0000 0 0x10000>; + interrupts =3D ; + clocks =3D <&lpass_rxmacro>; + clock-names =3D "iface"; + label =3D "RX"; + + pinctrl-0 =3D <&rx_swr_active>; + pinctrl-names =3D "default"; + + qcom,din-ports =3D <1>; + qcom,dout-ports =3D <11>; + + qcom,ports-sinterval =3D /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xf= f 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-offset1 =3D /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0x= ff 0xff 0xff 0xff 0xff>; + qcom,ports-offset2 =3D /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0x= ff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xf= f 0xff 0xff 0xff 0xff>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff= 0xff 0xff 0xff 0xff>; + qcom,ports-word-length =3D /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff= 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 = 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x0= 0 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xf= f 0xff 0xff 0xff 0xff 0xff>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + status =3D "disabled"; + }; + + lpass_txmacro: codec@6ae0000 { + compatible =3D "qcom,kaanapali-lpass-tx-macro", "qcom,sm8550-lpass-tx-m= acro"; + reg =3D <0x0 0x06ae0000 0x0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + }; + + lpass_wsamacro: codec@6b00000 { + compatible =3D "qcom,kaanapali-lpass-wsa-macro", + "qcom,sm8550-lpass-wsa-macro"; + reg =3D <0x0 0x06b00000 0x0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + }; + + swr0: soundwire@6b10000 { + compatible =3D "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0"; + reg =3D <0 0x06b10000 0 0x10000>; + interrupts =3D ; + clocks =3D <&lpass_wsamacro>; + clock-names =3D "iface"; + label =3D "WSA"; + + pinctrl-0 =3D <&wsa_swr_active>; + pinctrl-names =3D "default"; + + qcom,din-ports =3D <4>; + qcom,dout-ports =3D <9>; + + qcom,ports-sinterval =3D /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18= f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; + qcom,ports-offset1 =3D /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x= ff 0xff 0x06 0x0d 0xff 0x00>; + qcom,ports-offset2 =3D /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0x= ff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xf= f 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff= 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-word-length =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08= 0xff 0xff 0xff 0xff 0xff 0x18>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 = 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + status =3D "disabled"; + }; + lpass_lpiaon_noc: interconnect@7400000 { compatible =3D "qcom,kaanapali-lpass-lpiaon-noc"; reg =3D <0x0 0x07400000 0x0 0x19080>; @@ -2649,6 +2854,168 @@ lpass_lpicx_noc: interconnect@7420000 { #interconnect-cells =3D <2>; }; =20 + swr2: soundwire@7630000 { + compatible =3D "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0"; + reg =3D <0 0x07630000 0 0x10000>; + interrupts-extended =3D <&intc GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 40 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "core", "wakeup"; + clocks =3D <&lpass_txmacro>; + clock-names =3D "iface"; + label =3D "TX"; + + pinctrl-0 =3D <&tx_swr_active>; + pinctrl-names =3D "default"; + + qcom,din-ports =3D <4>; + qcom,dout-ports =3D <0>; + qcom,ports-sinterval-low =3D /bits/ 8 <0x01 0x01 0x03 0x03>; + qcom,ports-offset1 =3D /bits/ 8 <0x00 0x00 0x01 0x01>; + qcom,ports-offset2 =3D /bits/ 8 <0x00 0x00 0x00 0x00>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-word-length =3D /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0x01 0x02 0x00 0x00>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + status =3D "disabled"; + }; + + lpass_vamacro: codec@7660000 { + compatible =3D "qcom,kaanapali-lpass-va-macro", "qcom,sm8550-lpass-va-m= acro"; + reg =3D <0 0x07660000 0 0x2000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names =3D "mclk", "macro", "dcodec"; + + #clock-cells =3D <0>; + clock-output-names =3D "fsgen"; + #sound-dai-cells =3D <1>; + }; + + lpass_tlmm: pinctrl@7760000 { + compatible =3D "qcom,sm8750-lpass-lpi-pinctrl", + "qcom,sm8650-lpass-lpi-pinctrl"; + reg =3D <0 0x07760000 0 0x20000>; + + clocks =3D <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names =3D "core", "audio"; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&lpass_tlmm 0 0 23>; + + tx_swr_active: tx-swr-active-state { + clk-pins { + pins =3D "gpio0"; + function =3D "swr_tx_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio1", "gpio2", "gpio14"; + function =3D "swr_tx_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + rx_swr_active: rx-swr-active-state { + clk-pins { + pins =3D "gpio3"; + function =3D "swr_rx_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio4", "gpio5"; + function =3D "swr_rx_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + dmic01_default: dmic01-default-state { + clk-pins { + pins =3D "gpio6"; + function =3D "dmic1_clk"; + drive-strength =3D <8>; + output-high; + }; + + data-pins { + pins =3D "gpio7"; + function =3D "dmic1_data"; + drive-strength =3D <8>; + input-enable; + }; + }; + + dmic23_default: dmic23-default-state { + clk-pins { + pins =3D "gpio8"; + function =3D "dmic2_clk"; + drive-strength =3D <8>; + output-high; + }; + + data-pins { + pins =3D "gpio9"; + function =3D "dmic2_data"; + drive-strength =3D <8>; + input-enable; + }; + }; + + wsa_swr_active: wsa-swr-active-state { + clk-pins { + pins =3D "gpio10"; + function =3D "wsa_swr_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio11"; + function =3D "wsa_swr_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + wsa2_swr_active: wsa2-swr-active-state { + clk-pins { + pins =3D "gpio15"; + function =3D "wsa2_swr_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio16"; + function =3D "wsa2_swr_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + }; + lpass_ag_noc: interconnect@7f40000 { compatible =3D "qcom,kaanapali-lpass-ag-noc"; reg =3D <0x0 0x07f40000 0x0 0xe080>; --=20 2.25.1 From nobody Thu Apr 2 07:43:57 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21958305048 for ; Wed, 25 Feb 2026 07:20:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772004034; cv=none; b=RuqGUH90nvjz0qw95faOj8fd6VxHhx/T+ytoAO5FEo/YLpch0+ADbjrSLXbnJiUrLZiCJQ3BfDYf/wIsGZGzWvJF1dI9gtm7c1qx0QOA99zyqjjVvtP1MMo0rq5e8/B3P8AcYXFSSoUMuPM4ABOwizg6hh2poVZyGYWEHw5nl4Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772004034; c=relaxed/simple; bh=tW4K+WgSJyLZfWN+10XcL4+EBYZ+0pCMvRvFk+AoOeU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mqlgnsa5cAkLmuIoAwU0sZuituuK+Fb5JF6aDn8e2UV/LNM+caXXZtM0e+G6WIWmC2lAvFV9gKI2iMN6Oo62v3hDZYwUlHwhCCufCsAfK9EeBkUMBZeGRqbUggL/6zHaqw/AAGW+6eUiTV5TieDYvZ2yQ9ieOf+XbwO4ZNZTlaA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=A5EiotAL; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=hLVOo5Wj; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="A5EiotAL"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="hLVOo5Wj" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 61OL5VBM2432693 for ; Wed, 25 Feb 2026 07:20:32 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= kUqCiBd6ikhwKifJPE4u1pdAWzTgL175SpkaOSzjkt4=; b=A5EiotALzfwhjsvo 5Ns9Zx1yhWozatVMAE5ucVbvosaWXrhCkfpgCZwm9K3E7gglUUfUfy1Al0fw5JC0 +NElVgh0/PfSdzl82X+0merDkVEq/jG/XyMvbBjcKPoTzOuJi6nIZnk2L8JvPQrn fMVd5EVLaYHeveQLRjcy2r3DWflLiyot7LG6uMAIDnRK3p6L94ZW+IjQcfjVrXOD ZMbHexWSlPIDSPdrG3/pcyc0JPTgCHQ6FAWzaEtJaR3bWNgNCOHp+6vNJmVF/hM+ k9G/RXa3RjMZb0FVOjeJSNFRPbDij+KvhV0N5yywOwWdFflXxGbdbvL7Jqq/BPpm 4wUMsQ== Received: from mail-ot1-f69.google.com (mail-ot1-f69.google.com [209.85.210.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4chekjaqex-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 25 Feb 2026 07:20:32 +0000 (GMT) Received: by mail-ot1-f69.google.com with SMTP id 46e09a7af769-7d4c3d9dd70so94732309a34.1 for ; Tue, 24 Feb 2026 23:20:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1772004031; x=1772608831; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=kUqCiBd6ikhwKifJPE4u1pdAWzTgL175SpkaOSzjkt4=; b=hLVOo5WjQiX/js+3JH+GFiYnXWlSxlGZTIsysTC2jDbmIV3LnbNsHPD+PvErBK4EmM 3mE08uxVQzx3xEfNP8J8LpbS2yPiBThbbpcZBT4YOleX30bXb3zGkxt2FZTVVwGyrLYL TTiCr4O+SxVu2q0WahpX4V9mhjId4eH1qXvjyyGNQPJPyxqzr0dzJCsXNMG0ZZqO/jHn OUW966SyBaClmsSk0NFy+xPlBgvf8t4nq2CsVSOQUF2TRpSEXpZ/twcYKy1tabnqIG23 0N1Qp6Haa6yascwKBrVQu9TyVFQlq08GSaWOE3EwFLfJfZ3y5gsCcJrb0odIC8yBaE+R 6/Eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772004031; x=1772608831; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=kUqCiBd6ikhwKifJPE4u1pdAWzTgL175SpkaOSzjkt4=; b=DKjSPmO4di4nQHV72XRe756Bj5vg0GliJq8qFg4aYHIQnGMumycVzvUomoAfDm5mev vF249SQBgE9cdbCVnrcxKzDXQcHvdFRl1dZNRCO+3W6idkV/xoLVECX+Nx+EZ7OS0SMU l08+19MH2mzKlJ7iSP3jJjGwjkJFV7YM9AzCeC5j1YARsH2P/c4RVM8D9mvhopqGCl0s jJwgCSnzM3e3riea+GQ1/j5dcNxEMD6glqQZaYA4pyjak4Jx8vwYmKnlFI6MhrnL0g/7 P38pn1sCGtGsAp8cHbH5UrvsNTSJaNaSWh8yKudK5P5w1slspyC/R6PESK1BxmjFA0Td G7og== X-Forwarded-Encrypted: i=1; AJvYcCX6hZP2Y0828gkR7dXvZG8PmYLa8TKYTfrDrN0tCxoQAWKhQgoKsBDkO49I7bdELsGfv8dp3Zfi9DpMD+A=@vger.kernel.org X-Gm-Message-State: AOJu0Yy6EH7TBQ4pOUNTEf9aqhyR/Du17xtBkILmD542MN0aZh5/4cfY szDhv20g8PNxL6NocyIUzVpgRQJQxFADz73BYn0nyWQRZ7FhIL0x5dA6cKSAhumATVha4vkacun r1vYsL36nyJMWN97/IoG91K1xPkEuIc8Hm5p9nP1tzS186YnEBXR/eQevIYKiiUEWJUQwXvLka5 Zi9w== X-Gm-Gg: ATEYQzw2OaFrn//BB3f4FDV3QaXZ3/AWv90e8RzMze2k8T/ZuEwJhciM6hq/nLxMMUl 3LisYy8JAI3j5x7SarD/MIUd2U7bMG5JGoF2SA88BlWd12P6qT/vjpnMSBwJpVeJRIIXuxn1fnX n9bnyUPO8wELK66LQARPNtze466iJtctR0Kw+FnJtToAxesT7DfSc1CSH2DEHryl3D5xposTNn2 6j1+OJ4Gsqf7bXem4PiX7jXtx2jaNlOaDbhXMDjfzYOS1zGt7EIFaSeEQ7IV/16g+fy57X/DQgR 3z6b/Cmwz79VdSwVpGSq0r/h0H4EFmloq93W8Vu9aN4uIahw++nLWPMyKV0d28VHZHhQSBZvkSm MArjPd7ZFoX6Scs6zXWeLdUJlNKHW0r0U3yV8QIHjFhz1WLIWTxKP83wPg+quGvv6r3RwfHyV X-Received: by 2002:a05:6830:650c:b0:7c6:cf19:1df1 with SMTP id 46e09a7af769-7d52bf527demr6602434a34.30.1772004031465; Tue, 24 Feb 2026 23:20:31 -0800 (PST) X-Received: by 2002:a05:6830:650c:b0:7c6:cf19:1df1 with SMTP id 46e09a7af769-7d52bf527demr6602415a34.30.1772004031037; Tue, 24 Feb 2026 23:20:31 -0800 (PST) Received: from hu-jingyw-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7d52d038dcdsm11711730a34.16.2026.02.24.23.20.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Feb 2026 23:20:30 -0800 (PST) From: Jingyi Wang Date: Tue, 24 Feb 2026 23:19:21 -0800 Subject: [PATCH v6 06/10] arm64: dts: qcom: kaanapali-mtp: Enable ADSP and CDSP Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260224-knp-dts-misc-v6-6-79d20dab8a60@oss.qualcomm.com> References: <20260224-knp-dts-misc-v6-0-79d20dab8a60@oss.qualcomm.com> In-Reply-To: <20260224-knp-dts-misc-v6-0-79d20dab8a60@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jingyi Wang , 20260114-knp-remoteproc-v4-0-fcf0b04d01af@oss.qualcomm.com, Dmitry Baryshkov , Abel Vesa X-Mailer: b4 0.15-dev-3d134 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772004019; l=1007; i=jingyi.wang@oss.qualcomm.com; s=20250911; h=from:subject:message-id; bh=tW4K+WgSJyLZfWN+10XcL4+EBYZ+0pCMvRvFk+AoOeU=; b=vkAXnOPhfwr2eut1vvPbOoyFabyfDGcyiBgVPT73B/XerPm7r6/IV80UHhH40g04CFMSvh0pQ eZEds9TYdTnBm9TtqRLjGDdMDkEAKltlu4bo7wivWKReyA34fidBnZS X-Developer-Key: i=jingyi.wang@oss.qualcomm.com; a=ed25519; pk=PSoHZ6KbUss3IW8FPRVMHMK0Jkkr/jV347mBYJO3iLo= X-Authority-Analysis: v=2.4 cv=RNe+3oi+ c=1 sm=1 tr=0 ts=699ea2c0 cx=c_pps a=z9lCQkyTxNhZyzAvolXo/A==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=6pSOtZClNuHiBGgWezYA:9 a=QEXdDO2ut3YA:10 a=EyFUmsFV_t8cxB2kMr4A:22 X-Proofpoint-ORIG-GUID: lLuL-P_odQRC3Zh0YweRWWe00kBpr4t1 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjI1MDA3MCBTYWx0ZWRfX50470r9BbfQ9 1N/mdIK+f7n69uPKlnyVMEE3946vim9kdQ9z7bwfXKK6XxA8NLatRgCTVa8QAbzoWXjkAJJQW7b jA053j5qz47n6yWr/jz8utn+NGq1ULKIcrVeHBVLzw3kuF25yu41/s9hqAM0jm7M1Ik2Rxz2xiY z6weJlLCL9UVSxwHXuCvlBfmpCTwnszToUbvtPCbECPoVgYnMW2CKdgJWsgeooMMKRwEY2hqMEq mvfsLQXK4wdZy1BMpvyIRLzf7wUUAcdignPLTHnX9gBJOO0GxBS3Ek3p2E1oa2Qo9r8gggX9Dsz UOAAYWmu2ZEU0DL8EwVYmblGDduuQGTbC7tbll4IcngillP8+xcpRkzrH4sajTJCSpG1MWadK0O zRNgClj1oe27iMt/QmJGoBPH0hMSB/Pjrz5VUE91ZN2ldAyLovYs1lVm1s8HHYAVB7DP5aJ3Xo+ XNBjDvCIlfj3kzJPNbw== X-Proofpoint-GUID: lLuL-P_odQRC3Zh0YweRWWe00kBpr4t1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-24_03,2026-02-23_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 phishscore=0 clxscore=1015 spamscore=0 impostorscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602250070 Enable ADSP and CDSP on Kaanapali MTP board. Reviewed-by: Dmitry Baryshkov Reviewed-by: Abel Vesa Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/d= ts/qcom/kaanapali-mtp.dts index 32a082598434..3544f744fd1d 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts @@ -684,6 +684,20 @@ &pcie_port0 { reset-gpios =3D <&tlmm 102 GPIO_ACTIVE_LOW>; }; =20 +&remoteproc_adsp { + firmware-name =3D "qcom/kaanapali/adsp.mbn", + "qcom/kaanapali/adsp_dtb.mbn"; + + status =3D "okay"; +}; + +&remoteproc_cdsp { + firmware-name =3D "qcom/kaanapali/cdsp.mbn", + "qcom/kaanapali/cdsp_dtb.mbn"; + + status =3D "okay"; +}; + &sdhc_2 { cd-gpios =3D <&tlmm 55 GPIO_ACTIVE_LOW>; =20 --=20 2.25.1 From nobody Thu Apr 2 07:43:58 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84E7330BBAE for ; Wed, 25 Feb 2026 07:20:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772004036; cv=none; b=ZSMfkdyf8xD2slaZQh3iZ+OF2S4ZaVKos5k1PZUGZeTk0D99GvBAMfp7wKd+xhneBMVrXcieo062lOOc+XRQoCaYnsbr8PMSVG8PLkq7NdK1W+OWmPigkMxF8dgs7ziE89Q036svf1xBCZDH6ugWuDRWzdmZUZqq8Iad/dfRPkI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772004036; c=relaxed/simple; bh=QgXLnV6T5dAkEpu/n55wFjWDZqtEWJc1dDIY5S4JeXk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=donOnSS57cEZPwjG5JwxQN9KSh9BL3BxZog5BmcA7eIeA9DfUKOYjYQ6Tte5J7pMYXF70hHihrGI8YgtR8Nixkg6sfnqy3XyN3ga/Y86AxRpwoCcwQ+JQE1165ib2f9kvsJ1XoltXyxipeuho/IsfY8lsCHvlxv6qlivPf17Ea8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=IK7LCrtz; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=Ckx8kJ6L; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="IK7LCrtz"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="Ckx8kJ6L" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 61OLbphx2432436 for ; Wed, 25 Feb 2026 07:20:33 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= uyNK3FGeG2/VWrJDgtIaYbV7K8X2Bvq/x/mAZbpKTS8=; b=IK7LCrtz2TN+IVYe fbBKpedtFG5Mm7uWbjOkwcdvHBBHKlhfZIf3A3mnAwMe4YV0VhMrbb0W6SECDr7k 2vXbypCU9fmmOtNWmxWk8v+EE9K4ZUotLwyNE9Bd2cyIGzlnie8qZNMhDz0Y2rX0 OV/ucHtkPfD+S4Xzncg2ezJ6ARihmgR4DFpRARG4kgiWn55/jMzNf+qAnmYZ3VEt AQ+MxtsNWLuobkyYP4pbVphWniamUe0b5KTeNr1DwdPyi+Bvh8niv/EF17FEJXQx 6ZnpwOS18Rx3yCji+SNGcnKtMzXcwTScFvWl0Akb77z+9ZUxT/CHm8HeON7TsGv8 puAL1g== Received: from mail-ot1-f70.google.com (mail-ot1-f70.google.com [209.85.210.70]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4chekjaqf0-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 25 Feb 2026 07:20:33 +0000 (GMT) Received: by mail-ot1-f70.google.com with SMTP id 46e09a7af769-7d195fe3eb4so95082249a34.3 for ; Tue, 24 Feb 2026 23:20:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1772004033; x=1772608833; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=uyNK3FGeG2/VWrJDgtIaYbV7K8X2Bvq/x/mAZbpKTS8=; b=Ckx8kJ6Lf5ih5pz2rzZsUqzjaCKK4PWOKZu7p/+JBlD10qchuEPvHHRXrYnoxg0MbZ HrxPh1snpfsgVJnDQXG6Lpun5Qez6WUZyCZQSORJCXMfmPHANHv1nPAjzEO6pIVvNYBQ BoTeQDpqyxkStRxSlkuOtJgDzEanz7oAIi/684R9f0LTeaaKb8FIPyLn2cHEZAS4dBYA o721G/xrcPS96adWkM9dzV44UIk0ZL+ITtYlxVEvt6XMV5KLqwkNsOUyNEbvMAyGvP77 eEkMPvFrE0udcDrJwVwrqzo5sXdq0WIziuJ5UvY4jXXxztQBWEF+9MkaTPPfIvIOyjHg X4cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772004033; x=1772608833; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=uyNK3FGeG2/VWrJDgtIaYbV7K8X2Bvq/x/mAZbpKTS8=; b=k6uQKkB53FrCmqZcENwppkmOLGMbFHq0K+0eHGyJdi3o7K2X0RI8xmTE3EanIg2F/G bHKTBKRNzQASCeQTIfnSkMOwz6n9dMdHDq44ATcOVrnFDXFz5rGlGFe9WB1oOvErus3w tHtgQIfio1nT3veoEwjCuZdxU856bIr1kpAnP5sCLLNnpBVd6XHtsYLjwU2jSovw0kxN 5hGy3QrkINgHfg5cIK8O2k8+5Dprw45pgXwvb+YduaPay0Ra0UYFUSkKDFAQs7zhMQ5a mvAaHq3CHS0jK1kdaCe1N8+VTVUoeNgMQBh1TD4z5gD0U5GiUMgdUBcLELHBapDGuKFt Ykcg== X-Forwarded-Encrypted: i=1; AJvYcCVox+5s7Z+t5S/ctuh8UrM5vTxls951dSPtoLI85OM0SJBykdBe4VAjQxLh2uVG44ax0vS8q5T7JcfbqjY=@vger.kernel.org X-Gm-Message-State: AOJu0YycMMPgAsqkoncNs7P2RJo5JUjtKhos/dCsKTgLL7iWd3goszKk +stDELZrJR481CnAL5ahpnXEPIcui2goiTmCPcqc4z8DkPhtmeUM53jspJ0uXMsWUp5Q325qzna A/Q9HjXIcPkxS5PNOYXCJp0GsAWiNxjOxuZuwiy+pPdJHC8Nw2jgPbRjA6R3Ln5Cj66s= X-Gm-Gg: ATEYQzwT7pwwi5BC/wHDZuYmAQaGLvDBUglbod3NpLt1b3kRgHCcve39DseMPN+tAF1 hA9BpaxoE4gxXaoRgPNf66E1uXyAHF9WDBV4kIb4IlwHYRZRe9hU9kngDR/Kjearv5HbZQgWWOp DqFF+tWRB9Cl/4ez1AoDOflxQF3LfCKzd3kweBMlhA1MQ/SHpLNgO2Qx1BtI/Rkc/qcZs79Md7B M+tWLDAfVL53YLwG5gDv2hFo+OywVxCrrleqUyiD6qA9/uS8bkiR4kJP3yt8aPasA5YvPEOCHIW ga3KUnGGWRpScwHaPVEVs5RSDYEuQh6sWJzPNcnWn9t6VPhzGCbRooWblaJzet+6ee+PC/9p/Cb dHqOE3OLcJN2y1QQpGtUQuk/aZljpTO4T23IRDxZ2FOl2+E6p1J1giADhy0q+wkSSnI+GL3fH X-Received: by 2002:a05:6830:2546:b0:7ca:c7b0:17eb with SMTP id 46e09a7af769-7d52be37e7dmr8932420a34.10.1772004032890; Tue, 24 Feb 2026 23:20:32 -0800 (PST) X-Received: by 2002:a05:6830:2546:b0:7ca:c7b0:17eb with SMTP id 46e09a7af769-7d52be37e7dmr8932414a34.10.1772004032598; Tue, 24 Feb 2026 23:20:32 -0800 (PST) Received: from hu-jingyw-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7d52d038dcdsm11711730a34.16.2026.02.24.23.20.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Feb 2026 23:20:32 -0800 (PST) From: Jingyi Wang Date: Tue, 24 Feb 2026 23:19:22 -0800 Subject: [PATCH v6 07/10] arm64: dts: qcom: kaanapali-qrd: Enable ADSP and CDSP Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260224-knp-dts-misc-v6-7-79d20dab8a60@oss.qualcomm.com> References: <20260224-knp-dts-misc-v6-0-79d20dab8a60@oss.qualcomm.com> In-Reply-To: <20260224-knp-dts-misc-v6-0-79d20dab8a60@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jingyi Wang , 20260114-knp-remoteproc-v4-0-fcf0b04d01af@oss.qualcomm.com, Dmitry Baryshkov , Abel Vesa X-Mailer: b4 0.15-dev-3d134 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772004019; l=1012; i=jingyi.wang@oss.qualcomm.com; s=20250911; h=from:subject:message-id; bh=QgXLnV6T5dAkEpu/n55wFjWDZqtEWJc1dDIY5S4JeXk=; b=6/fWFyhMq3h7ZBLu8/cEhX9RAqL6e1qv8KztMgQ7R+C3M9mBhGm6zXPvpmhN1EyDVrairCbum AOXvK0TJgSTDPzOqJG/BRkXT+rMrPBzJYYuV8OKaG/e2Iw2KEZ/lXq3 X-Developer-Key: i=jingyi.wang@oss.qualcomm.com; a=ed25519; pk=PSoHZ6KbUss3IW8FPRVMHMK0Jkkr/jV347mBYJO3iLo= X-Authority-Analysis: v=2.4 cv=RNe+3oi+ c=1 sm=1 tr=0 ts=699ea2c1 cx=c_pps a=7uPEO8VhqeOX8vTJ3z8K6Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=lIVsHN_WdLZ9tVWbX6YA:9 a=QEXdDO2ut3YA:10 a=EXS-LbY8YePsIyqnH6vw:22 X-Proofpoint-ORIG-GUID: 1SkBeeB5rX30kw1WPCt-hBNhxxjkPoAC X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjI1MDA3MCBTYWx0ZWRfX2AIfWKCHSFps kjgXDpq/d6ohq2tZkK06+gfJGDbQi6OTFpdkGHB4Rz78AnmlZX58g+Od0HOVf//qx5DL+xrXzD/ eNQLLNuX82nQ+v3gsdT9V0r/PXgp0yXYTI2wCidK6TcNIq5eiVhse3kmoWmgWza7qoWBnjZxFfw jL+94xJ4OaUp652vRBH8QEoYshEkX1xPA3p+bZNG5aVfbd7FaQCyUyGJFcUXiUvzlLM25VCQ+wP 040Ng4jO9Oph8im1Waxp70Or2Qaqy9Ihsbdc9aWnakAuCmhl6ugAEps2OY7bjPZPQ9VOUOc7BZC AaSyemOpI+aAN3iWciGnz5HhipSiM/G+NGY8C4NToX527OxxJtEIae3QYhkzgDHuiK+GaOH8i4U /Xu/kjhcS2AYJg9e6vNjXfmIJxnXEj8Q+SJ6VbU4kWB6bRgPNEcB9I7vRRkGVG2PsVV3jP9Y+SC 76ggraxTB5b7UTU0CPQ== X-Proofpoint-GUID: 1SkBeeB5rX30kw1WPCt-hBNhxxjkPoAC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-24_03,2026-02-23_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 phishscore=0 clxscore=1015 spamscore=0 impostorscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602250070 Enable ADSP and CDSP on Kaanapali QRD board. Reviewed-by: Dmitry Baryshkov Reviewed-by: Abel Vesa Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali-qrd.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts b/arch/arm64/boot/d= ts/qcom/kaanapali-qrd.dts index 66b423a497b3..32034eed03eb 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts @@ -682,6 +682,20 @@ &sdhc_2 { status =3D "okay"; }; =20 +&remoteproc_adsp { + firmware-name =3D "qcom/kaanapali/adsp.mbn", + "qcom/kaanapali/adsp_dtb.mbn"; + + status =3D "okay"; +}; + +&remoteproc_cdsp { + firmware-name =3D "qcom/kaanapali/cdsp.mbn", + "qcom/kaanapali/cdsp_dtb.mbn"; + + status =3D "okay"; +}; + &tlmm { gpio-reserved-ranges =3D <36 4>, /* NFC eSE SPI */ <74 1>, /* eSE */ --=20 2.25.1 From nobody Thu Apr 2 07:43:58 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C07D30E0D6 for ; Wed, 25 Feb 2026 07:20:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772004038; cv=none; b=nPtIBoYTYbtc8vBxBK4qesV+7510XUfvFpViRWUvrdi9rwAeyQe2urVp0fDN53wn85Zqq8gs5aitsQ1M/Y/v+2Z5bzsGofIFPTgWAoA3i5b1qPW7/c3Z+H70+22I5eKowGhSmnlaFQDz9WGUb8QNvc+Dh4f/ydQJXnVD0i4b8b4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772004038; c=relaxed/simple; bh=mHUaP5NvtmLyzzQH6UoVGlyemVmnqXmW3W36Kns065s=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=U0q/8HVqxiNWKEuLtfWFY8LpyMx5pYoAQ6ubA0daHnbBg88mhx3/lk4hUAmclb99CC26bIWEjO3CgPCRAj4+QQ0I0cgVUCFylc4L/ScMn4w1Tho9QF1lhc3SYwCKxWuK5RvXSaTbbV2tx/duwoJd2H2FvxaVJ91S2+0Z5ehylPk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=VPLrGKr9; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=JHeA1+eh; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="VPLrGKr9"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="JHeA1+eh" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 61OMpTWj3177079 for ; Wed, 25 Feb 2026 07:20:35 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 2Ab85S6IbMI2MQ9YFhaoEHTiwYDDCEDsjuGQbKUiTio=; b=VPLrGKr9WZfP2K2p vXklmlVlgDkaa8i3iBEZGUrYvGFfu/VAPDuqSdlSDgP68MUGwFycGK3ADOCaTZyB DGDwCzeLCnWosMJnHLC3ihMn/ipFRjnQ4EljSlAhf/nVZCAU/vepjGoyYZjQkACz RtwWBDNcwcar1Armyqx4fx/lWwaPhWWquvY4UZmim0momMx2i8NY7r2EEGvatNxW zdWVjnjavZJpilEuJM5Dyt48p67CCTSIGNxBBFUVR/mEZ9XjlzBPkvvwl8YgIeUQ dtr2qrlVPuaFESsD6vmnvmtMv795LacQ3spsvQQrunF6J1mDSVqntqyGDSuUDoHO 6Yk9Ag== Received: from mail-ot1-f72.google.com (mail-ot1-f72.google.com [209.85.210.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4chemntn6k-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 25 Feb 2026 07:20:35 +0000 (GMT) Received: by mail-ot1-f72.google.com with SMTP id 46e09a7af769-7d4cb5810a0so40591704a34.1 for ; Tue, 24 Feb 2026 23:20:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1772004034; x=1772608834; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=2Ab85S6IbMI2MQ9YFhaoEHTiwYDDCEDsjuGQbKUiTio=; b=JHeA1+ehyFOpuWamRrm815agPfp1+FGMngmOnE2usW3HWWBKsiwsrnU0zTW5I1IwdF lIulefJ5vN4fAXdwoSsrJynf3CzXzQjJW/KhPGwjB2jlv1k/ngv/aSPDzx8wjzJeNhDX 5IZvT4Yr7L+qLUdXXXJxE5ctzaUu6FLfoJZ7EF40jtVlIybt0wMnc9jL48KpF4UP/tkS xjSG27uE+LIpi+jiROin6AdHgpqiLekI7QPx61ADRInsoUMIeDvJaP0OR2supAUutEgc j7zRfoyseOYPlHuI3pxZMpLuvSQEpnHbfJvryk6TcJMIJQXSsNVXi3yYu4MiuZKaRDT1 FAJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772004034; x=1772608834; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=2Ab85S6IbMI2MQ9YFhaoEHTiwYDDCEDsjuGQbKUiTio=; b=CG5Z/wg6ZNZ9fBw0MdpmVxSM4JIHuLbRMhgaVL+5Lm8wdXjowj0+568b0J24E5flGf VdRDLcDrhOpQraicsnxerj0ultjOv7f1BX7Tc9cYLC+jchr2caI6XDrnQwmcwyzsoVBl JQkkuG2uZ0vmQBj348ZNDmaci/pqiTiHNWsYIlsZ7q+O0VHGsBYf4bqmZgBJT/Sq0JPG vERGEDO/nb3qaSI6ugAmQQX9fMoWGa/HVFEBGnBSsIXuJYXjJyMUY98q/PqAdRx+kDkp ocFLizFeCzM1+yP9GSwcwloqLD/dGfOtIiVegoOpFkixLJh3iQ2HsDEZarJU/ZV6SYIn 4t4A== X-Forwarded-Encrypted: i=1; AJvYcCUUa8aRNYMhIvfvDT4EwDeMv4tv4kZPjK3KWButoaCQ1XZRaj4JoVudzlg/gGOCwR4WPibW+z8NQ8oTiVQ=@vger.kernel.org X-Gm-Message-State: AOJu0YzQ94oHBcJtqw2cfo2FspCSnBTO7SZkaHywXXtDhgYZjyOf0xUw koztIxp9aKwgA4AIEkw0FyoZrp1vDwRtRwe+hcI1iKZ6H9F0WHD9Jxes4lVZbCeYBOCi11+eixP St5XGadQJre0AGR8GApUih6qdcrAyjUCw32F9BhyGDCwhvcvVmoBHorEwK4cVtG6cr6s= X-Gm-Gg: ATEYQzzFI6rQfUC8GaiRuczXXMpa+zIkXRf8jlGVr+x5xoCGWepnHnDNs32RBqCUpqM hgSg5KygKeNbhvdcAFVok0eHZvUy5sfH5aPNvuodVKs/I9d/EycUB1oMw5YazJ6FTSI1VLhTEwQ eYMg8hq5jpDKW1ZIZFNTlN09ejxJZcpWHwnwDE7vEHSnFF4AZbgi4HiHPm78Gzp8JX7GhlvuNiR O0d9QLqElh16K7C9rZk2s7CL661Y7EeKT1P5/+DXJ5iBWXNlxNrEnGY+cCaSsHwXlElH0MC16UO 4+SYNk1bHHrr/avshFgvOnArjQzxeN05Wvl4PNx2PYZHQWvBMNF4g3LzLN0sXu9tgCQDxO3MCps Hxj3+W6Ppdctr275JrjRa48rYz+RAJGpbOdRBEMQqu+hH86kxYopJ9sadgYpc6riSDIZH6/oW X-Received: by 2002:a05:6830:4118:b0:7ce:2b15:de88 with SMTP id 46e09a7af769-7d52c2c9262mr9232035a34.26.1772004034370; Tue, 24 Feb 2026 23:20:34 -0800 (PST) X-Received: by 2002:a05:6830:4118:b0:7ce:2b15:de88 with SMTP id 46e09a7af769-7d52c2c9262mr9232012a34.26.1772004033907; Tue, 24 Feb 2026 23:20:33 -0800 (PST) Received: from hu-jingyw-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7d52d038dcdsm11711730a34.16.2026.02.24.23.20.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Feb 2026 23:20:33 -0800 (PST) From: Jingyi Wang Date: Tue, 24 Feb 2026 23:19:23 -0800 Subject: [PATCH v6 08/10] arm64: dts: qcom: kaanapali-mtp: Add audio support (WSA8845, WCD9395, DMIC) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260224-knp-dts-misc-v6-8-79d20dab8a60@oss.qualcomm.com> References: <20260224-knp-dts-misc-v6-0-79d20dab8a60@oss.qualcomm.com> In-Reply-To: <20260224-knp-dts-misc-v6-0-79d20dab8a60@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jingyi Wang , 20260114-knp-remoteproc-v4-0-fcf0b04d01af@oss.qualcomm.com, Prasad Kumpatla , Konrad Dybcio X-Mailer: b4 0.15-dev-3d134 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772004019; l=7373; i=jingyi.wang@oss.qualcomm.com; s=20250911; h=from:subject:message-id; bh=ameuWwKDmYuonMpUCitEB9BIFn0ezp5L7tJ6EyXrZQc=; b=WvK96evUixJDMihtHQ3LNCxJonPs4tgiUtY9t0wmqgIFUpPbe3AnqMHHMGyi8WBz5bXiqJTr7 2J+GmOPUpUADO8UZ0jaiZ2iFP7UMNyyK96Hi5vlAOzNWPSZy+KEKC/f X-Developer-Key: i=jingyi.wang@oss.qualcomm.com; a=ed25519; pk=PSoHZ6KbUss3IW8FPRVMHMK0Jkkr/jV347mBYJO3iLo= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjI1MDA3MCBTYWx0ZWRfXxFgP+3u7FYuA sNGL2Z2uWGyVWRXK3jPEEVdYo4uzI/uCfSnHfJpbBX3R1PTyWMQrgGTR2HXDF2Ciee9sZPJzofq 1EbhxVRRkDRNrrGFguI90RSDUdQBPUclgv1wjkDFbd49HMRTD6HpRk03X+SwNxOJ8UsEv966K5K F/qybtcN3jU4lZHs0+qYZbVhS5wSNTknNWdgCWQ+aET2fLZlQwuqa4r8/MZ7ByMXg3o9Zox9gdi u2APxBWinKPorJVuXs8C/kwYkse8sVCZ598g+/SCZK20qY90JSBhyys8hRse3oUVqH5nSIVzfyP HOOKdkRL91P8k+DbeaFLgiicJ2aIEpCRov7oHRk01JiDYTGMm2YHFc44z2ceSdEVHRgd4uDfHII B2iOQh7tTwp4T5Z8ENHC4zlWtgEITqqAf0CbVL9iniSdjeMAYssL7x152cg/o1QLCMfcNGjQ4ab 68tJKZM8skyydLhOpwA== X-Proofpoint-ORIG-GUID: R3Fi9RD6Sz3nmdTgy3CwMAHCrXxnKSdH X-Authority-Analysis: v=2.4 cv=Ro7I7SmK c=1 sm=1 tr=0 ts=699ea2c3 cx=c_pps a=+3WqYijBVYhDct2f5Fivkw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=lxMpYmIrUrCHLM_QX0YA:9 a=QEXdDO2ut3YA:10 a=eYe2g0i6gJ5uXG_o6N4q:22 X-Proofpoint-GUID: R3Fi9RD6Sz3nmdTgy3CwMAHCrXxnKSdH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-24_03,2026-02-23_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 spamscore=0 bulkscore=0 adultscore=0 impostorscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602250070 From: Prasad Kumpatla Add support for audio on the Kaanapali MTP platform by introducing device tree nodes for WSA8845 smart speaker amplifier for playback, DMIC microphone for capture, and sound card routing. The WCD9395 codec is add to supply MIC-BIAS, for enabling onboard microphone capture. Signed-off-by: Prasad Kumpatla Reviewed-by: Konrad Dybcio Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 226 +++++++++++++++++++++++++= ++++ 1 file changed, 226 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/d= ts/qcom/kaanapali-mtp.dts index 3544f744fd1d..bc57935c042c 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts @@ -52,6 +52,115 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { clock-div =3D <2>; }; }; + + sound { + compatible =3D "qcom,kaanapali-sndcard", "qcom,sm8450-sndcard"; + model =3D "Kaanapali-MTP"; + + audio-routing =3D "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS1", + "VA DMIC1", "MIC BIAS1", + "VA DMIC2", "MIC BIAS3", + "VA DMIC3", "MIC BIAS3", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + va-dai-link { + link-name =3D "VA Capture"; + + codec { + sound-dai =3D <&lpass_vamacro 0>; + }; + + cpu { + sound-dai =3D <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name =3D "WCD Capture"; + + codec { + sound-dai =3D <&wcd939x 1>, <&swr2 0>, <&lpass_txmacro 0>; + }; + + cpu { + sound-dai =3D <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + wcd-playback-dai-link { + link-name =3D "WCD Playback"; + + codec { + sound-dai =3D <&wcd939x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + cpu { + sound-dai =3D <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + wsa-dai-link { + link-name =3D "WSA Playback"; + + codec { + sound-dai =3D <&north_spkr>, <&south_spkr>, <&swr0 0>, + <&lpass_wsamacro 0>; + }; + + cpu { + sound-dai =3D <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + }; + + wcd939x: audio-codec { + compatible =3D "qcom,wcd9395-codec", "qcom,wcd9390-codec"; + + pinctrl-0 =3D <&wcd_default>; + pinctrl-names =3D "default"; + + qcom,micbias1-microvolt =3D <1800000>; + qcom,micbias2-microvolt =3D <1800000>; + qcom,micbias3-microvolt =3D <1800000>; + qcom,micbias4-microvolt =3D <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt =3D <75000 150000 237000 500000 + 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt =3D <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt =3D <50000>; + qcom,rx-device =3D <&wcd_rx>; + qcom,tx-device =3D <&wcd_tx>; + + reset-gpios =3D <&tlmm 161 GPIO_ACTIVE_LOW>; + + vdd-buck-supply =3D <&vreg_l15b_1p8>; + vdd-rxtx-supply =3D <&vreg_l15b_1p8>; + vdd-io-supply =3D <&vreg_l15b_1p8>; + vdd-mic-bias-supply =3D <&vreg_bob1>; + vdd-px-supply =3D <&vreg_l1g_1p2>; + + #sound-dai-cells =3D <1>; + }; }; =20 &apps_rsc { @@ -665,6 +774,14 @@ vreg_l7n_3p3: ldo7 { }; }; =20 +&lpass_vamacro { + pinctrl-0 =3D <&dmic01_default>, <&dmic23_default>; + pinctrl-names =3D "default"; + + vdd-micb-supply =3D <&vreg_l10b_1p8>; + qcom,dmic-sample-rate =3D <4800000>; +}; + &pcie0 { pinctrl-0 =3D <&pcie0_default_state>; pinctrl-names =3D "default"; @@ -715,12 +832,114 @@ &sdhc_2 { status =3D "okay"; }; =20 +&swr0 { + status =3D "okay"; + + /* WSA8845, Speaker North */ + north_spkr: speaker@0,0 { + compatible =3D "sdw20217020400"; + reg =3D <0 0>; + pinctrl-0 =3D <&spkr_0_sd_n_active>; + pinctrl-names =3D "default"; + powerdown-gpios =3D <&tlmm 76 GPIO_ACTIVE_LOW>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SpkrLeft"; + vdd-1p8-supply =3D <&vreg_l15b_1p8>; + vdd-io-supply =3D <&vreg_l2i_1p2>; + + /* + * WSA8845 Port 1 (DAC) <=3D> SWR0 Port 1 (SPKR_L) + * WSA8845 Port 2 (COMP) <=3D> SWR0 Port 2 (SPKR_L_COMP) + * WSA8845 Port 3 (BOOST) <=3D> SWR0 Port 3 (SPKR_L_BOOST) + * WSA8845 Port 4 (PBR) <=3D> SWR0 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=3D> SWR0 Port 10 (SPKR_L_VI) + * WSA8845 Port 6 (CPS) <=3D> SWR0 Port 13 (CPS) + */ + qcom,port-mapping =3D <1 2 3 7 10 13>; + }; + + /* WSA8845, Speaker South */ + south_spkr: speaker@0,1 { + compatible =3D "sdw20217020400"; + reg =3D <0 1>; + pinctrl-0 =3D <&spkr_1_sd_n_active>; + pinctrl-names =3D "default"; + powerdown-gpios =3D <&tlmm 77 GPIO_ACTIVE_LOW>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SpkrRight"; + vdd-1p8-supply =3D <&vreg_l15b_1p8>; + vdd-io-supply =3D <&vreg_l2i_1p2>; + + /* + * WSA8845 Port 1 (DAC) <=3D> SWR0 Port 4 (SPKR_R) + * WSA8845 Port 2 (COMP) <=3D> SWR0 Port 5 (SPKR_R_COMP) + * WSA8845 Port 3 (BOOST) <=3D> SWR0 Port 6 (SPKR_R_BOOST) + * WSA8845 Port 4 (PBR) <=3D> SWR0 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=3D> SWR0 Port 11 (SPKR_R_VI) + * WSA8845 Port 6 (CPS) <=3D> SWR0 Port 13 (CPS) + */ + qcom,port-mapping =3D <4 5 6 7 11 13>; + }; +}; + +&swr1 { + status =3D "okay"; + + /* WCD9395 RX */ + wcd_rx: codec@0,4 { + compatible =3D "sdw20217010e00"; + reg =3D <0 4>; + + /* + * WCD9395 RX Port 1 (HPH_L/R) <=3D> SWR1 Port 1 (HPH_L/R) + * WCD9395 RX Port 2 (CLSH) <=3D> SWR1 Port 2 (CLSH) + * WCD9395 RX Port 3 (COMP_L/R) <=3D> SWR1 Port 3 (COMP_L/R) + * WCD9395 RX Port 4 (LO) <=3D> SWR1 Port 4 (LO) + * WCD9395 RX Port 5 (DSD_L/R) <=3D> SWR1 Port 5 (DSD_L/R) + * WCD9395 RX Port 6 (HIFI_PCM_L/R) <=3D> SWR1 Port 9 (HIFI_PCM_L/R) + */ + qcom,rx-port-mapping =3D <1 2 3 4 5 9>; + }; +}; + +&swr2 { + status =3D "okay"; + + /* WCD9395 TX */ + wcd_tx: codec@0,3 { + compatible =3D "sdw20217010e00"; + reg =3D <0 3>; + + /* + * WCD9395 TX Port 1 (ADC1,2,3,4) <=3D> SWR2 Port 2 (TX SWR_INPU= T 0,1,2,3) + * WCD9395 TX Port 2 (ADC3,4 & DMIC0,1) <=3D> SWR2 Port 2 (TX SWR_INPU= T 0,1,2,3) + * WCD9395 TX Port 3 (DMIC0,1,2,3 & MBHC) <=3D> SWR2 Port 3 (TX SWR_INPU= T 4,5,6,7) + * WCD9395 TX Port 4 (DMIC4,5,6,7) <=3D> SWR2 Port 4 (TX SWR_INPU= T 8,9,10,11) + */ + qcom,tx-port-mapping =3D <2 2 3 4>; + }; +}; + &tlmm { gpio-reserved-ranges =3D <36 4>, /* NFC eSE SPI */ <74 1>, /* eSE */ <119 2>, /* SoCCP */ <144 4>; /* CXM UART */ =20 + spkr_0_sd_n_active: spkr-0-sd-n-active-state { + pins =3D "gpio76"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + }; + + spkr_1_sd_n_active: spkr-1-sd-n-active-state { + pins =3D "gpio77"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + }; + pcie0_default_state: pcie0-default-state { perst-n-pins { pins =3D "gpio102"; @@ -743,6 +962,13 @@ wake-n-pins { bias-pull-up; }; }; + + wcd_default: wcd-reset-n-active-state { + pins =3D "gpio161"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + }; }; =20 &uart7 { --=20 2.25.1 From nobody Thu Apr 2 07:43:58 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE49F30FC01 for ; Wed, 25 Feb 2026 07:20:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772004041; cv=none; b=khkFGAdYY118Dg5mxcS55cXAdyHbnlKPG395RPFbYKqqZA9N75h4gFJlFNdmOZbGoE9nNLOQ9FFMvDEjFJtovI5audSMOxt8xLTOY+gUkAmr/BH/0vwuccbhqxlIm3ivs1F5IQoicjTCUa0YNoVoz1H0BeAMJ3S8AR875BxnIjA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772004041; c=relaxed/simple; bh=nH/RL960Viqwo0UIk7J/RC9fDXoLarB0W2+36h9B1BI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tee8aLkaHzID2QN7QPWHNFRxwspAiimskB7qyX0UbHmWUyjlhNtltajMpdWaj4pMmcSSKYONPEr/Y1e0uKptxIpkLN7e3Xo1YDvrRICaCKs+i2k0b67T2Ri4UcBHrb6ihWKjRqwBD0U9pUeBCfN/m6BzA2IsIpUB/Vuf0PSwQZ8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=mxjrXyXI; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=hge+JPDR; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="mxjrXyXI"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="hge+JPDR" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 61OM9u3k3177097 for ; Wed, 25 Feb 2026 07:20:36 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= c7LLhlpqM6PoLC/o0FIKUUtAjchIO0ALnvSYLQ5VF04=; b=mxjrXyXIxDDXvM9A 9uJKyEuaSIE8mJU27GWhb5GuYpQLq4Dr2l392t6fJzZUdvbCbqJZ3CqsZCxy06Ss IxLUMzVz8vsh3FGxyWI9pByVSoQFVmuXDc5p+5S4utBH3XSFO4HvTa/Ltx+aLSIq StYZVO9tVOeRf4h7ide66GVuD/xb1MlKHNn+kTlXAlqjVwE0CC/pCng/H08SonBe ITWHSj6b9wg7FxA6vGkth0TlgrjOsWvY1QEvTumtrY3RNGc0bVuIoIemxwf0UeUa LHx3Z1qw/AO/7zqpGyZUP5o6xlMJ4VLt1Jrw4zwA1gl0Gwu7xz5U5e3h9eLReaj/ 0ScRDQ== Received: from mail-ot1-f70.google.com (mail-ot1-f70.google.com [209.85.210.70]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4chemntn6p-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 25 Feb 2026 07:20:36 +0000 (GMT) Received: by mail-ot1-f70.google.com with SMTP id 46e09a7af769-7d4beca8c53so78886345a34.2 for ; Tue, 24 Feb 2026 23:20:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1772004036; x=1772608836; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=c7LLhlpqM6PoLC/o0FIKUUtAjchIO0ALnvSYLQ5VF04=; b=hge+JPDRknzVw6D2ftXY+B7nohZVKXmuNAJ7yS92zUOsA8Og/927b31L3u6Y+APf7l QysoaO1wsoqph58EEjk7yLatRQbdjTwT8svzugmbpV4HytqzoellCWoCDBWAvxaCPYAz dAaq5tCSeKAsHr+TVe7E7qN+aHBqWjRf1qNqoHYaUK477N2pxW/+6i5S2O2q06hhaUev YO4AOEtXBsUaAu9mLJPLfoZuMPPAcCXNeDN6T7tfWqEEubQ3zJ+6nKwmHmc9rPZL+jDZ w6xlLiAyjnESGcLhyM+gNJNOYKwIPRIkO3HSWgclPJXqj3DR5eu8fNLC4LVXnkcQNAM4 UUxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772004036; x=1772608836; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=c7LLhlpqM6PoLC/o0FIKUUtAjchIO0ALnvSYLQ5VF04=; b=OyYq6wDC/OQCkUvnfCzmrM4QxyATfdC7kdEkmNHPFkef13ZkvTagIzTuGyHL/8CZU1 gF9oXg86cWSKwJYYlnuuSNDIjHtg97doMMT7XL4q+SOAmPyCiw1E6sH2x2W+gv3yc6OA IHpeT1z7UuHYN2DjQNRVXJ3fbbxIzPu7qCI87hN/3L6R6/19JFNk/Sss7chEIevZHYLZ FbK2+mlfNLEeAtUeN3HBzLLUqZcIts1IIcfTKiVZvheKFbZobX43O976WnuV7aHIGwwC tVaBooHfF2qANYoOEdPvWQtJMA4QeHuoA2q49Yi7sqL3JO/vafSguyxdBASdKutjoYWI DYqQ== X-Forwarded-Encrypted: i=1; AJvYcCVPtcD7IN5XdIrwAwGchhwzb9lE/gdhfBKvHkW/h77tvdnJD/3ZGZKHMg1o+U73PBC5Rj2cBorofx6pWBM=@vger.kernel.org X-Gm-Message-State: AOJu0YzrEeGPnXqf7s9Sv3ZHFkT/YsPq5srAe02gBsyl/EJv9OLisQob UkeBTywZydp7aiae/ffZ8XT9tUG1CFbNRNB4ry3ERpuDDljiDWInnc486XwQIBHfZhbLTesydXi KAu2azrlvZkX68HRcEnCngliRhAu/G7YHpYBpzLwbXEaS90YGDBP0t2eB18VpmslmOEw= X-Gm-Gg: ATEYQzyTJ2WZEbFlRKUxyxww+q7wYrRooHbzVSmhNfihCOf9sAgBy2LhbKnnaa3iRPD JXHe+ZmCU1qGVk0fSHdo0pLVqk1G7ViR3wp8iVj6OYspv9sPFA6X54gQvXgVRjnosZVynjWhW+L isxzzV7i9zLIgSlnPLU5S+QV6tpUu2nAFu5jvk979OYQz4MHuHCvsnjuC/mHb95Qte+6rNVPEAu T9mcPEHal03knPNYgq8IuC5DiMv6tY5qvoqEYYxGRlsJ37AhzeQDSS2Q5JbG+7/qRJk+9eFld45 V19njnqVN68tIK3gSmYAzIHKJBijc7zSD0N10F7v5+96uu57JFAtzG2cmWgLl5NaedDJVsKuT2c BJspVkj3tLo8NthmD/vL2uQWcnFHrWjVB5trAl2pCtwk/V28m9bYCSIHFlIc4GhDHRO6sIH3W X-Received: by 2002:a05:6830:2588:b0:7d1:9572:9111 with SMTP id 46e09a7af769-7d52bdf76bemr8338301a34.1.1772004035972; Tue, 24 Feb 2026 23:20:35 -0800 (PST) X-Received: by 2002:a05:6830:2588:b0:7d1:9572:9111 with SMTP id 46e09a7af769-7d52bdf76bemr8338279a34.1.1772004035496; Tue, 24 Feb 2026 23:20:35 -0800 (PST) Received: from hu-jingyw-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7d52d038dcdsm11711730a34.16.2026.02.24.23.20.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Feb 2026 23:20:34 -0800 (PST) From: Jingyi Wang Date: Tue, 24 Feb 2026 23:19:24 -0800 Subject: [PATCH v6 09/10] arm64: dts: qcom: kaanapali: Add support for MM clock controllers for Kaanapali Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260224-knp-dts-misc-v6-9-79d20dab8a60@oss.qualcomm.com> References: <20260224-knp-dts-misc-v6-0-79d20dab8a60@oss.qualcomm.com> In-Reply-To: <20260224-knp-dts-misc-v6-0-79d20dab8a60@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jingyi Wang , 20260114-knp-remoteproc-v4-0-fcf0b04d01af@oss.qualcomm.com, Taniya Das , Konrad Dybcio , Abel Vesa X-Mailer: b4 0.15-dev-3d134 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772004019; l=4559; i=jingyi.wang@oss.qualcomm.com; s=20250911; h=from:subject:message-id; bh=nsYZEEXXsjI4so4Na/T/SEdJ96D+J8BKnk0ZTfIBIXw=; b=TfBj9DIkEMRmRuI40yrrnUVy+NrYGVadVDZypwl6ydfXxa2XvshFnFd9tvliq5LH+/qhJ8rRJ 4oVnng1P/ZeDPdi16Pxp5Q2X/iEQb5w3ajdaY3tIhrnozPy6TMPs0w7 X-Developer-Key: i=jingyi.wang@oss.qualcomm.com; a=ed25519; pk=PSoHZ6KbUss3IW8FPRVMHMK0Jkkr/jV347mBYJO3iLo= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjI1MDA3MCBTYWx0ZWRfX1ad8a1gLe8+Q T5uk9G0tVrLmUJ0sY0Sh/ueKs+hb1loBQJUWT0yR7FywsY5b0UtyGVOgUNvP4orts2UUF1lzmjF izmampjKy7yDa7iHqyqBQdvOhmNc+l1DagWEx4/Nxi+A0HYPfjbDym1jw52glf4VtWbOYyOmLmX BjLW+IqULFiLCw6F+k/crFDQA5HZmqERLOAKbTpAtPhAix7qY+N9zIXut5lIRNipJYy3ptij0FX nZPf4YFMxJOl1kl4tZ5xcVk2cvOrUMFtg1C/V9J4C6hDgODpHyI0P82q6ciJ8YUgXjUbUHklXYg WP6J/wpU00LtwulaV8TP6BNYMv5rtCuTwsrxxknijmYfUfPCqP8AbTFeiyP9ziyhctNvX8+Lp4z pZadRR6rCy0Jcj0A7zlEfeVLXav0FjSbCskBL7h/nYFv+LFXvqKigQ1y/b7nMoVqxeBFSit8iXu 1Pf38yxEso0P46H9nxA== X-Proofpoint-ORIG-GUID: 0zNvjm2PI1lYCWGioakMdvtIdrLzrLzD X-Authority-Analysis: v=2.4 cv=Ro7I7SmK c=1 sm=1 tr=0 ts=699ea2c4 cx=c_pps a=7uPEO8VhqeOX8vTJ3z8K6Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=Y3HLYP14RHR0fgYgac8A:9 a=QEXdDO2ut3YA:10 a=EXS-LbY8YePsIyqnH6vw:22 X-Proofpoint-GUID: 0zNvjm2PI1lYCWGioakMdvtIdrLzrLzD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-24_03,2026-02-23_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 spamscore=0 bulkscore=0 adultscore=0 impostorscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602250070 From: Taniya Das Add the device nodes for the multimedia clock controllers (cambistmclkcc, camcc, dispcc, videocc, gpucc and gxclkctl). Signed-off-by: Taniya Das Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 111 ++++++++++++++++++++++++++++= ++++ 1 file changed, 111 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/= qcom/kaanapali.dtsi index d9880a87a928..54d6c235e1b1 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -3,7 +3,13 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 +#include +#include +#include #include +#include +#include +#include #include #include #include @@ -1557,6 +1563,24 @@ aggre_noc: interconnect@16e0000 { <&rpmhcc RPMH_IPA_CLK>; }; =20 + cambistmclkcc: clock-controller@1760000 { + compatible =3D "qcom,kaanapali-cambistmclkcc"; + reg =3D <0x0 0x01760000 0x0 0x8000>; + + clocks =3D <&gcc GCC_CAM_BIST_MCLK_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MX>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + mmss_noc: interconnect@1780000 { compatible =3D "qcom,kaanapali-mmss-noc"; reg =3D <0x0 0x01780000 0x0 0x5b800>; @@ -2532,6 +2556,46 @@ tcsr: clock-controller@1fc0000 { #reset-cells =3D <1>; }; =20 + videocc: clock-controller@20f0000 { + compatible =3D "qcom,kaanapali-videocc"; + reg =3D <0x0 0x020f0000 0x0 0x10000>; + clocks =3D <&bi_tcxo_div2>, + <&gcc GCC_VIDEO_AHB_CLK>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + gxclkctl: clock-controller@3d64000 { + compatible =3D "qcom,kaanapali-gxclkctl"; + reg =3D <0x0 0x03d64000 0x0 0x6000>; + + power-domains =3D <&rpmhpd RPMHPD_GFX>, + <&rpmhpd RPMHPD_GMXC>, + <&gpucc GPU_CC_CX_GDSC>; + + #power-domain-cells =3D <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible =3D "qcom,kaanapali-gpucc"; + reg =3D <0x0 0x03d90000 0x0 0x9800>; + + clocks =3D <&bi_tcxo_div2>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + remoteproc_adsp: remoteproc@6800000 { compatible =3D "qcom,kaanapali-adsp-pas", "qcom,sm8550-adsp-pas"; reg =3D <0x0 0x06800000 0x0 0x10000>; @@ -3073,6 +3137,53 @@ opp-202000000 { }; }; =20 + camcc: clock-controller@956d000 { + compatible =3D "qcom,kaanapali-camcc"; + reg =3D <0x0 0x0956d000 0x0 0x80000>; + + clocks =3D <&gcc GCC_CAMERA_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + dispcc: clock-controller@9ba2000 { + compatible =3D "qcom,kaanapali-dispcc"; + reg =3D <0x0 0x09ba2000 0x0 0x20000>; + clocks =3D <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + + #clock-cells =3D <1>; + #power-domain-cells =3D <1>; + #reset-cells =3D <1>; + }; + pdc: interrupt-controller@b220000 { compatible =3D "qcom,kaanapali-pdc", "qcom,pdc"; reg =3D <0x0 0x0b220000 0x0 0x10000>, --=20 2.25.1 From nobody Thu Apr 2 07:43:58 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A40B02F5313 for ; Wed, 25 Feb 2026 07:20:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772004040; cv=none; b=VxR73vSvDmzTDuFZOku4R6XtHETkH09GCEzcM9lW5tZlVdk0USnkXOCxehSk9fCXdMeb3kVrvf97w3HuAepvNDA+7OmD/ph/fTv3PZBpWyQD/TzcKTeO3FdZ9WvdVHmkOEETUGy4h0M8zlb5WGDfjoqkYJuTJYnzvlpJvFLyZBU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772004040; c=relaxed/simple; bh=RX2xvDlfbY2jB4gMuwAJiTjGu8FyoAFa5v+9xDn+jO4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=G/6Mixe5oDVDIlZ+EB9U2otikQcMkSAxfLPNlutHhHObfboBdkxyLqq1V+cT9EW4xL9ru+JxGpMOAM0jKS+otAIQOmbVwpbHnlugdzjYKKB+2mm+K7ME0CooOZgQ5/9pa4+gW5YmZJc0oGbLzWQksYEb+hs73kREeePtz9WXtZM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=VRMgnOWw; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=fo3Hf+P2; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="VRMgnOWw"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="fo3Hf+P2" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 61P0N37I061773 for ; Wed, 25 Feb 2026 07:20:38 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 38b2Y5v7C2CleGqNysqY7ea7ksqS4CP4xrO1wOPod/U=; b=VRMgnOWwo1j6ulH4 Ip+oqJrDuIyLNAmX6j8Opjr1dZSob0ROtIaM7S0n1CFoK7ejsurNLQH0/eDOOmCd AO45FfXRVlUdXvWz2YTuZlO61Ihu/NruMBHhiH/I56rUnRN2mAESgVTyje515/tU 98xkCRCOroCX96z6vYb76r2gV1S0fzEeSoWgI+QX6I7akmbOrr5X60R1brvSZw3t 3Nhsh1raYlmfX6eJGZeLT0ILDGyOtXZlYy0ZhoytT3GJ7RPf6kN6eJZZ1lq/hyT3 5fkhgcUuH5RRm/eDT7tqUeXZQIh4ubpnezJu3hDP/Op0QMz5hGuAajM1k6w1KO/r zkJY4w== Received: from mail-ot1-f69.google.com (mail-ot1-f69.google.com [209.85.210.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cherjamqg-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 25 Feb 2026 07:20:38 +0000 (GMT) Received: by mail-ot1-f69.google.com with SMTP id 46e09a7af769-7d4cb985fa3so26694586a34.2 for ; Tue, 24 Feb 2026 23:20:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1772004037; x=1772608837; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=38b2Y5v7C2CleGqNysqY7ea7ksqS4CP4xrO1wOPod/U=; b=fo3Hf+P2l6PzGVY8Yek6Trf4CsJfW3F7nwHAYBxy70QNQh/dRf6X75paS+C2glgiFC I2ep59szLWgv6Uq8XtIu2QPZRlOn+k7ugxOy4PsyThoQyOlgg8U7l/PoV9hw/0b0Sq07 hQ5aOty/6MzJ4jP28VEfbevB6XTC9qfvEs0s2cdvJbn0RnwKhZcLtmDf26nIDNT01b+h a1xNKb7WL2zKMy6ooa+k0SSmNQQ5t47k5We6vVqN1vMc4bg0h9KeJlGK3FB8+hWl4ICn vVy5p6GYCkcfMyEBoH6sxzFbQ8SlDyLAS8N3jXL3kw5X1Nfx4+6du8vmdDfVF6Sqtq8r NlqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772004037; x=1772608837; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=38b2Y5v7C2CleGqNysqY7ea7ksqS4CP4xrO1wOPod/U=; b=YQvcb1Tb2Ffb15HDD3xVbpzYECKUAaNddhVJZWDsLR3Sj0eGDGrK4SLDeXsyIPMiR5 evU7giBuc5nXY0o74dSVpBJ/VjPfq1MJtgXRNyoAb58+vFymDZRtd1VygJabpTo8FvwS /dR1/MCkqjRqfRjGQepLf/zfsmtZtc6gLyojZNw2Ylpe+hzi9BdPxyHX2VzVzTKqETZK n/eZhwmNh5eV0NKYVDcQ9L5X2mSXEvQCksbiRM23CTok4hmOp3FsNctDPuXTpge0SKE3 Zdzv4KPHksC7gDwO3P3hOaxfBeMBxlRUuFf/FCILTeG7ADc4hwApy33c6HoEApveXV6h coyQ== X-Forwarded-Encrypted: i=1; AJvYcCVMDSX+b1XyWYYJ5PSNlZ4nK2ze8snbLjbjog1cnvJcoka01VqCjBpmZEQlcTbLaBAUqKbtirJJ7ONCuEI=@vger.kernel.org X-Gm-Message-State: AOJu0YxEgXpE0OGlSVWPkZrq2dCHai2x4QykkP4gIq4SYQ3ZkfHzT/7a IFGRQCOqr7Z9iWFvgTmhS2h+1qmfns6JNLJxKFGxP4SdBkgoviCAPVO0TGMwax3l1q0vdGIy9m5 H3Kytx+doEWgAg+xFk4DjF9z6R0glG9E7Jxj67WaUicIVu0GHc2eSp1nD4FCCLRqmtA4jAuvoQp fZpg== X-Gm-Gg: ATEYQzycEwSIE1/SpF+CdTCG56frBi1O/M1c6bzdjoDNxM6REhI+0V2BDRfqrP988UP I6AyUj24QJwrVF5gTm/7Q0+dsQdqmqB1j+Rqeb0/w5bTBpMpjLJfpyn/5JAmkL/qYZ7sewjWq7K GDvE3pcN5YnUAx2gSCKMwNXSj1NcWHSPDlmTYCiipSHspqUM/jqS4pn2aq87cKMHOQaKUa1FVvi n0bp5k+L7wHXfZj4PmE8BvWkBhGWvOGwcRZsTeRn4ZrpIbNU5Me18rq6En8NcDu54+SD8TkSzYg JooQSQMJ/nQGV3Umg14j1tMD9Q0ubGPny4YyEhh4fvSO3mkizH0kfNtJUjsWqcdBXBbnd37mdcV 6Xz8Z/TamH9mo2FgTwNEx6UxnXSrbwojAciyyk8OTknxMr5/6F3BCFZRQQ5fja92jUsxlTHiK X-Received: by 2002:a05:6830:67c9:b0:7cf:da36:4cbb with SMTP id 46e09a7af769-7d52c1d65c6mr10004165a34.2.1772004037240; Tue, 24 Feb 2026 23:20:37 -0800 (PST) X-Received: by 2002:a05:6830:67c9:b0:7cf:da36:4cbb with SMTP id 46e09a7af769-7d52c1d65c6mr10004160a34.2.1772004036914; Tue, 24 Feb 2026 23:20:36 -0800 (PST) Received: from hu-jingyw-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7d52d038dcdsm11711730a34.16.2026.02.24.23.20.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Feb 2026 23:20:36 -0800 (PST) From: Jingyi Wang Date: Tue, 24 Feb 2026 23:19:25 -0800 Subject: [PATCH v6 10/10] arm64: defconfig: Enable Kaanapali clock controllers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260224-knp-dts-misc-v6-10-79d20dab8a60@oss.qualcomm.com> References: <20260224-knp-dts-misc-v6-0-79d20dab8a60@oss.qualcomm.com> In-Reply-To: <20260224-knp-dts-misc-v6-0-79d20dab8a60@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jingyi Wang , 20260114-knp-remoteproc-v4-0-fcf0b04d01af@oss.qualcomm.com, Taniya Das , Abel Vesa X-Mailer: b4 0.15-dev-3d134 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772004019; l=1019; i=jingyi.wang@oss.qualcomm.com; s=20250911; h=from:subject:message-id; bh=GwGDJFrSlIi28G0xKBu8W7R7zrPpokkDfUnwVZFXfnA=; b=7eKX0+jHRK5Acdl8fa6DZJpohKK8trw3F44eaaU7iKTJIGl73Zt4uDfNxEqUj0wLsW6P/iVKS y2dS/P6aoJiAAMczKJVA6AC7YnlfuvKw5jgJs2KKTfqX3UI1FvcNdHK X-Developer-Key: i=jingyi.wang@oss.qualcomm.com; a=ed25519; pk=PSoHZ6KbUss3IW8FPRVMHMK0Jkkr/jV347mBYJO3iLo= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjI1MDA3MCBTYWx0ZWRfXw4aXQwvAUt5H xsx5htaRm6PueewfQwvEEwmMhUCdYXVk0BFlVotbNIEad8jVeR6HZg/JnX4BeQr4VW9hFK9+JWs cL5dLsuFteN5PmcCVTGgHzuO4d4o+2iqhxGz3HlF47yuIW20x6kUjQpXBeuZPi3pdpMlwtepy0u d+sv/q8218zYker8xMsmEFT8wP3Z6xg3ZpFUQrTedANOn24yK697kP8AwK0losjTuhWkZ8QZtst xXyNLnxajq5Vx5A5iFDGLoM3RukaseJwXGEFW5PsvaitYnRgYhkADfm9hJbBGVlRG3E72fOz5bw ybJ9JUV7PA3ZH9qxghifhqS0457IhfWMhA6+4hcDGFOD+zg7UNRmCPDODWQ8dI4Yt1F3vH6FR8E QS1xKngE/SR7NHNknSbUSCZrQcl6g1zNm6XbfAkUPExhVCXHeyfQvxgYRTsMwLahi1UEe+wpT9J aoUPYqPKGLrtchFbs6A== X-Proofpoint-GUID: gRMXaRpo_zMkJutzxQ9MIE78ioGYUsOK X-Proofpoint-ORIG-GUID: gRMXaRpo_zMkJutzxQ9MIE78ioGYUsOK X-Authority-Analysis: v=2.4 cv=NeDrFmD4 c=1 sm=1 tr=0 ts=699ea2c6 cx=c_pps a=z9lCQkyTxNhZyzAvolXo/A==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=2LxjTKLKwRt7mIs9mlUA:9 a=QEXdDO2ut3YA:10 a=EyFUmsFV_t8cxB2kMr4A:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-24_03,2026-02-23_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 adultscore=0 spamscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602250070 From: Taniya Das Enable the Kaanapali display, video, camera and gpu clock controller for their respective functionalities on the Qualcomm Kaanapali QRD and MTP boards. Signed-off-by: Taniya Das Reviewed-by: Abel Vesa Signed-off-by: Jingyi Wang --- arch/arm64/configs/defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 4ed70ab7ee85..d1d51c2ef082 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1458,8 +1458,12 @@ CONFIG_COMMON_CLK_QCOM=3Dy CONFIG_CLK_GLYMUR_DISPCC=3Dm CONFIG_CLK_GLYMUR_GCC=3Dy CONFIG_CLK_GLYMUR_TCSRCC=3Dm +CONFIG_CLK_KAANAPALI_CAMCC=3Dm +CONFIG_CLK_KAANAPALI_DISPCC=3Dm CONFIG_CLK_KAANAPALI_GCC=3Dy +CONFIG_CLK_KAANAPALI_GPUCC=3Dm CONFIG_CLK_KAANAPALI_TCSRCC=3Dm +CONFIG_CLK_KAANAPALI_VIDEOCC=3Dm CONFIG_CLK_X1E80100_CAMCC=3Dm CONFIG_CLK_X1E80100_DISPCC=3Dm CONFIG_CLK_X1E80100_GCC=3Dy --=20 2.25.1