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Tue, 24 Feb 2026 06:47:00 -0800 (PST) From: Akhila YS Date: Tue, 24 Feb 2026 14:46:46 +0000 Subject: [PATCH v2 1/5] dt-bindings: arm: microchip,sama7g5-chipid : convert to DT schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260224-arm-microchip-v2-1-8bedacd2cdcb@gmail.com> References: <20260224-arm-microchip-v2-0-8bedacd2cdcb@gmail.com> In-Reply-To: <20260224-arm-microchip-v2-0-8bedacd2cdcb@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Alexandre Belloni , Claudiu Beznea Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Akhila YS X-Mailer: b4 0.14.3 Convert Atmel system registers binding to YAML format. Signed-off-by: Akhila YS --- .../bindings/arm/microchip,sama7g5-chipid.yaml | 41 ++++++++++++++++++= ++++ 1 file changed, 41 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/microchip,sama7g5-chipid= .yaml b/Documentation/devicetree/bindings/arm/microchip,sama7g5-chipid.yaml new file mode 100644 index 000000000000..0228a5505259 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/microchip,sama7g5-chipid.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/microchip,sama7g5-chipid.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel/Microchip RAMC SDRAM/DDR Controller + +maintainers: + - Nicolas Ferre + - Claudiu Beznea + +description: + This binding describes the Atmel/Microchip Chip ID register block used + for SoC identification and revision information. It requires compatible + strings matching specific SoC families and a reg property defining the + register address and size. + +properties: + compatible: + enum: + - atmel,sama5d2-chipid + - microchip,sama7g5-chipid + - microchip,sama7d65-chipid + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + chipid@fc069000 { + compatible =3D "atmel,sama5d2-chipid"; + reg =3D <0xfc069000 0x8>; + }; +... --=20 2.43.0 From nobody Fri Apr 17 01:39:42 2026 Received: from mail-pf1-f173.google.com (mail-pf1-f173.google.com [209.85.210.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F16933A0B1B for ; Tue, 24 Feb 2026 14:47:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771944429; cv=none; b=LKCpyNb5Py5NbPJLQI4aHvlFV6VkvSUY5YmsaQvxu9PIrL57H7MHy0/4LVeuPnetHSFHmpZF/kp7YjINq6OtIcIgnZMju+yq8fA2z56YRprt7f6WrIZKBpa8jcRjgj6LAAX/S8iEABzyc8HnMygHiq7C6KBP6VhE3a2sOkwcCyQ= ARC-Message-Signature: i=1; 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Tue, 24 Feb 2026 06:47:06 -0800 (PST) Received: from LAPTOP-872M7T80.localdomain ([122.168.64.105]) by smtp.googlemail.com with ESMTPSA id d2e1a72fcca58-826dd64367bsm11149895b3a.4.2026.02.24.06.47.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Feb 2026 06:47:06 -0800 (PST) From: Akhila YS Date: Tue, 24 Feb 2026 14:46:47 +0000 Subject: [PATCH v2 2/5] dt-bindings: arm: atmel,at91sam9260-pit: convert to DT schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260224-arm-microchip-v2-2-8bedacd2cdcb@gmail.com> References: <20260224-arm-microchip-v2-0-8bedacd2cdcb@gmail.com> In-Reply-To: <20260224-arm-microchip-v2-0-8bedacd2cdcb@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Alexandre Belloni , Claudiu Beznea Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Akhila YS X-Mailer: b4 0.14.3 Convert Atmel Periodic interval timer (PIT) binding to YAML format. Signed-off-by: Akhila YS --- .../bindings/arm/atmel,at91sam9260-pit.yaml | 49 ++++++++++++++++++= ++++ 1 file changed, 49 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/atmel,at91sam9260-pit.ya= ml b/Documentation/devicetree/bindings/arm/atmel,at91sam9260-pit.yaml new file mode 100644 index 000000000000..dbb5fd843a9b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/atmel,at91sam9260-pit.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/atmel,at91sam9260-pit.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel AT91SAM9260 Periodic Interval Timer (PIT) + +maintainers: + - Nicolas Ferre + - Claudiu Beznea + +description: + The Periodic Interval Timer (PIT) is part of the System Controller of + various Microchip 32-bit ARM-based SoCs (formerly Atmel AT91 series). + It is a simple down-counter timer used mainly as the kernel tick source. + The PIT is clocked from the slow clock and shares a single IRQ line with + other System Controller peripherals. + +properties: + compatible: + const: atmel,at91sam9260-pit + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + timer@fffffd30 { + compatible =3D "atmel,at91sam9260-pit"; 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Tue, 24 Feb 2026 06:47:11 -0800 (PST) From: Akhila YS Date: Tue, 24 Feb 2026 14:46:48 +0000 Subject: [PATCH v2 3/5] dt-bindings: arm: microchip,sam9x60-pit64b : convert to DT schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260224-arm-microchip-v2-3-8bedacd2cdcb@gmail.com> References: <20260224-arm-microchip-v2-0-8bedacd2cdcb@gmail.com> In-Reply-To: <20260224-arm-microchip-v2-0-8bedacd2cdcb@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Alexandre Belloni , Claudiu Beznea Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Akhila YS X-Mailer: b4 0.14.3 Convert Atmel Periodic interval timer of 64bit (PIT64b) binding to YAML format. Changes during conversion: - Add missing compatible "microchip,sama7g5-pit64b" along with a fallback compatible "microchip,sam9x60-pit64b". Signed-off-by: Akhila YS --- .../bindings/arm/microchip,sam9x60-pit64b.yaml | 68 ++++++++++++++++++= ++++ 1 file changed, 68 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/microchip,sam9x60-pit64b= .yaml b/Documentation/devicetree/bindings/arm/microchip,sam9x60-pit64b.yaml new file mode 100644 index 000000000000..cbc0a999748a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/microchip,sam9x60-pit64b.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/microchip,sam9x60-pit64b.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIT64B 64-bit Periodic Interval Timer + +maintainers: + - Nicolas Ferre + - Claudiu Beznea + +description: + The Microchip PIT64B is a 64-bit periodic interval timer used in + several modern Microchip ARM SoCs including SAM9X60, SAM9X7 and + SAMA7D65 families. It provides extended timing range, flexible + clock selection and supports both periodic and one-shot interrupt + generation modes. + +properties: + compatible: + oneOf: + - const: microchip,sam9x60-pit64b + - items: + - enum: + - microchip,sama7d65-pit64b + - microchip,sama7g5-pit64b + - microchip,sam9x7-pit64b + - const: microchip,sam9x60-pit64b + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + items: + enum: + - pclk + - gclk + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + #include + timer@f0028000 { + compatible =3D "microchip,sama7g5-pit64b", "microchip,sam9x60-pit6= 4b"; + reg =3D <0xf0028000 0x100>; + interrupts =3D <37 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; + clock-names =3D "pclk", "gclk"; + }; +... --=20 2.43.0 From nobody Fri Apr 17 01:39:42 2026 Received: from mail-pf1-f174.google.com (mail-pf1-f174.google.com [209.85.210.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2D461F8755 for ; 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Tue, 24 Feb 2026 06:47:16 -0800 (PST) Received: from LAPTOP-872M7T80.localdomain ([122.168.64.105]) by smtp.googlemail.com with ESMTPSA id d2e1a72fcca58-826dd64367bsm11149895b3a.4.2026.02.24.06.47.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Feb 2026 06:47:16 -0800 (PST) From: Akhila YS Date: Tue, 24 Feb 2026 14:46:49 +0000 Subject: [PATCH v2 4/5] dt-bindings: arm: atmel,at91rm9200-st: convert to DT schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260224-arm-microchip-v2-4-8bedacd2cdcb@gmail.com> References: <20260224-arm-microchip-v2-0-8bedacd2cdcb@gmail.com> In-Reply-To: <20260224-arm-microchip-v2-0-8bedacd2cdcb@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Alexandre Belloni , Claudiu Beznea Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Akhila YS X-Mailer: b4 0.14.3 Convert System Timer binding to YAML format. Signed-off-by: Akhila YS --- .../bindings/arm/atmel,at91rm9200-st.yaml | 65 ++++++++++++++++++= ++++ 1 file changed, 65 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/atmel,at91rm9200-st.yaml= b/Documentation/devicetree/bindings/arm/atmel,at91rm9200-st.yaml new file mode 100644 index 000000000000..ff485b37cba8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/atmel,at91rm9200-st.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/atmel,at91rm9200-st.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel System Timer + +maintainers: + - Nicolas Ferre + - Claudiu Beznea + +description: + The System Timer (ST) module in AT91RM9200 provides periodic tick and + alarm capabilities. It is exposed as a simple multi-function device + (simple-mfd + syscon) because it shares its register space and interrupt + with other System Controller blocks. + +properties: + compatible: + items: + - const: atmel,at91rm9200-st + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + watchdog: + type: object + description: Watchdog timer subnode. + properties: + compatible: + const: atmel,at91rm9200-wdt + required: + - compatible + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + timer@fffffd00 { + compatible =3D "atmel,at91rm9200-st", "syscon", "simple-mfd"; + reg =3D <0xfffffd00 0x100>; + interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&slow_xtal>; + + watchdog { + compatible =3D "atmel,at91rm9200-wdt"; + }; + }; +... --=20 2.43.0 From nobody Fri Apr 17 01:39:42 2026 Received: from mail-pf1-f182.google.com (mail-pf1-f182.google.com [209.85.210.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 513F43A0B30 for ; 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Tue, 24 Feb 2026 06:47:22 -0800 (PST) Received: from LAPTOP-872M7T80.localdomain ([122.168.64.105]) by smtp.googlemail.com with ESMTPSA id d2e1a72fcca58-826dd64367bsm11149895b3a.4.2026.02.24.06.47.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Feb 2026 06:47:21 -0800 (PST) From: Akhila YS Date: Tue, 24 Feb 2026 14:46:50 +0000 Subject: [PATCH v2 5/5] dt-bindings: arm: atmel,at91rm9200-sdramc: convert to DT schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260224-arm-microchip-v2-5-8bedacd2cdcb@gmail.com> References: <20260224-arm-microchip-v2-0-8bedacd2cdcb@gmail.com> In-Reply-To: <20260224-arm-microchip-v2-0-8bedacd2cdcb@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Alexandre Belloni , Claudiu Beznea Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Akhila YS X-Mailer: b4 0.14.3 Convert RAMC SDRAM/DDR controller binding to YAML format. Signed-off-by: Akhila YS --- .../bindings/arm/atmel,at91rm9200-sdramc.yaml | 67 ++++++++++++++++++= ++++ .../devicetree/bindings/arm/atmel-sysregs.txt | 48 ---------------- 2 files changed, 67 insertions(+), 48 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/atmel,at91rm9200-sdramc.= yaml b/Documentation/devicetree/bindings/arm/atmel,at91rm9200-sdramc.yaml new file mode 100644 index 000000000000..2cc07a772063 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/atmel,at91rm9200-sdramc.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/atmel,at91rm9200-sdramc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip (Atmel) SDRAM / DDR Controller (RAMC / DDRAMC / UDDRC) + +maintainers: + - Nicolas Ferre + - Claudiu Beznea + +description: + The SDRAM/DDR Controller (often called RAMC or DDRAMC) in various + Atmel/Microchip ARM9 and Cortex-A5/A7 SoCs manages external + SDRAM / DDR memory. It is typically exposed as a syscon node for + register access from other drivers (e.g. for initialization or mode + configuration). No interrupts or clocks are usually required in the + binding. + +properties: + compatible: + oneOf: + - items: + - const: atmel,at91rm9200-sdramc + - const: syscon + - items: + - const: microchip,sama7d65-uddrc + - const: microchip,sama7g5-uddrc + - items: + enum: + - atmel,at91sam9260-sdramc + - atmel,at91sam9g45-ddramc + - atmel,sama5d3-ddramc + - microchip,sam9x60-ddramc + - microchip,sam9x7-ddramc + - microchip,sama7g5-uddrc + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: ddrck + - const: mpddr + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + ramc@ffffe400 { + compatible =3D "atmel,at91sam9g45-ddramc"; + reg =3D <0xffffe400 0x200>; + clocks =3D <&pmc PMC_TYPE_SYSTEM 2>; + clock-names =3D "ddrck"; + }; +... diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Docu= mentation/devicetree/bindings/arm/atmel-sysregs.txt deleted file mode 100644 index 5ce54f9befe6..000000000000 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ /dev/null @@ -1,48 +0,0 @@ -Atmel system registers - -Chipid required properties: -- compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipi= d" - "microchip,sama7d65-chipid" -- reg : Should contain registers location and length - -PIT Timer required properties: -- compatible: Should be "atmel,at91sam9260-pit" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt for the PIT which is the IRQ line - shared across all System Controller members. - -PIT64B Timer required properties: -- compatible: Should be "microchip,sam9x60-pit64b" or - "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b" - "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt for PIT64B timer -- clocks: Should contain the available clock sources for PIT64B timer. - -System Timer (ST) required properties: -- compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt for the ST which is the IRQ line - shared across all System Controller members. -- clocks: phandle to input clock. -Its subnodes can be: -- watchdog: compatible should be "atmel,at91rm9200-wdt" - -RAMC SDRAM/DDR Controller required properties: -- compatible: Should be "atmel,at91rm9200-sdramc", "syscon" or - "atmel,at91sam9260-sdramc" or - "atmel,at91sam9g45-ddramc" or - "atmel,sama5d3-ddramc" or - "microchip,sam9x60-ddramc" or - "microchip,sama7g5-uddrc" or - "microchip,sama7d65-uddrc", "microchip,sama7g5-uddrc" or - "microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc". -- reg: Should contain registers location and length - -Examples: - - ramc0: ramc@ffffe800 { - compatible =3D "atmel,at91sam9g45-ddramc"; - reg =3D <0xffffe800 0x200>; - }; - --=20 2.43.0