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Mon, 23 Feb 2026 12:42:38 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Richard Cochran , , , , , Gal Pressman , Dragos Tatulea , Cosmin Ratiu , Pavel Begunkov , David Wei Subject: [PATCH net-next 01/15] net/mlx5e: Make mlx5e_rq_param naming consistent Date: Mon, 23 Feb 2026 22:41:41 +0200 Message-ID: <20260223204155.1783580-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260223204155.1783580-1-tariqt@nvidia.com> References: <20260223204155.1783580-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC9:EE_|SA1PR12MB7125:EE_ X-MS-Office365-Filtering-Correlation-Id: fa17f28d-f2e4-45e6-6016-08de731c2229 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?bgXKRBP+EQAVwDk6SCW9PsVIdkQna/zefGwhRx+aT+OVU6AGfCgndUZUH4uz?= =?us-ascii?Q?IHdBqhW8VGnu6ctE/Mgw94j/l9EFjxkQGZSET+zUN/2NOXsmzgtWAUnJ/OEn?= =?us-ascii?Q?Py0FWRMECyJhbPpJzK5Hjid7YZgzFJhiWvoyP9ULiPqqVHmO/3yzvChMLZby?= =?us-ascii?Q?cFJUoG4YlXqPEFJQzxZrGG6sotJkt54zKVygXQU9Hd+2XUJwlAO9eAKVSmo6?= =?us-ascii?Q?wfXu8w2Rvcern8R8d7eMOyxKXLQYAwKwRLLoD6oyaWR8H6jLIqz8kngEsTEu?= =?us-ascii?Q?WaAg7eTBPa9iwwlDTsnhJVZ2F1cSZFvVmrQG5XxQ64DBUzQJI4UsZurhRLGS?= =?us-ascii?Q?3/I/+NXpxqACCNksUYNkMb7WNK9s88ufeyP2+0UmpMvzB/NxYekQlq7ALDcu?= =?us-ascii?Q?YFvFv34krsxhFbhFlG62dMFBBH/wZ1Hwg7og5V3U+SW2kpUEnd9rmQ8WtKWD?= =?us-ascii?Q?Sn+Z726dbNofs7ExBKhMALPkSkQaZNmASRw8/APuaQl/7tc5pubBDqyLv29e?= =?us-ascii?Q?8bLSF1tG8Wo++FVsogWEAFyKi15RG1Kt1fis5J9g/SvYduZr9FkPRso+sMAb?= =?us-ascii?Q?W8BB4XXrrgEaG7T0Mk2+MSX8LUJT0P+bRIm3azQij1MxJ3yTaCTNX1Nt/hbw?= =?us-ascii?Q?DQ8rTo6FYm8ppwuD1PoQX3a2rlBSnlUtafdFWgqQKSCW1VR0gUwYzvE/pm5I?= =?us-ascii?Q?00NrG3Jod3Z6L6fW573hcpNG1jxzWlq0oTs4K+YGcTp+N7da83Ke24Ar+ov5?= =?us-ascii?Q?fcO5T0Ou83g8NZQWS71qjqDucDMWGCjS3E4iOt+9KJZBWw1Ne/pXKj/0xNGu?= =?us-ascii?Q?hArJZeKf2oLSPbjuis65/rJCsDS+26bFngk52HNpBMLU8oXblDw/nFmxvQfb?= =?us-ascii?Q?WdRYEalwCHHDdf6Y/v5VoACi3fFtyBCCyaNgd4W8OoLr8Z158aA0ioAMpbKl?= =?us-ascii?Q?2OO1klEnQAhLlXeEJWYywhutaJ1Us38AvB87cLKsP+01mshHIugNZ7NCyP3g?= =?us-ascii?Q?GmuQEnV4yP/DKXH/A8qK5mJvfatK1CcwUtlZMf0BC5zf9F53hCyp61X5CPQ7?= =?us-ascii?Q?fwDcbXyj4QjXraEMpJnSKV/4pTV2bXIMgVNm5OSR99g9JWTOMKk9KrTrG+Kf?= =?us-ascii?Q?p3g4ZyyAmiOYIbhVxG5TolTF3MewKptg3TCF8w2eQdRBDJL3aOYPd1TIJlNu?= =?us-ascii?Q?KT77xhlNXdzMRWVH93VAp5bm7XPJ6Az47HIEkd5Mn6eJ/H55R007Wg9Zk5lf?= =?us-ascii?Q?ppsJ509ArBG0Xc89piWKy0ob3mUiJalyzzQH1NRUXfz7FBwOmN7tH21SJ7RA?= =?us-ascii?Q?G9ECspwvS3PvrIDHaplnrL+spXdJE4h1/iM0Qwb4DH2T6CikxEXVWgt+OLqK?= =?us-ascii?Q?Rguvi+psMSaTwoO+g2hlKY83IVjiRURdILvHwsY9s9QEDls8LJk/mKaLPDiU?= =?us-ascii?Q?c1xVwldwPI5IR6sC6Ex+XYUf+eis3JYMQgcdzMJEMBDSiU4XE9JkvGKizHwh?= =?us-ascii?Q?dfA8g2ahOirPsfzOknEZFe7or1VxVoAZXyDoucMCQbMxEE3wMy2KOFEwwzKR?= =?us-ascii?Q?cTdT00DOVdZ9KKsx917s8UyN5vNlKKuwD556wb7/HDnIAkfZ2KZXt59H/Buo?= =?us-ascii?Q?G65ICvIrRb3jLfUY2VYNWVUaAt65A7HhqE/KdmJDopR9t+wampY7t0n2FyWV?= =?us-ascii?Q?Kw9O6Q=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(36860700013)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: xrIkHdlOkUBWbFXj7wlCtbBAWtfLnuGYZ3IMdVuZfS4NZmRKXdsfyCnHqPweHYdLhDRytEGQP3i14CBZdJ+Le3Q27FCKbVGMnIU/eE6irU4j41//TWwpJsKWEEkCKcdIVJHadeHuoTMI6uxvS/52SM1HGrfLLlWMMzneI0I4C2U35OjNBf8oeqRRpZJ+N+ufeEdZ01jxF70HTpT+JAIPNu9xc8cUB99IzxIy2mZr8JeQhfueepgmzjU/dwONyabePRsNwHefW0ZWB/4VsaYVwv6N8qW4fig5vomfFHsTCUaXlrlOF/p9RjIb5CpMwKu9lw5ORugTMde+TE1SCcC4g8D/8CK/EIrzAyN5uGbvF3QCGIBAThP2d5ebgz28P5X9fKWqB5wdKT7aiRme4vXBWYs9Wu+/uPn/zFfvvQc1eHD7fMo4WF0M4Mp6boEsGOJF X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Feb 2026 20:43:00.1030 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fa17f28d-f2e4-45e6-6016-08de731c2229 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC9.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7125 Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea This structure is used under different names: rq_param, rq_params, param, rqp. Refactor the code to use a single name: rq_param. This patch has no functional change. Signed-off-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 5 +- .../ethernet/mellanox/mlx5/core/en/params.c | 27 +++++----- .../net/ethernet/mellanox/mlx5/core/en/ptp.c | 4 +- .../mellanox/mlx5/core/en/xsk/setup.c | 9 ++-- .../net/ethernet/mellanox/mlx5/core/en_main.c | 50 +++++++++---------- 5 files changed, 51 insertions(+), 44 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index ea2cd1f5d1d0..550426979627 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -1060,13 +1060,14 @@ void mlx5e_timestamp_init(struct mlx5e_priv *priv); struct mlx5e_xsk_param; =20 struct mlx5e_rq_param; -int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *para= m, +int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *rq_p= aram, struct mlx5e_xsk_param *xsk, int node, u16 q_counter, struct mlx5e_rq *rq); #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */ int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time); void mlx5e_close_rq(struct mlx5e_rq *rq); -int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param, u16= q_counter); +int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *rq_param, + u16 q_counter); void mlx5e_destroy_rq(struct mlx5e_rq *rq); =20 bool mlx5e_reset_rx_moderation(struct dim_cq_moder *cq_moder, u8 cq_period= _mode, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c b/drivers/= net/ethernet/mellanox/mlx5/core/en/params.c index 8e99d07586fa..3fdaf003e1d0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c @@ -883,14 +883,16 @@ static u8 rq_end_pad_mode(struct mlx5_core_dev *mdev,= struct mlx5e_params *param int mlx5e_build_rq_param(struct mlx5_core_dev *mdev, struct mlx5e_params *params, struct mlx5e_xsk_param *xsk, - struct mlx5e_rq_param *param) + struct mlx5e_rq_param *rq_param) { - void *rqc =3D param->rqc; - void *wq =3D MLX5_ADDR_OF(rqc, rqc, wq); + void *rqc =3D rq_param->rqc; u32 lro_timeout; int ndsegs =3D 1; + void *wq; int err; =20 + wq =3D MLX5_ADDR_OF(rqc, rqc, wq); + switch (params->rq_wq_type) { case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: { u8 log_wqe_num_of_strides =3D mlx5e_mpwqe_get_log_num_strides(mdev, para= ms, xsk); @@ -938,11 +940,12 @@ int mlx5e_build_rq_param(struct mlx5_core_dev *mdev, } default: /* MLX5_WQ_TYPE_CYCLIC */ MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames); - err =3D mlx5e_build_rq_frags_info(mdev, params, xsk, ¶m->frags_info, - ¶m->xdp_frag_size); + err =3D mlx5e_build_rq_frags_info(mdev, params, xsk, + &rq_param->frags_info, + &rq_param->xdp_frag_size); if (err) return err; - ndsegs =3D param->frags_info.num_frags; + ndsegs =3D rq_param->frags_info.num_frags; } =20 MLX5_SET(wq, wq, wq_type, params->rq_wq_type); @@ -953,23 +956,23 @@ int mlx5e_build_rq_param(struct mlx5_core_dev *mdev, MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable); MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en); =20 - param->wq.buf_numa_node =3D dev_to_node(mlx5_core_dma_dev(mdev)); - mlx5e_build_rx_cq_param(mdev, params, xsk, ¶m->cqp); + rq_param->wq.buf_numa_node =3D dev_to_node(mlx5_core_dma_dev(mdev)); + mlx5e_build_rx_cq_param(mdev, params, xsk, &rq_param->cqp); =20 return 0; } =20 void mlx5e_build_drop_rq_param(struct mlx5_core_dev *mdev, - struct mlx5e_rq_param *param) + struct mlx5e_rq_param *rq_param) { - void *rqc =3D param->rqc; + void *rqc =3D rq_param->rqc; void *wq =3D MLX5_ADDR_OF(rqc, rqc, wq); =20 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); MLX5_SET(wq, wq, log_wq_stride, mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1)); =20 - param->wq.buf_numa_node =3D dev_to_node(mlx5_core_dma_dev(mdev)); + rq_param->wq.buf_numa_node =3D dev_to_node(mlx5_core_dma_dev(mdev)); } =20 void mlx5e_build_tx_cq_param(struct mlx5_core_dev *mdev, @@ -1097,7 +1100,7 @@ static u32 mlx5e_mpwrq_total_umr_wqebbs(struct mlx5_c= ore_dev *mdev, =20 static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5_core_dev *mdev, struct mlx5e_params *params, - struct mlx5e_rq_param *rqp) + struct mlx5e_rq_param *rq_param) { u32 wqebbs, total_pages, useful_space; =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c b/drivers/net= /ethernet/mellanox/mlx5/core/en/ptp.c index 74660e7fe674..13add74d1b97 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c @@ -660,13 +660,13 @@ static void mlx5e_ptp_build_rq_param(struct mlx5_core= _dev *mdev, struct net_device *netdev, struct mlx5e_ptp_params *ptp_params) { - struct mlx5e_rq_param *rq_params =3D &ptp_params->rq_param; + struct mlx5e_rq_param *rq_param =3D &ptp_params->rq_param; struct mlx5e_params *params =3D &ptp_params->params; =20 params->rq_wq_type =3D MLX5_WQ_TYPE_CYCLIC; mlx5e_init_rq_type_params(mdev, params); params->sw_mtu =3D netdev->max_mtu; - mlx5e_build_rq_param(mdev, params, NULL, rq_params); + mlx5e_build_rq_param(mdev, params, NULL, rq_param); } =20 static void mlx5e_ptp_build_params(struct mlx5e_ptp *c, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c b/drive= rs/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c index 5981c71cae2d..50c14ad29ed6 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c @@ -90,8 +90,10 @@ static int mlx5e_init_xsk_rq(struct mlx5e_channel *c, return xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq_xdp_ix, c->napi.napi= _id); } =20 -static int mlx5e_open_xsk_rq(struct mlx5e_channel *c, struct mlx5e_params = *params, - struct mlx5e_rq_param *rq_params, struct xsk_buff_pool *pool, +static int mlx5e_open_xsk_rq(struct mlx5e_channel *c, + struct mlx5e_params *params, + struct mlx5e_rq_param *rq_param, + struct xsk_buff_pool *pool, struct mlx5e_xsk_param *xsk) { u16 q_counter =3D c->priv->q_counter[c->sd_ix]; @@ -102,7 +104,8 @@ static int mlx5e_open_xsk_rq(struct mlx5e_channel *c, s= truct mlx5e_params *param if (err) return err; =20 - err =3D mlx5e_open_rq(params, rq_params, xsk, cpu_to_node(c->cpu), q_coun= ter, xskrq); + err =3D mlx5e_open_rq(params, rq_param, xsk, cpu_to_node(c->cpu), + q_counter, xskrq); if (err) return err; =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 7eb691c2a1bd..f2ce24cf56ce 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -780,7 +780,7 @@ static int mlx5e_create_rq_hd_mkey(struct mlx5_core_dev= *mdev, =20 static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *mdev, struct mlx5e_params *params, - struct mlx5e_rq_param *rqp, + struct mlx5e_rq_param *rq_param, struct mlx5e_rq *rq, int node) { @@ -791,7 +791,7 @@ static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *m= dev, if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) return 0; =20 - hd_per_wq =3D mlx5e_shampo_hd_per_wq(mdev, params, rqp); + hd_per_wq =3D mlx5e_shampo_hd_per_wq(mdev, params, rq_param); hd_buf_size =3D hd_per_wq * BIT(MLX5E_SHAMPO_LOG_HEADER_ENTRY_SIZE); nentries =3D hd_buf_size / PAGE_SIZE; if (!nentries) { @@ -852,18 +852,17 @@ static void mlx5e_rq_free_shampo(struct mlx5e_rq *rq) =20 static int mlx5e_alloc_rq(struct mlx5e_params *params, struct mlx5e_xsk_param *xsk, - struct mlx5e_rq_param *rqp, + struct mlx5e_rq_param *rq_param, int node, struct mlx5e_rq *rq) { + void *rqc_wq =3D MLX5_ADDR_OF(rqc, rq_param->rqc, wq); struct mlx5_core_dev *mdev =3D rq->mdev; - void *rqc =3D rqp->rqc; - void *rqc_wq =3D MLX5_ADDR_OF(rqc, rqc, wq); u32 pool_size; int wq_sz; int err; int i; =20 - rqp->wq.db_numa_node =3D node; + rq_param->wq.db_numa_node =3D node; INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work); INIT_WORK(&rq->rx_timeout_work, mlx5e_rq_timeout_work); =20 @@ -879,8 +878,8 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params, =20 switch (rq->wq_type) { case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: - err =3D mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq, - &rq->wq_ctrl); + err =3D mlx5_wq_ll_create(mdev, &rq_param->wq, rqc_wq, + &rq->mpwqe.wq, &rq->wq_ctrl); if (err) goto err_rq_xdp_prog; =20 @@ -925,14 +924,14 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params, if (err) goto err_rq_mkey; =20 - err =3D mlx5_rq_shampo_alloc(mdev, params, rqp, rq, node); + err =3D mlx5_rq_shampo_alloc(mdev, params, rq_param, rq, node); if (err) goto err_free_mpwqe_info; =20 break; default: /* MLX5_WQ_TYPE_CYCLIC */ - err =3D mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq, - &rq->wq_ctrl); + err =3D mlx5_wq_cyc_create(mdev, &rq_param->wq, rqc_wq, + &rq->wqe.wq, &rq->wq_ctrl); if (err) goto err_rq_xdp_prog; =20 @@ -940,7 +939,7 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params, =20 wq_sz =3D mlx5_wq_cyc_get_size(&rq->wqe.wq); =20 - rq->wqe.info =3D rqp->frags_info; + rq->wqe.info =3D rq_param->frags_info; rq->buff.frame0_sz =3D rq->wqe.info.arr[0].frag_stride; =20 err =3D mlx5e_init_wqe_alloc_info(rq, node); @@ -1085,7 +1084,8 @@ static void mlx5e_free_rq(struct mlx5e_rq *rq) xdp_rxq_info_unreg(&rq->xdp_rxq); } =20 -int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param, u16= q_counter) +int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *rq_param, + u16 q_counter) { struct mlx5_core_dev *mdev =3D rq->mdev; u8 ts_format; @@ -1107,7 +1107,7 @@ int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e= _rq_param *param, u16 q_cou rqc =3D MLX5_ADDR_OF(create_rq_in, in, ctx); wq =3D MLX5_ADDR_OF(rqc, rqc, wq); =20 - memcpy(rqc, param->rqc, sizeof(param->rqc)); + memcpy(rqc, rq_param->rqc, sizeof(rq_param->rqc)); =20 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn); MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); @@ -1323,7 +1323,7 @@ void mlx5e_free_rx_descs(struct mlx5e_rq *rq) =20 } =20 -int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *para= m, +int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *rq_p= aram, struct mlx5e_xsk_param *xsk, int node, u16 q_counter, struct mlx5e_rq *rq) { @@ -1333,11 +1333,11 @@ int mlx5e_open_rq(struct mlx5e_params *params, stru= ct mlx5e_rq_param *param, if (params->packet_merge.type =3D=3D MLX5E_PACKET_MERGE_SHAMPO) __set_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state); =20 - err =3D mlx5e_alloc_rq(params, xsk, param, node, rq); + err =3D mlx5e_alloc_rq(params, xsk, rq_param, node, rq); if (err) return err; =20 - err =3D mlx5e_create_rq(rq, param, q_counter); + err =3D mlx5e_create_rq(rq, rq_param, q_counter); if (err) goto err_free_rq; =20 @@ -2507,16 +2507,17 @@ static int mlx5e_set_tx_maxrate(struct net_device *= dev, int index, u32 rate) } =20 static int mlx5e_open_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params = *params, - struct mlx5e_rq_param *rq_params) + struct mlx5e_rq_param *rq_param) { u16 q_counter =3D c->priv->q_counter[c->sd_ix]; int err; =20 - err =3D mlx5e_init_rxq_rq(c, params, rq_params->xdp_frag_size, &c->rq); + err =3D mlx5e_init_rxq_rq(c, params, rq_param->xdp_frag_size, &c->rq); if (err) return err; =20 - return mlx5e_open_rq(params, rq_params, NULL, cpu_to_node(c->cpu), q_coun= ter, &c->rq); + return mlx5e_open_rq(params, rq_param, NULL, cpu_to_node(c->cpu), + q_counter, &c->rq); } =20 static struct mlx5e_icosq * @@ -3577,15 +3578,14 @@ static void mlx5e_free_drop_rq(struct mlx5e_rq *rq) =20 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq, - struct mlx5e_rq_param *param) + struct mlx5e_rq_param *rq_param) { - void *rqc =3D param->rqc; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Richard Cochran , , , , , Gal Pressman , Dragos Tatulea , Cosmin Ratiu , Pavel Begunkov , David Wei Subject: [PATCH net-next 02/15] net/mlx5e: Extract striding rq param calculation in function Date: Mon, 23 Feb 2026 22:41:42 +0200 Message-ID: <20260223204155.1783580-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260223204155.1783580-1-tariqt@nvidia.com> References: <20260223204155.1783580-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000206:EE_|DM4PR12MB6327:EE_ X-MS-Office365-Filtering-Correlation-Id: ee4f2b31-f676-41df-1949-08de731c253b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?rDGR/knnNFh5Ei9S/aDitKyWjX2jGqilTcdcappI3TcBPIqfxZ2AQLZUofQ/?= =?us-ascii?Q?dS1DlKZoCpR84RbXsIEtFZblp55KljIr+HT84/ymnoWhCMx84+t2q3RVEQpQ?= =?us-ascii?Q?HXE+Hu3TG3HDhnppliU9HBlrMgPeRjZllOUKXNbepIDM4tWQ3bVa4fGYwPWA?= =?us-ascii?Q?7GsZ73JHDnPBtUFInJjndkJQP+sCNXdB4K8tzaHRF4kZCPrq7LaxY7nVZFjP?= =?us-ascii?Q?IhmZNK1ZiDdJjsyGak62EUHhhoG91XpmMZu+1f0Ofh+1yK1yTRMDq8Iw9PdA?= =?us-ascii?Q?iY4NAhodN9xom1SZdXUcTHIZ7+bscS3p9/OzQ+20TXUmbbunVGc9++lmweaT?= =?us-ascii?Q?f+/4zCr2UH/VUOTIW7lKFW99VQJG3eB7/qjYm2pgahsFsObYyU8qfn/9bYrz?= =?us-ascii?Q?9nJZFX/bMa6LTLsK4sea/1IV/qllMfrGPta1oEvopai/9bjmpJz1k7swY0Zz?= =?us-ascii?Q?0+ax3K2fcCXc841r9Y8rHFWrSF+6vqQDb8eyNCnMRdCuORk5t5Ff0X9B5DAD?= =?us-ascii?Q?Sjnu2ZCYU7qj91tuayK5Pc0h32do60rpP9gaKrvcbMhNnJ2IM5rCz2IJZ6Qc?= =?us-ascii?Q?DeygdbHhDm/I7nfHf9F1l3TFFFPUEEOwPuidXPVi9HuSlQ9k753dj2Ulzqve?= =?us-ascii?Q?2VQ4G85wMe2hHUUlOzign+vzK1NXVbhDkFvLoxKFHFHfRe2IbUFhIlGfwuvF?= =?us-ascii?Q?VAmrja60zET0hJNm2QIjWjFmNSImZWwihG5QADIWUyUhnD6dssIMQIpCGLSH?= =?us-ascii?Q?Gf+VuNZsaXZAOHRo4k8B+JrJMa9fY34GkUposp5ekPMD6tbumr0GrgVEc+l4?= =?us-ascii?Q?kjw9C6XgpS8BFsDaj3Y3+6lBsSKcq49sackX4aLhY8591XNZnPM/YG8FMwWD?= =?us-ascii?Q?j/9uccGpDN77iWOFI/m8twol8TfbcA5n1F6aeFryKYUKokSG7e+JTdOchBI3?= =?us-ascii?Q?YlQSfeyuKI1qIRaLL/JIsMKYf10I09nUrhkfzUprl+y+AwoAy/uIFfoyMTsE?= =?us-ascii?Q?vbVMnrEOOhbsIe/rWzq3LMmNoCnrZ1zF2sB83LHBy5rzKuqAeIfMxbtMpizD?= =?us-ascii?Q?+ml/HM0rVDzGdy8X++QZKelMnB/jzW3Ielos2lBP3Z6LoN7o/EZSBX26kUvh?= =?us-ascii?Q?dM5N1EJGsq3yy2CoHvYSNys0F7ZHuwKNt9wlOVr+wgmaUbzKeHv+ZytaiFUP?= =?us-ascii?Q?boJlEzO8vRKxSD9a1PU06yzpR+gKO2EsEeokxkZktraTDBoWxDLvT5WHNUVW?= =?us-ascii?Q?IB3Y+DWp3P0QfKqVNmReuUzpBv2AKMzsZUDNBdw6Gy4DE0vRfXl4lWHyY5ff?= =?us-ascii?Q?WTUjxXh5asShQFhNBUVgj4p74EY6ixk0n9+sqbDg7/aZVezVtQHFsfjChnQ9?= =?us-ascii?Q?nBZFMUOOtq6zfCFvWHvSnPRkckmswnMOS6vOeefTG4ljADc9k93z2O2/NcNt?= =?us-ascii?Q?yEVpJLuV2WAOOWBwQq0WHaz4hVrKSQYL4b9FSLtYD051SucYzVwgYZ86d/7l?= =?us-ascii?Q?qb1efX17UnHfR0Mrkntuoe0lxOS8urGTHL1PXOPNBjbry5jmtmqwlFplxmlI?= =?us-ascii?Q?LMMDBDNGD/g0uppfR12+wMI6ldWBkmHUv/mCBplhPpYqhaSo8IYg5jk1t9DL?= =?us-ascii?Q?Hqnyf5Q21Rv0EtedEqF2Y08bEGYWtZmLiZ/qGH6kjBIA9Egn7YF1ZT2nudqG?= =?us-ascii?Q?1mTMLw=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: lcid46Yg7WSFy6vsQp0zJVYnur6S23FykJUj4gZFIYVYhYuwAXm7Av2bk1Ji4jAfTRDlRANYF6RG5QLHV1TmOFysJ5/5aVN3tyN8BmtEFJ8hNVOURtghE33UxaS7xBrE/gokj5lL+HKAN+xBSi2ZYgTTh9VJndUDfjxk4KNYr/ji/kcnOeIMGTRD+L0oRtFlT5+pXF/OAjmblKGfROrPHsXkkVHcfiGqgYxUHiKgHLWRPygo3ug8oXhHMaiJyRQegIskEIlvhq9O4+eps5CxMvH+1JO2vFxeB1o9fxuxhP72vbwy6j8fIH49agst4+3NJyk7VbNDjsAhWxDemNRnTrsI2Skn161TAF31XZKxHcR+g6s5E3CiqBwsAZOeUq2JWMbhbHIyy8u4n17eHZPzbfFY7vtq+WZhrdaGlZhN5My/rjemAklUBZjZJwuOKXbv X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Feb 2026 20:43:05.3714 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ee4f2b31-f676-41df-1949-08de731c253b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000206.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6327 Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea Calculating parameters for striding rq is large enough to deserve its own function. As the names are also very long it is very easy to hit on the 80 char limitation every time a change is made. This is an additional sign that it should be extracted into its own function. This patch has no functional change. Signed-off-by: Dragos Tatulea Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/en/params.c | 106 ++++++++++-------- 1 file changed, 62 insertions(+), 44 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c b/drivers/= net/ethernet/mellanox/mlx5/core/en/params.c index 3fdaf003e1d0..07d75a85ee7f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c @@ -880,13 +880,70 @@ static u8 rq_end_pad_mode(struct mlx5_core_dev *mdev,= struct mlx5e_params *param MLX5_WQ_END_PAD_MODE_NONE : MLX5_WQ_END_PAD_MODE_ALIGN; } =20 +static int mlx5e_mpwqe_build_rq_param(struct mlx5_core_dev *mdev, + struct mlx5e_params *params, + struct mlx5e_xsk_param *xsk, + struct mlx5e_rq_param *rq_param) +{ + u8 log_rq_sz =3D mlx5e_mpwqe_get_log_rq_size(mdev, params, xsk); + u8 page_shift =3D mlx5e_mpwrq_page_shift(mdev, xsk); + u8 log_wqe_num_of_strides, log_wqe_stride_size; + enum mlx5e_mpwrq_umr_mode umr_mode; + void *rqc =3D rq_param->rqc; + u32 lro_timeout; + void *wq; + + log_wqe_num_of_strides =3D mlx5e_mpwqe_get_log_num_strides(mdev, params, + xsk); + log_wqe_stride_size =3D mlx5e_mpwqe_get_log_stride_size(mdev, params, + xsk); + umr_mode =3D mlx5e_mpwrq_umr_mode(mdev, xsk); + + wq =3D MLX5_ADDR_OF(rqc, rqc, wq); + if (!mlx5e_verify_rx_mpwqe_strides(mdev, log_wqe_stride_size, + log_wqe_num_of_strides, + page_shift, umr_mode)) { + mlx5_core_err(mdev, + "Bad RX MPWQE params: log_stride_size %u, log_num_strides %u, umr= _mode %d\n", + log_wqe_stride_size, log_wqe_num_of_strides, + umr_mode); + return -EINVAL; + } + + MLX5_SET(wq, wq, log_wqe_num_of_strides, + log_wqe_num_of_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE); + MLX5_SET(wq, wq, log_wqe_stride_size, + log_wqe_stride_size - MLX5_MPWQE_LOG_STRIDE_SZ_BASE); + MLX5_SET(wq, wq, log_wq_sz, log_rq_sz); + if (params->packet_merge.type !=3D MLX5E_PACKET_MERGE_SHAMPO) + return 0; + + MLX5_SET(wq, wq, shampo_enable, true); + MLX5_SET(wq, wq, log_reservation_size, + MLX5E_SHAMPO_WQ_LOG_RESRV_SIZE - + MLX5E_SHAMPO_WQ_RESRV_SIZE_BASE_SHIFT); + MLX5_SET(wq, wq, log_max_num_of_packets_per_reservation, + mlx5e_shampo_get_log_pkt_per_rsrv(params)); + MLX5_SET(wq, wq, log_headers_entry_size, + MLX5E_SHAMPO_LOG_HEADER_ENTRY_SIZE - + MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE_SHIFT); + lro_timeout =3D mlx5e_choose_lro_timeout(mdev, + MLX5E_DEFAULT_SHAMPO_TIMEOUT); + MLX5_SET(rqc, rqc, reservation_timeout, lro_timeout); + MLX5_SET(rqc, rqc, shampo_match_criteria_type, + MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED); + MLX5_SET(rqc, rqc, shampo_no_match_alignment_granularity, + MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE); + + return 0; +} + int mlx5e_build_rq_param(struct mlx5_core_dev *mdev, struct mlx5e_params *params, struct mlx5e_xsk_param *xsk, struct mlx5e_rq_param *rq_param) { void *rqc =3D rq_param->rqc; - u32 lro_timeout; int ndsegs =3D 1; void *wq; int err; @@ -894,50 +951,11 @@ int mlx5e_build_rq_param(struct mlx5_core_dev *mdev, wq =3D MLX5_ADDR_OF(rqc, rqc, wq); =20 switch (params->rq_wq_type) { - case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: { - u8 log_wqe_num_of_strides =3D mlx5e_mpwqe_get_log_num_strides(mdev, para= ms, xsk); - u8 log_wqe_stride_size =3D mlx5e_mpwqe_get_log_stride_size(mdev, params,= xsk); - enum mlx5e_mpwrq_umr_mode umr_mode =3D mlx5e_mpwrq_umr_mode(mdev, xsk); - u8 page_shift =3D mlx5e_mpwrq_page_shift(mdev, xsk); - - if (!mlx5e_verify_rx_mpwqe_strides(mdev, log_wqe_stride_size, - log_wqe_num_of_strides, - page_shift, umr_mode)) { - mlx5_core_err(mdev, - "Bad RX MPWQE params: log_stride_size %u, log_num_strides %u, um= r_mode %d\n", - log_wqe_stride_size, log_wqe_num_of_strides, - umr_mode); - return -EINVAL; - } - - MLX5_SET(wq, wq, log_wqe_num_of_strides, - log_wqe_num_of_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE); - MLX5_SET(wq, wq, log_wqe_stride_size, - log_wqe_stride_size - MLX5_MPWQE_LOG_STRIDE_SZ_BASE); - MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(mdev, params, xs= k)); - if (params->packet_merge.type !=3D MLX5E_PACKET_MERGE_SHAMPO) - break; - - MLX5_SET(wq, wq, shampo_enable, true); - MLX5_SET(wq, wq, log_reservation_size, - MLX5E_SHAMPO_WQ_LOG_RESRV_SIZE - - MLX5E_SHAMPO_WQ_RESRV_SIZE_BASE_SHIFT); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Richard Cochran , , , , , Gal Pressman , Dragos Tatulea , Cosmin Ratiu , Pavel Begunkov , David Wei Subject: [PATCH net-next 03/15] net/mlx5e: Extract max_xsk_wqebbs into its own function Date: Mon, 23 Feb 2026 22:41:43 +0200 Message-ID: <20260223204155.1783580-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260223204155.1783580-1-tariqt@nvidia.com> References: <20260223204155.1783580-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC9:EE_|LV9PR12MB9805:EE_ X-MS-Office365-Filtering-Correlation-Id: 29593076-ac45-40d3-e197-08de731c2977 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|7416014|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Yr1bM2JKXHYooYVIxqpBGg2DYbMrUFrMHmXmnzPajnDfTPufDhgrwiPBT2Ye?= =?us-ascii?Q?O48G65iJy4tYN8hXu7iPaj2WUDvepsbZYEP9xFO+uDxXxDPof/kw1Bs7gTVb?= =?us-ascii?Q?h6n8r5wF4FRenZc2SINkM6mcG2J9rlK8ex1gNj3j1VPl5WhGlrxIJgpPzfFa?= =?us-ascii?Q?0lmUgFy0hjL+nBgTCft6mYxkMwdBeRFp1kke1yNzN/04Nf14UA+Y1qmYiyhp?= =?us-ascii?Q?vs0QUJET4m3EIfdfKpuJN3E+aYKTvIBlFWl2zdcgCMR5wHyjfQZV6Shpw0RD?= =?us-ascii?Q?FLsg/e4r18XvHhMOJqZcSnJDvyfD5YeEvCn0ln/qYojuuaBvIxe0V2q4m2o5?= =?us-ascii?Q?D1In5FZobk05nBN1kWncfOnvPGLXyXo8+9Qlg3EGIdYNMMr1LxMJQnrvhhXe?= =?us-ascii?Q?NIJ1bZy0eXZXgMpM43RGDDYCf0rwqkzilsFP4CjLt3QGR07IKZ+vSF9fbOEN?= =?us-ascii?Q?tsMFCbyoKu/fyV0dJT3IPcbZhwelD/oEceHBSgJrhQTF5cjYG9ULxNh6zpTl?= =?us-ascii?Q?Kiz8L2jUBEhsFKm+lQuNqS1c1U1dSM5fRmFBE04gcQj2aJSfdP6wrvhBw5Qo?= =?us-ascii?Q?qVe+SOgoEZI1LWyQRqs30omJWPcjSRZWm9kET6uWQscpmF5qkJMqRxkz8Xl4?= =?us-ascii?Q?OJGiAhsOwhxPMh1d/kBzw/ug6N9wUj05IWRlesw8DI6WGdY6MPOh7y5bZh5Z?= =?us-ascii?Q?/ucJwfSz/STJsN7H6bVq5OldUBwEOVGC+SLYyNOQlQOUkG8GqK/MtCBL0nzt?= =?us-ascii?Q?DVhOB3r3LVTu51WROKQohPtAmzZD/wrby07j90/IEehlWAbDqR3DiK1SN8Hw?= =?us-ascii?Q?G0Oz4I33A6EZT0g3Get8YpZjBozjW3EigwWrEMzRXNcW+1yeglilRGxGwdAN?= =?us-ascii?Q?1asOqipnyMApVl+ZU/uyIaHmswKoeQLF1difL/dRboVTxQ4TYDr3cIRgFCwy?= =?us-ascii?Q?HALrlb6OR513wT2P0cG1LJc3TdaRgdQ4QssZETJawZACfKmLZ3engKoW2McA?= =?us-ascii?Q?AFpbIhnSQ+t04gP7ikQu2Uf72XenEAbAcIi69McYPjoZMcNIktRJ0Ry5VAdo?= =?us-ascii?Q?3hCWM1Lxu0qcVvYN6+IQArwMcunY9nEheyZ7lJoq8b7AgphMq6F96abdU2ot?= =?us-ascii?Q?7yeIoFYELX6loCuU76wnCBJJlBPGo/CMFbIHf3g8lvO9Xfoc1zr/4+dWc7OE?= =?us-ascii?Q?fii82sRsP7vtaAyrcaGy+zUWkkKTziApHB/0LKLPJDCbLTsrt198x4qMEy4k?= =?us-ascii?Q?KXCCMwTZVB8JmFBfYdK+wH/DbFrHvCtZLR1FGR1Ou4hHq9ui+1UEE11kgabM?= =?us-ascii?Q?vEU3PcDoMqUMMyzeVonk4X3u6J5NRDYPP1geO9tVXvBxg6+cEznRxA47l/fb?= =?us-ascii?Q?IQy4TIK4dxIZnjrj+P0QhyRVAfKlXFotUC2H0B8EzexvlyMFXrBTCzSBBtrd?= =?us-ascii?Q?rq3GP4FE+HtG9QtiytEuoWHAuU3DCGca6JCBVP7M/ioCcagBsI9nfixaYkFj?= =?us-ascii?Q?GHEHUdUlZIBYZzH0/sLdknH0/wqf0vsv9JoDsThrhTazZFVbRLn8LvBZK5BM?= =?us-ascii?Q?9UH/oZZ1Os8FIec/rP95t3RjqohqXlxq2wcHKxA1uTEO6Q6pt7i32DuiUMBp?= =?us-ascii?Q?6DKtj/uLl0UaAltlg5fHticIkTS5bVGZpMOjchUZHoc0BYgm/wF4LUG0c/iD?= =?us-ascii?Q?kM618w=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(7416014)(376014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: CJlBvzHTuJi0UlHm0TWeRjyI8sB1jTDUJlFJQ9MehICrpi2GLqm/8+b2ZGFgbCiMpB5aBUY9wDRYFJv4PL8VhUYJDe0dRTxESMBouEDi4SzYU0zsolcMeioXDdlYKYOp/zidogWWSItFZEMTBwp62pBm2Pn/jM+dn9U4JrbjU5YqOc/XEZeswT/rmYPw9dHNJwZGX66HFbq5ylxwWEUqCCZRImiD+1nGzQRDvBLH3haOjZ5PbrKEErqeDqqOT9se2xK23v9PfY91ud/Pa2Yn3aOjd64SWMFGhrMtntYaD9/jGa5gV9IpN+ug56faO9uslZPYVJFY+PlS3Y3f5JFc7aeGAyTr3rTeVuj3oM4bosb7W4l1W0tAbi/hiIGw/Wm+Hlq63SAwL5YjTHa9j5FI2MJe/x+4FisInYfD/aWBaqNADiZrh7jqNvRQd0BXuN+e X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Feb 2026 20:43:12.3888 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 29593076-ac45-40d3-e197-08de731c2977 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC9.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV9PR12MB9805 Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea Calculating max_xsk_wqebbs seems large enough to deserve its own function. It will make upcoming changes easier. This patch has no functional changes. Signed-off-by: Dragos Tatulea Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/en/params.c | 94 ++++++++++--------- 1 file changed, 52 insertions(+), 42 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c b/drivers/= net/ethernet/mellanox/mlx5/core/en/params.c index 07d75a85ee7f..be1aa37531de 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c @@ -1116,18 +1116,15 @@ static u32 mlx5e_mpwrq_total_umr_wqebbs(struct mlx5= _core_dev *mdev, return umr_wqebbs * (1 << mlx5e_mpwqe_get_log_rq_size(mdev, params, xsk)); } =20 -static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5_core_dev *mdev, - struct mlx5e_params *params, - struct mlx5e_rq_param *rq_param) +static u32 mlx5e_max_xsk_wqebbs(struct mlx5_core_dev *mdev, + struct mlx5e_params *params) { - u32 wqebbs, total_pages, useful_space; - - /* MLX5_WQ_TYPE_CYCLIC */ - if (params->rq_wq_type !=3D MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) - return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE; + struct mlx5e_xsk_param xsk =3D {0}; + u32 max_xsk_wqebbs =3D 0; + u8 frame_shift; =20 - /* UMR WQEs for the regular RQ. */ - wqebbs =3D mlx5e_mpwrq_total_umr_wqebbs(mdev, params, NULL); + if (!params->xdp_prog) + return 0; =20 /* If XDP program is attached, XSK may be turned on at any time without * restarting the channel. ICOSQ must be big enough to fit UMR WQEs of @@ -1139,41 +1136,54 @@ static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5_c= ore_dev *mdev, * from capabilities. Hence, we have to try all valid values of XSK * frame size (and page_shift) to find the maximum. */ - if (params->xdp_prog) { - u32 max_xsk_wqebbs =3D 0; - u8 frame_shift; - - for (frame_shift =3D XDP_UMEM_MIN_CHUNK_SHIFT; - frame_shift <=3D PAGE_SHIFT; frame_shift++) { - /* The headroom doesn't affect the calculation. */ - struct mlx5e_xsk_param xsk =3D { - .chunk_size =3D 1 << frame_shift, - .unaligned =3D false, - }; - - /* XSK aligned mode. */ - max_xsk_wqebbs =3D max(max_xsk_wqebbs, - mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &xsk)); - - /* XSK unaligned mode, frame size is a power of two. */ - xsk.unaligned =3D true; - max_xsk_wqebbs =3D max(max_xsk_wqebbs, - mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &xsk)); - - /* XSK unaligned mode, frame size is not equal to stride size. */ - xsk.chunk_size -=3D 1; - max_xsk_wqebbs =3D max(max_xsk_wqebbs, - mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &xsk)); - - /* XSK unaligned mode, frame size is a triple power of two. */ - xsk.chunk_size =3D (1 << frame_shift) / 4 * 3; - max_xsk_wqebbs =3D max(max_xsk_wqebbs, - mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &xsk)); - } + for (frame_shift =3D XDP_UMEM_MIN_CHUNK_SHIFT; + frame_shift <=3D PAGE_SHIFT; frame_shift++) { + u32 total_wqebbs; =20 - wqebbs +=3D max_xsk_wqebbs; + /* The headroom doesn't affect the calculations below. */ + + /* XSK aligned mode. */ + xsk.chunk_size =3D 1 << frame_shift; + xsk.unaligned =3D false; + total_wqebbs =3D mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &xsk); + max_xsk_wqebbs =3D max(max_xsk_wqebbs, total_wqebbs); + + /* XSK unaligned mode, frame size is a power of two. */ + xsk.unaligned =3D true; + total_wqebbs =3D mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &xsk); + max_xsk_wqebbs =3D max(max_xsk_wqebbs, total_wqebbs); + + /* XSK unaligned mode, frame size is not equal to stride + * size. + */ + xsk.chunk_size -=3D 1; + total_wqebbs =3D mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &xsk); + max_xsk_wqebbs =3D max(max_xsk_wqebbs, total_wqebbs); + + /* XSK unaligned mode, frame size is a triple power of two. */ + xsk.chunk_size =3D (1 << frame_shift) / 4 * 3; + total_wqebbs =3D mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &xsk); + max_xsk_wqebbs =3D max(max_xsk_wqebbs, total_wqebbs); } =20 + return max_xsk_wqebbs; +} + +static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5_core_dev *mdev, + struct mlx5e_params *params, + struct mlx5e_rq_param *rq_param) +{ + u32 wqebbs, total_pages, useful_space; + + /* MLX5_WQ_TYPE_CYCLIC */ + if (params->rq_wq_type !=3D MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) + return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE; + + /* UMR WQEs for the regular RQ. */ + wqebbs =3D mlx5e_mpwrq_total_umr_wqebbs(mdev, params, NULL); + + wqebbs +=3D mlx5e_max_xsk_wqebbs(mdev, params); + /* UMR WQEs don't cross the page boundary, they are padded with NOPs. * This padding is always smaller than the max WQE size. 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Mon, 23 Feb 2026 12:42:58 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Richard Cochran , , , , , Gal Pressman , Dragos Tatulea , Cosmin Ratiu , Pavel Begunkov , David Wei Subject: [PATCH net-next 04/15] net/mlx5e: Expose and rename xsk channel parameter function Date: Mon, 23 Feb 2026 22:41:44 +0200 Message-ID: <20260223204155.1783580-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260223204155.1783580-1-tariqt@nvidia.com> References: <20260223204155.1783580-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001505:EE_|SN7PR12MB8104:EE_ X-MS-Office365-Filtering-Correlation-Id: 98e5a312-7409-4012-0d33-08de731c2ebd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|7416014|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Cmus7hIuNv0VY5Vw+AMZ7OH05Gy2ogP14ymsokI5W5dELLE0A3bkbTDNOC7C?= =?us-ascii?Q?nipQ6myiat5GMhim2E8a8HZJy6sCM3cjsI8SZD1WCSc+txcjIOBRnD0ggILf?= =?us-ascii?Q?toHmCQ9MR/XKoJ+SbR6vfOX+ykJLwKSraFV2064EqJVV2VIReehQuhix2m5Y?= =?us-ascii?Q?hToh+yY5ZuJFumri2mf4np4zmnPCQ1rBSV1eR6xqQF4ncDC8cZf0A/BLHWky?= =?us-ascii?Q?DwiDoU/A35eHKsG/T6KYcDS5SZkkWX3Hi93YZ/Rcbt2OddPUqR9dsC/G5ZNa?= =?us-ascii?Q?8bwH4wL5sAM/fRwdzFflAgvh7DaSJHdvKPSBGsZkHsyxvgvC8Ohi1Ah7nFfd?= =?us-ascii?Q?iA4uVH8dUfecvKAqnIAMLRw6p+3zZVhekMQKHD53DIfCv0ekq6yPmyjAYV7N?= =?us-ascii?Q?O0jhQeq+HkRYU+qjyPQk+mQWm3/h3jeFWfS8A/chXhFnnBdzzzorasMZhcjF?= =?us-ascii?Q?p1CZpd2XdgWb3TvnqObxLNPglQ2kedDjbmY6SPvHgipYwZYQ4a0Q+MkXGs6P?= =?us-ascii?Q?TrYsFQqK1pUOOXt7/wraUo0WfcJLwgjFRZtrTjOzYBGgqPr+qmvp6Z+jJbhp?= =?us-ascii?Q?5dkvy5uf2WdKvz27df/f8/q4dON20z+pDL2wKsLtcj0mis5hDXLAD0nJGSqf?= =?us-ascii?Q?KXkZIxs0juUSv3s1DGOQWTCrmP3p3wwNlpj9k7jbEi0lBAZgU0ozyxTGHxs6?= =?us-ascii?Q?clBq1+m4LeGI8v5+oxohdyFbZygVSR8NdEZMb38bIHjeDR2aZFGutDae1HIG?= =?us-ascii?Q?Kze9lpUl4stPnCBOGFYgbXwB4y4sHjroiFkgNNHTqCrjgUaAtQHUGrCT8KRe?= =?us-ascii?Q?jwbxMRrzGMzi2vd9lNReU/b2RS8Fkk6K0UYfLWz1f7gWJEQSJ2mDwTMtar0L?= =?us-ascii?Q?jsqLi3x2psib2KiSgK/aKdr/5KLcE33TeOHG7BNLITWBjmlp0nA44uFSgCCH?= =?us-ascii?Q?cxYRsLGbe4joVc7iIulNXoNUcdBkJfxlElE0ESTXVemD5O0BVuoibcWmFiKA?= =?us-ascii?Q?+hUZwI1tK+DCbOKrwxRGSqMHnJ3Od2/bhhn9v29gO3U26rrlRRGLFQHvxL4z?= =?us-ascii?Q?EqytjNViCPxw/TtaBf/B8XLEXSZJDF41LeisLNcIY3ujSm1TkVaTgh59jj0/?= =?us-ascii?Q?+6WcUQrzt79YGZ2bt8JH7LBp6toB15eCJSPAxwSj5KQfjV/dk37LmD2KDJA0?= =?us-ascii?Q?LEVag1TB0HArgUn+v/x/6EppvFuhdwzqMflYwjipS6EqUi+1MJTSTjt8qPJr?= =?us-ascii?Q?LIAr7QAdCKbGm1Gko1nurF9rBM+GEiPulN6SuC4srKLZoPGgLjuQL5Eolln+?= =?us-ascii?Q?mN0y09t1WbvHsQuVAuPZpGYy6ty8JaJCLVj/PfBAP8UQRm0kCOXQpEenfOTR?= =?us-ascii?Q?BgPIgCUeg3PjE2czeXFfDHnJtb9OQlxSQgjVsDpQdsFOTuTLjP3yzIbs360H?= =?us-ascii?Q?rcFXtQjW1n1JRdj/hYM1p71vK4ua4lFGtnKAqzQSooX6uvFlq3DBosQMG38Y?= =?us-ascii?Q?P4R55TctkPG1mbBK6IYbg04xCUKdc0HbjMxx+P4+I+tZS+PsLnXZarqmqdDn?= =?us-ascii?Q?AIWGdy38ATETQD/TM/a0tkPpreVkzBJ9JN74eMfbV725DMXiqcghDHrRDVZM?= =?us-ascii?Q?MngqNZ19Cp2xVSt4h9NfRbMWKPx48m7FYgTfHYhe1yPSJwGmEadd9anOrbc8?= =?us-ascii?Q?rmhACg=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(7416014)(376014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Cxd8Eyt0pVEB5eu6qSBGqoWwZLjZI7i/tGZq4xR+ituPTFzpYmQk7rY/4IybQCYzE9WQIV8tMr1TIopyFh66/Ich6XlSmDgHrgjetTaIxBETJn2sS+hnGm48JuVt807xXAO6fkkrvz1B2IYy7RZ6dLBs8BBkvA34hxPioYrX7dJoEYVL5SLfwgxeD01WNuIFvTk8FYZxMds+oRzLpdyF5MY/sH4HhLYsS2SKw63Ww+IQDC1eyNREyn+ZLdj+8XAYHIgt1fgtbdCsMvpMdDY00XhoqbNUJcJksLLdnHbzm6r7mkB/3YccyGj+MuQD3tdbrG6G5MtktkpQ6cUeOK1JucG9/uEvNX9sl0tU+ZfErbiLa75X5uaptqM50hVlxKQuHFH1JSK1VnQTX6UmPbPI5YgxOPqUcEGO+r3TGBDu6vhgUM5rxks819goHeNkIJfe X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Feb 2026 20:43:21.2256 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 98e5a312-7409-4012-0d33-08de731c2ebd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001505.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8104 Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea mlx5e_build_xsk_cparam() is meant to be the alternative to mlx5e_build_channel_param(). It calculates only the parameters that it requires using the previously configured mlx5e_xsk_param. Move this function to params.c to be alongside mlx5e_build_channel_param() and give it a similar name. Expose the function as it will be needed by upcoming changes. This patch has no functional changes. Signed-off-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en/params.c | 9 +++++++++ drivers/net/ethernet/mellanox/mlx5/core/en/params.h | 5 +++++ .../net/ethernet/mellanox/mlx5/core/en/xsk/setup.c | 11 +---------- 3 files changed, 15 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c b/drivers/= net/ethernet/mellanox/mlx5/core/en/params.c index be1aa37531de..4d51fad7d9eb 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c @@ -1272,3 +1272,12 @@ int mlx5e_build_channel_param(struct mlx5_core_dev *= mdev, =20 return 0; } + +void mlx5e_build_xsk_channel_param(struct mlx5_core_dev *mdev, + struct mlx5e_params *params, + struct mlx5e_xsk_param *xsk, + struct mlx5e_channel_param *cparam) +{ + mlx5e_build_rq_param(mdev, params, xsk, &cparam->rq); + mlx5e_build_xdpsq_param(mdev, params, &cparam->xdp_sq); +} diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.h b/drivers/= net/ethernet/mellanox/mlx5/core/en/params.h index 00617c65fe3c..26680985ee39 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.h @@ -138,6 +138,11 @@ int mlx5e_build_channel_param(struct mlx5_core_dev *md= ev, struct mlx5e_params *params, struct mlx5e_channel_param *cparam); =20 +void mlx5e_build_xsk_channel_param(struct mlx5_core_dev *mdev, + struct mlx5e_params *params, + struct mlx5e_xsk_param *xsk, + struct mlx5e_channel_param *cparam); + u16 mlx5e_calc_sq_stop_room(struct mlx5_core_dev *mdev, struct mlx5e_param= s *params); int mlx5e_validate_params(struct mlx5_core_dev *mdev, struct mlx5e_params = *params); bool mlx5e_verify_params_rx_mpwqe_strides(struct mlx5_core_dev *mdev, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c b/drive= rs/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c index 50c14ad29ed6..e3b7e79863ae 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c @@ -48,15 +48,6 @@ bool mlx5e_validate_xsk_param(struct mlx5e_params *param= s, } } =20 -static void mlx5e_build_xsk_cparam(struct mlx5_core_dev *mdev, - struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk, - struct mlx5e_channel_param *cparam) -{ - mlx5e_build_rq_param(mdev, params, xsk, &cparam->rq); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Richard Cochran , , , , , Gal Pressman , Dragos Tatulea , Cosmin Ratiu , Pavel Begunkov , David Wei Subject: [PATCH net-next 05/15] net/mlx5e: Alloc xsk channel param out of mlx5e_open_xsk() Date: Mon, 23 Feb 2026 22:41:45 +0200 Message-ID: <20260223204155.1783580-6-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260223204155.1783580-1-tariqt@nvidia.com> References: <20260223204155.1783580-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001509:EE_|CH3PR12MB8901:EE_ X-MS-Office365-Filtering-Correlation-Id: b8107a6d-02aa-4285-86e9-08de731c333a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700013|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?bHH+6207j8Xo8MAJ0wK8hTmaYk+fTrlQ+8kTqcCW36wuGyJzGFCe8T2HJP02?= =?us-ascii?Q?eulgYBLxfSyfBW4TO+Xfwto4pqTpHL4U5BE8wpcKWQQwtkBcVVk9CQ4RA+W4?= =?us-ascii?Q?GCAzPl60jdMdmPGzLj+USlwnbK+G34p07XCcI2mtZTippQO/wc4X3vM+k1/J?= =?us-ascii?Q?3I7qL42WZRh94HVMfFM7exd5rHCQi8E85Cgz8jaBytsdVms5OD+sIZ2l831N?= =?us-ascii?Q?Mwp8Z3GBn+tv51FrYyoH6sHn8hs0xYCF3SVG/pf+m+2kEkW5Us5XshYmS+MM?= =?us-ascii?Q?/NtpwTQx/8DzVK4weQmoXVa+wYqcGWyMHv3OVEc4eEfZF9DqdOA5JOozwVw3?= =?us-ascii?Q?x6riNmm58PAsMOhWTvGJGBbrr7JTBxq/ly1LtghpFFfyI170doLvs0UrHGuW?= =?us-ascii?Q?F/JHQn7HA2ovR4xPcmqXVORZd/+SdJqHH8JbQbF7IYAFTHk/6R0JuU7Rd6cE?= =?us-ascii?Q?yq9oEAeLgvoeanaaz9o3cgrUCraWGm3bK1SskIpBAashUtUUqcGtVetMnfdk?= =?us-ascii?Q?k6WgfKoPUSJ3OrWriblvVR5efIXX6xMvtm1J2tSpUl7Uz/iKZYcC9s8vn/Fo?= =?us-ascii?Q?EUzrvuJygEhHQ7XPedbN+7V1gb/Dvtb9mTm0wElpgT097PUHbLKGNL9QiOM9?= =?us-ascii?Q?iJ88M9plF7Mcjv5ZzdLDLqoNLFsu6tc8Q3PJ7QIkP9LGAlA+swdLlRPkyD6n?= =?us-ascii?Q?LN+0f8bcvkd5c1IPIYn2zAMYivEK7pG/N1O8Y1iUDDBDXEFpXuA8ly9R7j+0?= =?us-ascii?Q?JQ3+NdD2+jYPvJuXwSXofIHdW0yZHln9uKLkNZqu680SMe81zICmgw1WCVtT?= =?us-ascii?Q?xLNa+OyIT1y6O1aBfl+Pc86HuaACW0hHoxYkC3FZbI4PB/NtFRWGirWuSOZ2?= =?us-ascii?Q?gspwZnRWrLyaWgsR9WCaUwaqj912hAqvlmDdGvZRiHNBsK/piv0vXnAuKiam?= =?us-ascii?Q?7/CbvGt5HZ+lPfKyrNkbcxKoD8Lb5ha0CF42HueK/ZbkKBmGBlNH0xPuuazB?= =?us-ascii?Q?MgtvZ6ntd7pxIvQMVYirm/Ix+M8aegam3i4BMjHirntZlESKRqF4xOIHtl7F?= =?us-ascii?Q?0k5/Ijd9FmUh0HJyeHjDdYFui/M5NSMeg2YZySq/7KjO2loT6S2TJ+l8w4QO?= =?us-ascii?Q?+KZKG0+6NQSSDegrZbkc8zqTeWmxKqhJ8yLbpaycIUzlJymXkNGVpcakt+Qu?= =?us-ascii?Q?fa/mvs3cnjuyByEwf4e6qsz77IzwaGLT4wvb1KtKDjlONVJdZsp8SFj9lOot?= =?us-ascii?Q?ImNUdtPQu6iVeVuTDCE8K1wo6lR2cJMEZIp6CIJeGVirWipVNFpqiQJgh3Vp?= =?us-ascii?Q?JR4mNiY84WG5yq+eDtrvaW0FUUO6ezBPCFJKS8mgabLnTqQ7U+4l+4laQgn3?= =?us-ascii?Q?eTZPfk2YcE54Q9FS6zNt5MgZChuUmnJJPXVNvQpwfHKGSggFPy9bjQteUKje?= =?us-ascii?Q?oodL7ySs0CioBCBodrBWOHDJCOBs07hlPCe2NJodz2NEicXpHKozoB/ulo/L?= =?us-ascii?Q?eEmk1M6lsLguIIoIi4kT3fnrq7fmgnm34Bw15RfZ749jjMu4MDPdX5lGKpiK?= =?us-ascii?Q?uHb50ecCpTlQaJ2nvtAaipozwBQuqL8NoFo+YLbNRluqleF6TznGR+ifbOuM?= =?us-ascii?Q?rgayJvbPsem1epqtAh0ObTbMuwn5qGHsJOJvE0a07a9aFyADoyxhtg5YfdNe?= =?us-ascii?Q?EdVbxQ=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(36860700013)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: AvwvlpNvdWizVqZRLn4CnRvB4nvTkT21jtjQDuhlIW3eK9oHI9YGo0s100QeYBkTCTkOV5KDf6DevPDFPT+hg9XHxr/Nr4JfzGgRYs9Doy9LmrHQtLGeduQ/5/73tjyoMeGq1uEqYUqLk1MlPLItYM31Hdr8SAYTlNWeEj7pC64MSXNI+n6+hI2sv+c0Mm4haCEwj1b1qf6virh50PrAe6YjNAUCn/FFjI26jXnrSCDVjEcPdB10OpbdFpbG3wlQsOqsH9r/hWwrCK9h/ubbdO0nA8FiQnWmWZXjeP5oSbAJ9vXIMQMAV6nKjyC7lk3yBcIHgdeHNXe8/eo8cJExtUMxSR0Buqc92S/jQCvXQL2XeqVzu9iLzq5XdavQDLaSuWWnAAQYF7dbc2i+ForV08T0stj/OkXw9faK7EM/X2mVM81LC6A8DczQBxYw3JKi X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Feb 2026 20:43:28.7511 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b8107a6d-02aa-4285-86e9-08de731c333a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001509.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8901 Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea Currently the allocation and filling of the xsk channel parameters was done in mlx5e_open_xsk(). Move this responsibility out of mlx5e_open_xsk() and have the function take an already filled mlx5e_channel_param. mlx5e_open_channel() already allocates channel parameters. The only precaution that is needed is to call mlx5e_build_xsk_channel_param() before mlx5e_open_xsk(). mlx5e_xsk_enable_locked() now allocates and fills the xsk parameters. For simplicity, link the xsk parameters in struct mlx5e_channel_params so that channel params can be passed around. This patch has no functional changes. Signed-off-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/en/params.c | 1 + .../ethernet/mellanox/mlx5/core/en/params.h | 1 + .../ethernet/mellanox/mlx5/core/en/xsk/pool.c | 17 +++++++++++++++-- .../ethernet/mellanox/mlx5/core/en/xsk/setup.c | 18 ++++-------------- .../ethernet/mellanox/mlx5/core/en/xsk/setup.h | 4 +++- .../net/ethernet/mellanox/mlx5/core/en_main.c | 3 ++- 6 files changed, 26 insertions(+), 18 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c b/drivers/= net/ethernet/mellanox/mlx5/core/en/params.c index 4d51fad7d9eb..ef88097c1d4d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c @@ -1278,6 +1278,7 @@ void mlx5e_build_xsk_channel_param(struct mlx5_core_d= ev *mdev, struct mlx5e_xsk_param *xsk, struct mlx5e_channel_param *cparam) { + cparam->xsk =3D xsk; mlx5e_build_rq_param(mdev, params, xsk, &cparam->rq); mlx5e_build_xdpsq_param(mdev, params, &cparam->xdp_sq); } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.h b/drivers/= net/ethernet/mellanox/mlx5/core/en/params.h index 26680985ee39..c132649dd9f2 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.h @@ -42,6 +42,7 @@ struct mlx5e_channel_param { struct mlx5e_sq_param xdp_sq; struct mlx5e_sq_param icosq; struct mlx5e_sq_param async_icosq; + struct mlx5e_xsk_param *xsk; }; =20 struct mlx5e_create_sq_param { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/pool.c b/driver= s/net/ethernet/mellanox/mlx5/core/en/xsk/pool.c index 5c5360a25c64..92bcf16a2019 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/pool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/pool.c @@ -79,6 +79,7 @@ static int mlx5e_xsk_enable_locked(struct mlx5e_priv *pri= v, struct xsk_buff_pool *pool, u16 ix) { struct mlx5e_params *params =3D &priv->channels.params; + struct mlx5e_channel_param *cparam; struct mlx5e_xsk_param xsk; struct mlx5e_channel *c; int err; @@ -89,15 +90,20 @@ static int mlx5e_xsk_enable_locked(struct mlx5e_priv *p= riv, if (unlikely(!mlx5e_xsk_is_pool_sane(pool))) return -EINVAL; =20 + cparam =3D kvzalloc_obj(*cparam, GFP_KERNEL); + if (!cparam) + return -ENOMEM; + err =3D mlx5e_xsk_map_pool(mlx5_sd_ch_ix_get_dev(priv->mdev, ix), pool); if (unlikely(err)) - return err; + goto err_free_cparam; =20 err =3D mlx5e_xsk_add_pool(&priv->xsk, pool, ix); if (unlikely(err)) goto err_unmap_pool; =20 mlx5e_build_xsk_param(pool, &xsk); + mlx5e_build_xsk_channel_param(priv->mdev, params, &xsk, cparam); =20 if (priv->channels.params.rq_wq_type =3D=3D MLX5_WQ_TYPE_LINKED_LIST_STRI= DING_RQ && mlx5e_mpwrq_umr_mode(priv->mdev, &xsk) =3D=3D MLX5E_MPWRQ_UMR_MODE_OV= ERSIZED) { @@ -122,7 +128,7 @@ static int mlx5e_xsk_enable_locked(struct mlx5e_priv *p= riv, =20 c =3D priv->channels.c[ix]; =20 - err =3D mlx5e_open_xsk(priv, params, &xsk, pool, c); + err =3D mlx5e_open_xsk(priv, params, cparam, pool, c); if (unlikely(err)) goto err_remove_pool; =20 @@ -138,6 +144,8 @@ static int mlx5e_xsk_enable_locked(struct mlx5e_priv *p= riv, mlx5e_deactivate_rq(&c->rq); mlx5e_flush_rq(&c->rq, MLX5_RQC_STATE_RDY); =20 + kvfree(cparam); + return 0; =20 err_remove_pool: @@ -146,6 +154,9 @@ static int mlx5e_xsk_enable_locked(struct mlx5e_priv *p= riv, err_unmap_pool: mlx5e_xsk_unmap_pool(priv, pool); =20 +err_free_cparam: + kvfree(cparam); + return err; =20 validate_closed: @@ -157,6 +168,8 @@ static int mlx5e_xsk_enable_locked(struct mlx5e_priv *p= riv, goto err_remove_pool; } =20 + kvfree(cparam); + return 0; } =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c b/drive= rs/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c index e3b7e79863ae..03f1be361701 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c @@ -105,10 +105,11 @@ static int mlx5e_open_xsk_rq(struct mlx5e_channel *c, } =20 int mlx5e_open_xsk(struct mlx5e_priv *priv, struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk, struct xsk_buff_pool *pool, + struct mlx5e_channel_param *cparam, + struct xsk_buff_pool *pool, struct mlx5e_channel *c) { - struct mlx5e_channel_param *cparam; + struct mlx5e_xsk_param *xsk =3D cparam->xsk; struct mlx5e_create_cq_param ccp; int err; =20 @@ -117,16 +118,10 @@ int mlx5e_open_xsk(struct mlx5e_priv *priv, struct ml= x5e_params *params, if (!mlx5e_validate_xsk_param(params, xsk, priv->mdev)) return -EINVAL; =20 - cparam =3D kvzalloc(sizeof(*cparam), GFP_KERNEL); - if (!cparam) - return -ENOMEM; - - mlx5e_build_xsk_channel_param(priv->mdev, params, xsk, cparam); - err =3D mlx5e_open_cq(c->mdev, params->rx_cq_moderation, &cparam->rq.cqp,= &ccp, &c->xskrq.cq); if (unlikely(err)) - goto err_free_cparam; + return err; =20 err =3D mlx5e_open_xsk_rq(c, params, &cparam->rq, pool, xsk); if (unlikely(err)) @@ -147,8 +142,6 @@ int mlx5e_open_xsk(struct mlx5e_priv *priv, struct mlx5= e_params *params, if (unlikely(err)) goto err_close_tx_cq; =20 - kvfree(cparam); - set_bit(MLX5E_CHANNEL_STATE_XSK, c->state); =20 return 0; @@ -162,9 +155,6 @@ int mlx5e_open_xsk(struct mlx5e_priv *priv, struct mlx5= e_params *params, err_close_rx_cq: mlx5e_close_cq(&c->xskrq.cq); =20 -err_free_cparam: - kvfree(cparam); - return err; } =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.h b/drive= rs/net/ethernet/mellanox/mlx5/core/en/xsk/setup.h index 50e111b85efd..fc86d19ea2b3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.h @@ -11,8 +11,10 @@ struct mlx5e_xsk_param; bool mlx5e_validate_xsk_param(struct mlx5e_params *params, struct mlx5e_xsk_param *xsk, struct mlx5_core_dev *mdev); +struct mlx5e_channel_param; int mlx5e_open_xsk(struct mlx5e_priv *priv, struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk, struct xsk_buff_pool *pool, + struct mlx5e_channel_param *cparam, + struct xsk_buff_pool *pool, struct mlx5e_channel *c); void mlx5e_close_xsk(struct mlx5e_channel *c); void mlx5e_activate_xsk(struct mlx5e_channel *c); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index f2ce24cf56ce..35b767105492 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -2829,7 +2829,8 @@ static int mlx5e_open_channel(struct mlx5e_priv *priv= , int ix, =20 if (xsk_pool) { mlx5e_build_xsk_param(xsk_pool, &xsk); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Richard Cochran , , , , , Gal Pressman , Dragos Tatulea , Cosmin Ratiu , Pavel Begunkov , David Wei Subject: [PATCH net-next 06/15] net/mlx5e: Move xsk param into new option container struct Date: Mon, 23 Feb 2026 22:41:46 +0200 Message-ID: <20260223204155.1783580-7-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260223204155.1783580-1-tariqt@nvidia.com> References: <20260223204155.1783580-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000205:EE_|DS0PR12MB6462:EE_ X-MS-Office365-Filtering-Correlation-Id: 538353c6-e85a-4529-ff4d-08de731c32de X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|7416014|376014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?9iIpFlzEOSrCUUSegn/+f4rjct0pwSu/ORNSE407aC18c/ol3Z91ZvC/8NWm?= =?us-ascii?Q?7fUpGzz53YhLDyJtdTnnCCRbEF74e5GbtykRvgCiLnEPaJSYsLSSSLLpSvCw?= =?us-ascii?Q?nx2qJqrYPp55w7tWSxPO2ozbcTmCe73JTX/7pFAN69ka53yEZOPFKA1zo9VM?= =?us-ascii?Q?W5rrHYtHCVl5PuMCPqCGzIfNsJI060RzhqDeHTjHEO+vY88PXC0ZsRQvYtYx?= =?us-ascii?Q?BaxGc4W17ggwUj1dM/upEDB7yWg5GcG4bLdUGfhLVLhvHYzkBx32GuZJjwnw?= =?us-ascii?Q?Eexc4oQURUmYd7sMYg801NnWguTxqeq85Lm+d4zEX7bXsVoQYucMqbFxu5GQ?= =?us-ascii?Q?d6hVikwN9hYJ/I3QV95mp8kR6KKluHM7MwXy11g37qJe+G7YsWDWBOLD2coT?= =?us-ascii?Q?X+3xZYLClitJt59R9VDdNLRsBNDrgr/MZ4H42i2j+/Shtlgj6FF3/jSaxuLJ?= =?us-ascii?Q?oJNhLLkstwkPeucQZgDKBNPvHJcmbNrDyzykZd+17sNob2V31dIHXR0l2uJF?= =?us-ascii?Q?J/tEMDNSQp2OQEjhSxnuw14DWR338ZNs0/DhUsNCetJomyxMbjlBFM5SRl3s?= =?us-ascii?Q?NMYdTF/QQ59eQv2Mc3BjnJf9HaAYlD8HGCUWNaXmnQZ0L/FVPRluizNMsNiK?= =?us-ascii?Q?0a6k77nv0JmsI+Z2XuohjRacIX44uQdzJWIaRRKSofTq/w82WWsPPq1w6Ji+?= =?us-ascii?Q?GsC4D56CEWWgJBEwCie+wJzWIBehkJ2nL6L2ehlkWM+U3D/TUVjEpwlej05A?= =?us-ascii?Q?dt4fzvGV4Fe9W6ImlSHahOYYvWyYBejxeiRmZRrBydLU9jGCA9YiqSZFvNW9?= =?us-ascii?Q?cyI9XayVRU4Sgp/NqO2lbILmWhphwpn9R/22YqmUPRUxc7xawjF540VUoBG4?= =?us-ascii?Q?I0Z97ROsT4/yM+5OtsSEuMy6TelMGY9hIHegKDEeJcz9nZxDNHpSy7JIU7HA?= =?us-ascii?Q?AQKMr0uUHnAakm8SeCTzdHLmyN4RCqtY2nmo3xRFtiHMZPp+hBv4jQBA9hwI?= =?us-ascii?Q?JbaXBewFVlkTQw0e6mbzwzXxbPOJOoSdiNi1mPkMdpo8rF1a92Gy0duV/VrA?= =?us-ascii?Q?ouk4C4proEBCweoWv2pEdtZ9JgBIGITrgWyfIJlACe2JcxY35DUeC98bURkF?= =?us-ascii?Q?ipXdBnT8Ya7tCL/5QhlN7P+BqD+ufYgDC+jr01MOV0wH5WJUOMMsbMZE2v9e?= =?us-ascii?Q?vd30EqKMnyd/CKcEDFuOXQDRU5TCzYQ5YHEWf+BRyHH6ajM0hVRUdLd8u8nm?= =?us-ascii?Q?+BbM10j88TBnPPLkUTXlC1zlqwD86VTpHBK5iqZH6TPYld4RIP607jj6GFAR?= =?us-ascii?Q?K+Cy30yMt6AAdhk0XFD2iuZVjJB3rcymslssiK5LZLobXjGS14KsY3rC1c1B?= =?us-ascii?Q?YcWheoqYAfua5fZeCHC3MnX3qk2oQnwHOw8YB+uOzThLjGbaDhzQVVkmOGJP?= =?us-ascii?Q?V8Pw3y0x7LzII2AXU4QUlAmOhIROE3BuKgJ7MeSG0U4IJ4YQqmOn5lrogx+P?= =?us-ascii?Q?NX2bYcJCzwpkYvxVkr78jaZLDCh53MT0pk9PJA9dFSqqLIffCAB0WrNJyi6u?= =?us-ascii?Q?ejxsqe6dm3QzaFcEagRQEdibtMNmKVf0J3rFZZ5rNtdag68VAy2Tv8NeX7RE?= =?us-ascii?Q?x65s/1YuDxraRQl5f1oMTNY+aGIhXbYnMqB68Y1vgS5rXN+mNJr9shJoQDTd?= =?us-ascii?Q?ZzDfUw=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(7416014)(376014)(36860700013);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: r/8+nUpkYHu3CGBiMgyqMrQfn+t41lvfIM3E7dMqTdZmtwPQJCxRoe6abc4ohCgkXoRmflOrsya+UqhNGnYrtzHTW8Vqmtlgi/wZfgJIVwyM5eA+Sr6qOEcA3SVDgRVazPnsyCIzAsdkB9FOStYc5wrXlJr7p7hHq8FiC4bL9UMHhWgRQP5n1NkiNLZlydkzwg6PUdiSvDAUrFIVw9KaXUdT0P2Epy9EXN0OudHSdPgUJ/POpRgs8qFvVGKx9HnwrkRipxu+1+fsa7hqp3QMMNbqgDmBzBPTKjqeCjhogRjH+ooLeozUsdg+FMATi3ge3W7b+osofGTesvgL0uLlOXqT2E8VHV+ZYfrmTcMqiM7+K5gVmaQGGO3C/qtrHMi8ApYNMYUKbiwciv1dAVnHXJdfBUJ+Cb78HvBXfapT6hcPjFFeHxWxH2Fd1FGutlPs X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Feb 2026 20:43:28.2569 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 538353c6-e85a-4529-ff4d-08de731c32de X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000205.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6462 Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea The xsk parameter configuration (struct mlx5e_xsk_param) is passed around many places during parameter calculation. It is used to contain channel specific information (as opposed to the global info from struct mlx5e_params). Upcoming changes will need to push similar channel specific rq configuration. Instead of adding one more parameter to all these functions, create a new container structure that has optional rq specific parameters. The xsk parameter will be the first of such kind. The new container struct is itself optional. That means that before checking its members, it has to be checked itself for validity. This patch has no functional changes. Signed-off-by: Dragos Tatulea Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 3 +- .../ethernet/mellanox/mlx5/core/en/params.c | 192 ++++++++++-------- .../ethernet/mellanox/mlx5/core/en/params.h | 38 ++-- .../net/ethernet/mellanox/mlx5/core/en/xdp.c | 5 +- .../net/ethernet/mellanox/mlx5/core/en/xdp.h | 3 +- .../ethernet/mellanox/mlx5/core/en/xsk/pool.c | 6 +- .../mellanox/mlx5/core/en/xsk/setup.c | 31 +-- .../mellanox/mlx5/core/en/xsk/setup.h | 2 +- .../net/ethernet/mellanox/mlx5/core/en_main.c | 33 +-- 9 files changed, 185 insertions(+), 128 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index 550426979627..5181d6ab39ae 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -1060,8 +1060,9 @@ void mlx5e_timestamp_init(struct mlx5e_priv *priv); struct mlx5e_xsk_param; =20 struct mlx5e_rq_param; +struct mlx5e_rq_opt_param; int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *rq_p= aram, - struct mlx5e_xsk_param *xsk, int node, u16 q_counter, + struct mlx5e_rq_opt_param *rqo, int node, u16 q_counter, struct mlx5e_rq *rq); #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */ int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c b/drivers/= net/ethernet/mellanox/mlx5/core/en/params.c index ef88097c1d4d..97f5d1c2adea 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c @@ -21,10 +21,14 @@ static u8 mlx5e_mpwrq_min_page_shift(struct mlx5_core_d= ev *mdev) return min_page_shift ? : 12; } =20 -u8 mlx5e_mpwrq_page_shift(struct mlx5_core_dev *mdev, struct mlx5e_xsk_par= am *xsk) +u8 mlx5e_mpwrq_page_shift(struct mlx5_core_dev *mdev, + struct mlx5e_rq_opt_param *rqo) { - u8 req_page_shift =3D xsk ? order_base_2(xsk->chunk_size) : PAGE_SHIFT; + struct mlx5e_xsk_param *xsk =3D mlx5e_rqo_xsk_param(rqo); u8 min_page_shift =3D mlx5e_mpwrq_min_page_shift(mdev); + u8 req_page_shift; + + req_page_shift =3D xsk ? order_base_2(xsk->chunk_size) : PAGE_SHIFT; =20 /* Regular RQ uses order-0 pages, the NIC must be able to map them. */ if (WARN_ON_ONCE(!xsk && req_page_shift < min_page_shift)) @@ -34,7 +38,8 @@ u8 mlx5e_mpwrq_page_shift(struct mlx5_core_dev *mdev, str= uct mlx5e_xsk_param *xs } =20 enum mlx5e_mpwrq_umr_mode -mlx5e_mpwrq_umr_mode(struct mlx5_core_dev *mdev, struct mlx5e_xsk_param *x= sk) +mlx5e_mpwrq_umr_mode(struct mlx5_core_dev *mdev, + struct mlx5e_rq_opt_param *rqo) { /* Different memory management schemes use different mechanisms to map * user-mode memory. The stricter guarantees we have, the faster @@ -45,7 +50,8 @@ mlx5e_mpwrq_umr_mode(struct mlx5_core_dev *mdev, struct m= lx5e_xsk_param *xsk) * 3. KLM - indirect mapping to another MKey to arbitrary addresses, and * mappings can have different sizes. */ - u8 page_shift =3D mlx5e_mpwrq_page_shift(mdev, xsk); + struct mlx5e_xsk_param *xsk =3D mlx5e_rqo_xsk_param(rqo); + u8 page_shift =3D mlx5e_mpwrq_page_shift(mdev, rqo); bool unaligned =3D xsk ? xsk->unaligned : false; bool oversized =3D false; =20 @@ -225,12 +231,12 @@ u8 mlx5e_mpwrq_max_log_rq_pkts(struct mlx5_core_dev *= mdev, u8 page_shift, } =20 u16 mlx5e_get_linear_rq_headroom(struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk) + struct mlx5e_rq_opt_param *rqo) { u16 headroom; =20 - if (xsk) - return xsk->headroom; + if (mlx5e_rqo_xsk_param(rqo)) + return rqo->xsk->headroom; =20 headroom =3D NET_IP_ALIGN; if (params->xdp_prog) @@ -263,19 +269,23 @@ static u32 mlx5e_rx_get_linear_sz_skb(struct mlx5e_pa= rams *params, bool no_head_ =20 static u32 mlx5e_rx_get_linear_stride_sz(struct mlx5_core_dev *mdev, struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk, + struct mlx5e_rq_opt_param *rqo, bool mpwqe) { + struct mlx5e_xsk_param *xsk =3D mlx5e_rqo_xsk_param(rqo); bool no_head_tail_room; u32 sz; =20 /* XSK frames are mapped as individual pages, because frames may come in * an arbitrary order from random locations in the UMEM. */ - if (xsk) - return mpwqe ? 1 << mlx5e_mpwrq_page_shift(mdev, xsk) : PAGE_SIZE; + if (xsk) { + return mpwqe ? + BIT(mlx5e_mpwrq_page_shift(mdev, rqo)) : PAGE_SIZE; + } =20 - no_head_tail_room =3D params->xdp_prog && mpwqe && !mlx5e_rx_is_linear_sk= b(mdev, params, xsk); + no_head_tail_room =3D params->xdp_prog && mpwqe && + !mlx5e_rx_is_linear_skb(mdev, params, rqo); =20 /* When no_head_tail_room is set, headroom and tailroom are excluded from= skb calculations. * no_head_tail_room should be set in the case of XDP with Striding RQ @@ -291,11 +301,12 @@ static u32 mlx5e_rx_get_linear_stride_sz(struct mlx5_= core_dev *mdev, =20 static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5_core_dev *mdev, struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk) + struct mlx5e_rq_opt_param *rqo) { - u32 linear_stride_sz =3D mlx5e_rx_get_linear_stride_sz(mdev, params, xsk,= true); - enum mlx5e_mpwrq_umr_mode umr_mode =3D mlx5e_mpwrq_umr_mode(mdev, xsk); - u8 page_shift =3D mlx5e_mpwrq_page_shift(mdev, xsk); + enum mlx5e_mpwrq_umr_mode umr_mode =3D mlx5e_mpwrq_umr_mode(mdev, rqo); + u32 linear_stride_sz =3D + mlx5e_rx_get_linear_stride_sz(mdev, params, rqo, true); + u8 page_shift =3D mlx5e_mpwrq_page_shift(mdev, rqo); =20 return mlx5e_mpwrq_log_wqe_sz(mdev, page_shift, umr_mode) - order_base_2(linear_stride_sz); @@ -303,8 +314,10 @@ static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5_cor= e_dev *mdev, =20 bool mlx5e_rx_is_linear_skb(struct mlx5_core_dev *mdev, struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk) + struct mlx5e_rq_opt_param *rqo) { + struct mlx5e_xsk_param *xsk =3D mlx5e_rqo_xsk_param(rqo); + if (params->packet_merge.type !=3D MLX5E_PACKET_MERGE_NONE) return false; =20 @@ -315,7 +328,7 @@ bool mlx5e_rx_is_linear_skb(struct mlx5_core_dev *mdev, * Both XSK and non-XSK cases allocate an SKB on XDP_PASS. Packet data * must fit into a CPU page. */ - if (mlx5e_rx_get_linear_sz_skb(params, xsk) > PAGE_SIZE) + if (mlx5e_rx_get_linear_sz_skb(params, !!xsk) > PAGE_SIZE) return false; =20 /* XSK frames must be big enough to hold the packet data. */ @@ -349,12 +362,14 @@ static bool mlx5e_verify_rx_mpwqe_strides(struct mlx5= _core_dev *mdev, =20 bool mlx5e_verify_params_rx_mpwqe_strides(struct mlx5_core_dev *mdev, struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk) + struct mlx5e_rq_opt_param *rqo) { - u8 log_wqe_num_of_strides =3D mlx5e_mpwqe_get_log_num_strides(mdev, param= s, xsk); - u8 log_wqe_stride_size =3D mlx5e_mpwqe_get_log_stride_size(mdev, params, = xsk); - enum mlx5e_mpwrq_umr_mode umr_mode =3D mlx5e_mpwrq_umr_mode(mdev, xsk); - u8 page_shift =3D mlx5e_mpwrq_page_shift(mdev, xsk); + enum mlx5e_mpwrq_umr_mode umr_mode =3D mlx5e_mpwrq_umr_mode(mdev, rqo); + u8 log_wqe_num_of_strides =3D + mlx5e_mpwqe_get_log_num_strides(mdev, params, rqo); + u8 log_wqe_stride_size =3D + mlx5e_mpwqe_get_log_stride_size(mdev, params, rqo); + u8 page_shift =3D mlx5e_mpwrq_page_shift(mdev, rqo); =20 return mlx5e_verify_rx_mpwqe_strides(mdev, log_wqe_stride_size, log_wqe_num_of_strides, @@ -363,18 +378,20 @@ bool mlx5e_verify_params_rx_mpwqe_strides(struct mlx5= _core_dev *mdev, =20 bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev, struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk) + struct mlx5e_rq_opt_param *rqo) { - enum mlx5e_mpwrq_umr_mode umr_mode =3D mlx5e_mpwrq_umr_mode(mdev, xsk); - u8 page_shift =3D mlx5e_mpwrq_page_shift(mdev, xsk); + enum mlx5e_mpwrq_umr_mode umr_mode =3D mlx5e_mpwrq_umr_mode(mdev, rqo); + u32 linear_stride_sz =3D + mlx5e_rx_get_linear_stride_sz(mdev, params, rqo, true); + u8 page_shift =3D mlx5e_mpwrq_page_shift(mdev, rqo); u8 log_num_strides; u8 log_stride_sz; u8 log_wqe_sz; =20 - if (!mlx5e_rx_is_linear_skb(mdev, params, xsk)) + if (!mlx5e_rx_is_linear_skb(mdev, params, rqo)) return false; =20 - log_stride_sz =3D order_base_2(mlx5e_rx_get_linear_stride_sz(mdev, params= , xsk, true)); + log_stride_sz =3D order_base_2(linear_stride_sz); log_wqe_sz =3D mlx5e_mpwrq_log_wqe_sz(mdev, page_shift, umr_mode); =20 if (log_wqe_sz < log_stride_sz) @@ -389,13 +406,13 @@ bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_de= v *mdev, =20 u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5_core_dev *mdev, struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk) + struct mlx5e_rq_opt_param *rqo) { - enum mlx5e_mpwrq_umr_mode umr_mode =3D mlx5e_mpwrq_umr_mode(mdev, xsk); + enum mlx5e_mpwrq_umr_mode umr_mode =3D mlx5e_mpwrq_umr_mode(mdev, rqo); u8 log_pkts_per_wqe, page_shift, max_log_rq_size; =20 - log_pkts_per_wqe =3D mlx5e_mpwqe_log_pkts_per_wqe(mdev, params, xsk); - page_shift =3D mlx5e_mpwrq_page_shift(mdev, xsk); + log_pkts_per_wqe =3D mlx5e_mpwqe_log_pkts_per_wqe(mdev, params, rqo); + page_shift =3D mlx5e_mpwrq_page_shift(mdev, rqo); max_log_rq_size =3D mlx5e_mpwrq_max_log_rq_size(mdev, page_shift, umr_mod= e); =20 /* Numbers are unsigned, don't subtract to avoid underflow. */ @@ -423,10 +440,11 @@ static u8 mlx5e_shampo_get_log_pkt_per_rsrv(struct ml= x5e_params *params) =20 u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev, struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk) + struct mlx5e_rq_opt_param *rqo) { - if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, xsk)) - return order_base_2(mlx5e_rx_get_linear_stride_sz(mdev, params, xsk, tru= e)); + if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, rqo)) + return order_base_2(mlx5e_rx_get_linear_stride_sz(mdev, params, + rqo, true)); =20 /* XDP in mlx5e doesn't support multiple packets per page. */ if (params->xdp_prog) @@ -437,17 +455,18 @@ u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_d= ev *mdev, =20 u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev, struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk) + struct mlx5e_rq_opt_param *rqo) { - enum mlx5e_mpwrq_umr_mode umr_mode =3D mlx5e_mpwrq_umr_mode(mdev, xsk); - u8 page_shift =3D mlx5e_mpwrq_page_shift(mdev, xsk); + enum mlx5e_mpwrq_umr_mode umr_mode =3D mlx5e_mpwrq_umr_mode(mdev, rqo); + u8 page_shift =3D mlx5e_mpwrq_page_shift(mdev, rqo); u8 log_wqe_size, log_stride_size; =20 log_wqe_size =3D mlx5e_mpwrq_log_wqe_sz(mdev, page_shift, umr_mode); - log_stride_size =3D mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk); + log_stride_size =3D mlx5e_mpwqe_get_log_stride_size(mdev, params, rqo); WARN(log_wqe_size < log_stride_size, "Log WQE size %u < log stride size %u (page shift %u, umr mode %d, x= sk on? %d)\n", - log_wqe_size, log_stride_size, page_shift, umr_mode, !!xsk); + log_wqe_size, log_stride_size, page_shift, umr_mode, + rqo && rqo->xsk); return log_wqe_size - log_stride_size; } =20 @@ -459,14 +478,14 @@ u8 mlx5e_mpwqe_get_min_wqe_bulk(unsigned int wq_sz) =20 u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev, struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk) + struct mlx5e_rq_opt_param *rqo) { - u16 linear_headroom =3D mlx5e_get_linear_rq_headroom(params, xsk); + u16 linear_headroom =3D mlx5e_get_linear_rq_headroom(params, rqo); =20 if (params->rq_wq_type =3D=3D MLX5_WQ_TYPE_CYCLIC) return linear_headroom; =20 - if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, xsk)) + if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, rqo)) return linear_headroom; =20 if (params->packet_merge.type =3D=3D MLX5E_PACKET_MERGE_SHAMPO) @@ -535,10 +554,11 @@ int mlx5e_mpwrq_validate_regular(struct mlx5_core_dev= *mdev, struct mlx5e_params } =20 int mlx5e_mpwrq_validate_xsk(struct mlx5_core_dev *mdev, struct mlx5e_para= ms *params, - struct mlx5e_xsk_param *xsk) + struct mlx5e_rq_opt_param *rqo) { - enum mlx5e_mpwrq_umr_mode umr_mode =3D mlx5e_mpwrq_umr_mode(mdev, xsk); - u8 page_shift =3D mlx5e_mpwrq_page_shift(mdev, xsk); + enum mlx5e_mpwrq_umr_mode umr_mode =3D mlx5e_mpwrq_umr_mode(mdev, rqo); + struct mlx5e_xsk_param *xsk =3D mlx5e_rqo_xsk_param(rqo); + u8 page_shift =3D mlx5e_mpwrq_page_shift(mdev, rqo); u16 max_mtu_pkts; =20 if (!mlx5e_check_fragmented_striding_rq_cap(mdev, page_shift, umr_mode)) { @@ -547,7 +567,7 @@ int mlx5e_mpwrq_validate_xsk(struct mlx5_core_dev *mdev= , struct mlx5e_params *pa return -EOPNOTSUPP; } =20 - if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, xsk)) { + if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, rqo)) { mlx5_core_err(mdev, "Striding RQ linear mode for XSK can't be activated = with current params\n"); return -EINVAL; } @@ -559,7 +579,8 @@ int mlx5e_mpwrq_validate_xsk(struct mlx5_core_dev *mdev= , struct mlx5e_params *pa mlx5e_mpwrq_max_log_rq_pkts(mdev, page_shift, xsk->unaligned)); if (params->log_rq_mtu_frames > max_mtu_pkts) { mlx5_core_err(mdev, "Current RQ length %d is too big for XSK with given = frame size %u\n", - 1 << params->log_rq_mtu_frames, xsk->chunk_size); + 1 << params->log_rq_mtu_frames, + xsk->chunk_size); return -EINVAL; } =20 @@ -672,7 +693,7 @@ static void mlx5e_rx_compute_wqe_bulk_params(struct mlx= 5e_params *params, =20 static int mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev, struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk, + struct mlx5e_rq_opt_param *rqo, struct mlx5e_rq_frags_info *info, u32 *xdp_frag_size) { @@ -684,10 +705,11 @@ static int mlx5e_build_rq_frags_info(struct mlx5_core= _dev *mdev, int max_mtu; int i; =20 - if (mlx5e_rx_is_linear_skb(mdev, params, xsk)) { + if (mlx5e_rx_is_linear_skb(mdev, params, rqo)) { int frag_stride; =20 - frag_stride =3D mlx5e_rx_get_linear_stride_sz(mdev, params, xsk, false); + frag_stride =3D mlx5e_rx_get_linear_stride_sz(mdev, params, rqo, + false); =20 info->arr[0].frag_size =3D byte_count; info->arr[0].frag_stride =3D frag_stride; @@ -703,7 +725,7 @@ static int mlx5e_build_rq_frags_info(struct mlx5_core_d= ev *mdev, goto out; } =20 - headroom =3D mlx5e_get_linear_rq_headroom(params, xsk); + headroom =3D mlx5e_get_linear_rq_headroom(params, rqo); first_frag_size_max =3D SKB_WITH_OVERHEAD(frag_size_max - headroom); =20 max_mtu =3D mlx5e_max_nonlinear_mtu(first_frag_size_max, frag_size_max, @@ -819,12 +841,13 @@ static void mlx5e_build_common_cq_param(struct mlx5_c= ore_dev *mdev, =20 static u32 mlx5e_shampo_get_log_cq_size(struct mlx5_core_dev *mdev, struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk) + struct mlx5e_rq_opt_param *rqo) { - u16 num_strides =3D BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk= )); - u8 log_stride_sz =3D mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk); + u8 log_stride_sz =3D mlx5e_mpwqe_get_log_stride_size(mdev, params, rqo); + u16 num_strides =3D BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, + rqo)); int pkt_per_rsrv =3D BIT(mlx5e_shampo_get_log_pkt_per_rsrv(params)); - int wq_size =3D BIT(mlx5e_mpwqe_get_log_rq_size(mdev, params, xsk)); + int wq_size =3D BIT(mlx5e_mpwqe_get_log_rq_size(mdev, params, rqo)); int wqe_size =3D BIT(log_stride_sz) * num_strides; int rsrv_size =3D MLX5E_SHAMPO_WQ_RESRV_SIZE; =20 @@ -836,7 +859,7 @@ static u32 mlx5e_shampo_get_log_cq_size(struct mlx5_cor= e_dev *mdev, =20 static void mlx5e_build_rx_cq_param(struct mlx5_core_dev *mdev, struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk, + struct mlx5e_rq_opt_param *rqo, struct mlx5e_cq_param *param) { bool hw_stridx =3D false; @@ -847,10 +870,13 @@ static void mlx5e_build_rx_cq_param(struct mlx5_core_= dev *mdev, case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: hw_stridx =3D MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index); if (params->packet_merge.type =3D=3D MLX5E_PACKET_MERGE_SHAMPO) - log_cq_size =3D mlx5e_shampo_get_log_cq_size(mdev, params, xsk); + log_cq_size =3D + mlx5e_shampo_get_log_cq_size(mdev, params, rqo); else - log_cq_size =3D mlx5e_mpwqe_get_log_rq_size(mdev, params, xsk) + - mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk); + log_cq_size =3D + mlx5e_mpwqe_get_log_rq_size(mdev, params, rqo) + + mlx5e_mpwqe_get_log_num_strides(mdev, params, + rqo); break; default: /* MLX5_WQ_TYPE_CYCLIC */ log_cq_size =3D params->log_rq_mtu_frames; @@ -882,22 +908,22 @@ static u8 rq_end_pad_mode(struct mlx5_core_dev *mdev,= struct mlx5e_params *param =20 static int mlx5e_mpwqe_build_rq_param(struct mlx5_core_dev *mdev, struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk, + struct mlx5e_rq_opt_param *rqo, struct mlx5e_rq_param *rq_param) { - u8 log_rq_sz =3D mlx5e_mpwqe_get_log_rq_size(mdev, params, xsk); - u8 page_shift =3D mlx5e_mpwrq_page_shift(mdev, xsk); + u8 log_rq_sz =3D mlx5e_mpwqe_get_log_rq_size(mdev, params, rqo); + u8 page_shift =3D mlx5e_mpwrq_page_shift(mdev, rqo); u8 log_wqe_num_of_strides, log_wqe_stride_size; enum mlx5e_mpwrq_umr_mode umr_mode; void *rqc =3D rq_param->rqc; u32 lro_timeout; void *wq; =20 - log_wqe_num_of_strides =3D mlx5e_mpwqe_get_log_num_strides(mdev, params, - xsk); - log_wqe_stride_size =3D mlx5e_mpwqe_get_log_stride_size(mdev, params, - xsk); - umr_mode =3D mlx5e_mpwrq_umr_mode(mdev, xsk); + log_wqe_num_of_strides =3D + mlx5e_mpwqe_get_log_num_strides(mdev, params, rqo); + log_wqe_stride_size =3D + mlx5e_mpwqe_get_log_stride_size(mdev, params, rqo); + umr_mode =3D mlx5e_mpwrq_umr_mode(mdev, rqo); =20 wq =3D MLX5_ADDR_OF(rqc, rqc, wq); if (!mlx5e_verify_rx_mpwqe_strides(mdev, log_wqe_stride_size, @@ -940,7 +966,7 @@ static int mlx5e_mpwqe_build_rq_param(struct mlx5_core_= dev *mdev, =20 int mlx5e_build_rq_param(struct mlx5_core_dev *mdev, struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk, + struct mlx5e_rq_opt_param *rqo, struct mlx5e_rq_param *rq_param) { void *rqc =3D rq_param->rqc; @@ -952,13 +978,13 @@ int mlx5e_build_rq_param(struct mlx5_core_dev *mdev, =20 switch (params->rq_wq_type) { case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: - err =3D mlx5e_mpwqe_build_rq_param(mdev, params, xsk, rq_param); + err =3D mlx5e_mpwqe_build_rq_param(mdev, params, rqo, rq_param); if (err) return err; break; default: /* MLX5_WQ_TYPE_CYCLIC */ MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames); - err =3D mlx5e_build_rq_frags_info(mdev, params, xsk, + err =3D mlx5e_build_rq_frags_info(mdev, params, rqo, &rq_param->frags_info, &rq_param->xdp_frag_size); if (err) @@ -975,7 +1001,7 @@ int mlx5e_build_rq_param(struct mlx5_core_dev *mdev, MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en); =20 rq_param->wq.buf_numa_node =3D dev_to_node(mlx5_core_dma_dev(mdev)); - mlx5e_build_rx_cq_param(mdev, params, xsk, &rq_param->cqp); + mlx5e_build_rx_cq_param(mdev, params, rqo, &rq_param->cqp); =20 return 0; } @@ -1105,20 +1131,22 @@ u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *= mdev, u32 wanted_timeout) =20 static u32 mlx5e_mpwrq_total_umr_wqebbs(struct mlx5_core_dev *mdev, struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk) + struct mlx5e_rq_opt_param *rqo) { - enum mlx5e_mpwrq_umr_mode umr_mode =3D mlx5e_mpwrq_umr_mode(mdev, xsk); - u8 page_shift =3D mlx5e_mpwrq_page_shift(mdev, xsk); + enum mlx5e_mpwrq_umr_mode umr_mode =3D mlx5e_mpwrq_umr_mode(mdev, rqo); + u8 page_shift =3D mlx5e_mpwrq_page_shift(mdev, rqo); u8 umr_wqebbs; =20 umr_wqebbs =3D mlx5e_mpwrq_umr_wqebbs(mdev, page_shift, umr_mode); =20 - return umr_wqebbs * (1 << mlx5e_mpwqe_get_log_rq_size(mdev, params, xsk)); + return umr_wqebbs * + (1 << mlx5e_mpwqe_get_log_rq_size(mdev, params, rqo)); } =20 static u32 mlx5e_max_xsk_wqebbs(struct mlx5_core_dev *mdev, struct mlx5e_params *params) { + struct mlx5e_rq_opt_param rqo =3D {0}; struct mlx5e_xsk_param xsk =3D {0}; u32 max_xsk_wqebbs =3D 0; u8 frame_shift; @@ -1126,6 +1154,8 @@ static u32 mlx5e_max_xsk_wqebbs(struct mlx5_core_dev = *mdev, if (!params->xdp_prog) return 0; =20 + rqo.xsk =3D &xsk; + /* If XDP program is attached, XSK may be turned on at any time without * restarting the channel. ICOSQ must be big enough to fit UMR WQEs of * both regular RQ and XSK RQ. @@ -1145,24 +1175,24 @@ static u32 mlx5e_max_xsk_wqebbs(struct mlx5_core_de= v *mdev, /* XSK aligned mode. */ xsk.chunk_size =3D 1 << frame_shift; xsk.unaligned =3D false; - total_wqebbs =3D mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &xsk); + total_wqebbs =3D mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &rqo); max_xsk_wqebbs =3D max(max_xsk_wqebbs, total_wqebbs); =20 /* XSK unaligned mode, frame size is a power of two. */ xsk.unaligned =3D true; - total_wqebbs =3D mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &xsk); + total_wqebbs =3D mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &rqo); max_xsk_wqebbs =3D max(max_xsk_wqebbs, total_wqebbs); =20 /* XSK unaligned mode, frame size is not equal to stride * size. */ xsk.chunk_size -=3D 1; - total_wqebbs =3D mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &xsk); + total_wqebbs =3D mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &rqo); max_xsk_wqebbs =3D max(max_xsk_wqebbs, total_wqebbs); =20 /* XSK unaligned mode, frame size is a triple power of two. */ xsk.chunk_size =3D (1 << frame_shift) / 4 * 3; - total_wqebbs =3D mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &xsk); + total_wqebbs =3D mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &rqo); max_xsk_wqebbs =3D max(max_xsk_wqebbs, total_wqebbs); } =20 @@ -1278,7 +1308,7 @@ void mlx5e_build_xsk_channel_param(struct mlx5_core_d= ev *mdev, struct mlx5e_xsk_param *xsk, struct mlx5e_channel_param *cparam) { - cparam->xsk =3D xsk; - mlx5e_build_rq_param(mdev, params, xsk, &cparam->rq); + cparam->rq_opt.xsk =3D xsk; + mlx5e_build_rq_param(mdev, params, &cparam->rq_opt, &cparam->rq); mlx5e_build_xdpsq_param(mdev, params, &cparam->xdp_sq); } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.h b/drivers/= net/ethernet/mellanox/mlx5/core/en/params.h index c132649dd9f2..4bce769d48ed 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.h @@ -12,6 +12,10 @@ struct mlx5e_xsk_param { bool unaligned; }; =20 +struct mlx5e_rq_opt_param { + struct mlx5e_xsk_param *xsk; +}; + struct mlx5e_cq_param { u32 cqc[MLX5_ST_SZ_DW(cqc)]; struct mlx5_wq_param wq; @@ -38,11 +42,11 @@ struct mlx5e_sq_param { =20 struct mlx5e_channel_param { struct mlx5e_rq_param rq; + struct mlx5e_rq_opt_param rq_opt; struct mlx5e_sq_param txq_sq; struct mlx5e_sq_param xdp_sq; struct mlx5e_sq_param icosq; struct mlx5e_sq_param async_icosq; - struct mlx5e_xsk_param *xsk; }; =20 struct mlx5e_create_sq_param { @@ -57,9 +61,11 @@ struct mlx5e_create_sq_param { =20 /* Striding RQ dynamic parameters */ =20 -u8 mlx5e_mpwrq_page_shift(struct mlx5_core_dev *mdev, struct mlx5e_xsk_par= am *xsk); +u8 mlx5e_mpwrq_page_shift(struct mlx5_core_dev *mdev, + struct mlx5e_rq_opt_param *rqo); enum mlx5e_mpwrq_umr_mode -mlx5e_mpwrq_umr_mode(struct mlx5_core_dev *mdev, struct mlx5e_xsk_param *x= sk); +mlx5e_mpwrq_umr_mode(struct mlx5_core_dev *mdev, + struct mlx5e_rq_opt_param *rqo); u8 mlx5e_mpwrq_umr_entry_size(enum mlx5e_mpwrq_umr_mode mode); u8 mlx5e_mpwrq_log_wqe_sz(struct mlx5_core_dev *mdev, u8 page_shift, enum mlx5e_mpwrq_umr_mode umr_mode); @@ -81,22 +87,22 @@ u8 mlx5e_mpwrq_max_log_rq_pkts(struct mlx5_core_dev *md= ev, u8 page_shift, bool slow_pci_heuristic(struct mlx5_core_dev *mdev); int mlx5e_mpwrq_validate_regular(struct mlx5_core_dev *mdev, struct mlx5e_= params *params); int mlx5e_mpwrq_validate_xsk(struct mlx5_core_dev *mdev, struct mlx5e_para= ms *params, - struct mlx5e_xsk_param *xsk); + struct mlx5e_rq_opt_param *rqo); void mlx5e_build_rq_params(struct mlx5_core_dev *mdev, struct mlx5e_params= *params); void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *pa= rams); void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev, struct mlx5e_pa= rams *params); =20 u16 mlx5e_get_linear_rq_headroom(struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk); + struct mlx5e_rq_opt_param *rqo); bool mlx5e_rx_is_linear_skb(struct mlx5_core_dev *mdev, struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk); + struct mlx5e_rq_opt_param *rqo); bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev, struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk); + struct mlx5e_rq_opt_param *rqo); u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5_core_dev *mdev, struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk); + struct mlx5e_rq_opt_param *rqo); u32 mlx5e_shampo_hd_per_wqe(struct mlx5_core_dev *mdev, struct mlx5e_params *params, struct mlx5e_rq_param *rq_param); @@ -106,21 +112,21 @@ u32 mlx5e_shampo_hd_per_wq(struct mlx5_core_dev *mdev, u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeou= t); u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev, struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk); + struct mlx5e_rq_opt_param *rqo); u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev, struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk); + struct mlx5e_rq_opt_param *rqo); u8 mlx5e_mpwqe_get_min_wqe_bulk(unsigned int wq_sz); u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev, struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk); + struct mlx5e_rq_opt_param *rqo); =20 /* Build queue parameters */ =20 void mlx5e_build_create_cq_param(struct mlx5e_create_cq_param *ccp, struct= mlx5e_channel *c); int mlx5e_build_rq_param(struct mlx5_core_dev *mdev, struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk, + struct mlx5e_rq_opt_param *rqo, struct mlx5e_rq_param *param); void mlx5e_build_drop_rq_param(struct mlx5_core_dev *mdev, struct mlx5e_rq_param *param); @@ -148,7 +154,7 @@ u16 mlx5e_calc_sq_stop_room(struct mlx5_core_dev *mdev,= struct mlx5e_params *par int mlx5e_validate_params(struct mlx5_core_dev *mdev, struct mlx5e_params = *params); bool mlx5e_verify_params_rx_mpwqe_strides(struct mlx5_core_dev *mdev, struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk); + struct mlx5e_rq_opt_param *rqo); =20 static inline void mlx5e_params_print_info(struct mlx5_core_dev *mdev, struct mlx5e_params *params) @@ -164,4 +170,10 @@ static inline void mlx5e_params_print_info(struct mlx5= _core_dev *mdev, "enhanced" : "basic"); }; =20 +static inline struct mlx5e_xsk_param * +mlx5e_rqo_xsk_param(struct mlx5e_rq_opt_param *rqo) +{ + return rqo ? rqo->xsk : NULL; +} + #endif /* __MLX5_EN_PARAMS_H__ */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c b/drivers/net= /ethernet/mellanox/mlx5/core/en/xdp.c index 80f9fc10877a..04e1b5fa4825 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c @@ -37,9 +37,10 @@ #include #include =20 -int mlx5e_xdp_max_mtu(struct mlx5e_params *params, struct mlx5e_xsk_param = *xsk) +int mlx5e_xdp_max_mtu(struct mlx5e_params *params, + struct mlx5e_rq_opt_param *rqo) { - int hr =3D mlx5e_get_linear_rq_headroom(params, xsk); + int hr =3D mlx5e_get_linear_rq_headroom(params, rqo); =20 /* Let S :=3D SKB_DATA_ALIGN(sizeof(struct skb_shared_info)). * The condition checked in mlx5e_rx_is_linear_skb is: diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.h b/drivers/net= /ethernet/mellanox/mlx5/core/en/xdp.h index 46ab0a9e8cdd..3c54f8962664 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.h @@ -96,7 +96,8 @@ union mlx5e_xdp_info { }; =20 struct mlx5e_xsk_param; -int mlx5e_xdp_max_mtu(struct mlx5e_params *params, struct mlx5e_xsk_param = *xsk); +int mlx5e_xdp_max_mtu(struct mlx5e_params *params, + struct mlx5e_rq_opt_param *rqo); bool mlx5e_xdp_handle(struct mlx5e_rq *rq, struct bpf_prog *prog, struct mlx5e_xdp_buff *mlctx); void mlx5e_xdp_mpwqe_complete(struct mlx5e_xdpsq *sq); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/pool.c b/driver= s/net/ethernet/mellanox/mlx5/core/en/xsk/pool.c index 92bcf16a2019..565e5c4ddcce 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/pool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/pool.c @@ -80,6 +80,7 @@ static int mlx5e_xsk_enable_locked(struct mlx5e_priv *pri= v, { struct mlx5e_params *params =3D &priv->channels.params; struct mlx5e_channel_param *cparam; + enum mlx5e_mpwrq_umr_mode umr_mode; struct mlx5e_xsk_param xsk; struct mlx5e_channel *c; int err; @@ -105,8 +106,9 @@ static int mlx5e_xsk_enable_locked(struct mlx5e_priv *p= riv, mlx5e_build_xsk_param(pool, &xsk); mlx5e_build_xsk_channel_param(priv->mdev, params, &xsk, cparam); =20 + umr_mode =3D mlx5e_mpwrq_umr_mode(priv->mdev, &cparam->rq_opt); if (priv->channels.params.rq_wq_type =3D=3D MLX5_WQ_TYPE_LINKED_LIST_STRI= DING_RQ && - mlx5e_mpwrq_umr_mode(priv->mdev, &xsk) =3D=3D MLX5E_MPWRQ_UMR_MODE_OV= ERSIZED) { + umr_mode =3D=3D MLX5E_MPWRQ_UMR_MODE_OVERSIZED) { const char *recommendation =3D is_power_of_2(xsk.chunk_size) ? "Upgrade firmware" : "Disable striding RQ"; =20 @@ -163,7 +165,7 @@ static int mlx5e_xsk_enable_locked(struct mlx5e_priv *p= riv, /* Check the configuration in advance, rather than fail at a later stage * (in mlx5e_xdp_set or on open) and end up with no channels. */ - if (!mlx5e_validate_xsk_param(params, &xsk, priv->mdev)) { + if (!mlx5e_validate_xsk_param(params, &cparam->rq_opt, priv->mdev)) { err =3D -EINVAL; goto err_remove_pool; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c b/drive= rs/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c index 03f1be361701..11500fd213a5 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c @@ -9,9 +9,9 @@ =20 static int mlx5e_legacy_rq_validate_xsk(struct mlx5_core_dev *mdev, struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk) + struct mlx5e_rq_opt_param *rqo) { - if (!mlx5e_rx_is_linear_skb(mdev, params, xsk)) { + if (!mlx5e_rx_is_linear_skb(mdev, params, rqo)) { mlx5_core_err(mdev, "Legacy RQ linear mode for XSK can't be activated wi= th current params\n"); return -EINVAL; } @@ -25,9 +25,14 @@ static int mlx5e_legacy_rq_validate_xsk(struct mlx5_core= _dev *mdev, #define MLX5E_MIN_XSK_CHUNK_SIZE max(2048, XDP_UMEM_MIN_CHUNK_SIZE) =20 bool mlx5e_validate_xsk_param(struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk, + struct mlx5e_rq_opt_param *rqo, struct mlx5_core_dev *mdev) { + struct mlx5e_xsk_param *xsk =3D mlx5e_rqo_xsk_param(rqo); + + if (WARN_ON(!xsk)) + return false; + /* AF_XDP doesn't support frames larger than PAGE_SIZE, * and xsk->chunk_size is limited to 65535 bytes. */ @@ -42,9 +47,9 @@ bool mlx5e_validate_xsk_param(struct mlx5e_params *params, */ switch (params->rq_wq_type) { case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: - return !mlx5e_mpwrq_validate_xsk(mdev, params, xsk); + return !mlx5e_mpwrq_validate_xsk(mdev, params, rqo); default: /* MLX5_WQ_TYPE_CYCLIC */ - return !mlx5e_legacy_rq_validate_xsk(mdev, params, xsk); + return !mlx5e_legacy_rq_validate_xsk(mdev, params, rqo); } } =20 @@ -83,19 +88,20 @@ static int mlx5e_init_xsk_rq(struct mlx5e_channel *c, =20 static int mlx5e_open_xsk_rq(struct mlx5e_channel *c, struct mlx5e_params *params, - struct mlx5e_rq_param *rq_param, - struct xsk_buff_pool *pool, - struct mlx5e_xsk_param *xsk) + struct mlx5e_channel_param *cparam, + struct xsk_buff_pool *pool) { + struct mlx5e_rq_param *rq_param =3D &cparam->rq; + struct mlx5e_rq_opt_param *rqo =3D &cparam->rq_opt; u16 q_counter =3D c->priv->q_counter[c->sd_ix]; struct mlx5e_rq *xskrq =3D &c->xskrq; int err; =20 - err =3D mlx5e_init_xsk_rq(c, params, pool, xsk, xskrq); + err =3D mlx5e_init_xsk_rq(c, params, pool, rqo->xsk, xskrq); if (err) return err; =20 - err =3D mlx5e_open_rq(params, rq_param, xsk, cpu_to_node(c->cpu), + err =3D mlx5e_open_rq(params, rq_param, rqo, cpu_to_node(c->cpu), q_counter, xskrq); if (err) return err; @@ -109,13 +115,12 @@ int mlx5e_open_xsk(struct mlx5e_priv *priv, struct ml= x5e_params *params, struct xsk_buff_pool *pool, struct mlx5e_channel *c) { - struct mlx5e_xsk_param *xsk =3D cparam->xsk; struct mlx5e_create_cq_param ccp; int err; =20 mlx5e_build_create_cq_param(&ccp, c); =20 - if (!mlx5e_validate_xsk_param(params, xsk, priv->mdev)) + if (!mlx5e_validate_xsk_param(params, &cparam->rq_opt, priv->mdev)) return -EINVAL; =20 err =3D mlx5e_open_cq(c->mdev, params->rx_cq_moderation, &cparam->rq.cqp,= &ccp, @@ -123,7 +128,7 @@ int mlx5e_open_xsk(struct mlx5e_priv *priv, struct mlx5= e_params *params, if (unlikely(err)) return err; =20 - err =3D mlx5e_open_xsk_rq(c, params, &cparam->rq, pool, xsk); + err =3D mlx5e_open_xsk_rq(c, params, cparam, pool); if (unlikely(err)) goto err_close_rx_cq; =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.h b/drive= rs/net/ethernet/mellanox/mlx5/core/en/xsk/setup.h index fc86d19ea2b3..664ec78192c3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.h @@ -9,7 +9,7 @@ struct mlx5e_xsk_param; =20 bool mlx5e_validate_xsk_param(struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk, + struct mlx5e_rq_opt_param *rqo, struct mlx5_core_dev *mdev); struct mlx5e_channel_param; int mlx5e_open_xsk(struct mlx5e_priv *priv, struct mlx5e_params *params, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 35b767105492..9e406275e243 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -851,8 +851,8 @@ static void mlx5e_rq_free_shampo(struct mlx5e_rq *rq) } =20 static int mlx5e_alloc_rq(struct mlx5e_params *params, - struct mlx5e_xsk_param *xsk, struct mlx5e_rq_param *rq_param, + struct mlx5e_rq_opt_param *rqo, int node, struct mlx5e_rq *rq) { void *rqc_wq =3D MLX5_ADDR_OF(rqc, rq_param->rqc, wq); @@ -871,7 +871,7 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params, RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog); =20 rq->buff.map_dir =3D params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVI= CE; - rq->buff.headroom =3D mlx5e_get_rq_headroom(mdev, params, xsk); + rq->buff.headroom =3D mlx5e_get_rq_headroom(mdev, params, rqo); pool_size =3D 1 << params->log_rq_mtu_frames; =20 rq->mkey_be =3D cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey); @@ -891,8 +891,8 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params, =20 wq_sz =3D mlx5_wq_ll_get_size(&rq->mpwqe.wq); =20 - rq->mpwqe.page_shift =3D mlx5e_mpwrq_page_shift(mdev, xsk); - rq->mpwqe.umr_mode =3D mlx5e_mpwrq_umr_mode(mdev, xsk); + rq->mpwqe.page_shift =3D mlx5e_mpwrq_page_shift(mdev, rqo); + rq->mpwqe.umr_mode =3D mlx5e_mpwrq_umr_mode(mdev, rqo); rq->mpwqe.pages_per_wqe =3D mlx5e_mpwrq_pages_per_wqe(mdev, rq->mpwqe.page_shift, rq->mpwqe.umr_mode); @@ -904,14 +904,17 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params, rq->mpwqe.umr_mode); =20 pool_size =3D rq->mpwqe.pages_per_wqe << - mlx5e_mpwqe_get_log_rq_size(mdev, params, xsk); + mlx5e_mpwqe_get_log_rq_size(mdev, params, rqo); =20 - if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, xsk) && params->xdp_prog) + if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, rqo) && + params->xdp_prog) pool_size *=3D 2; /* additional page per packet for the linear part */ =20 - rq->mpwqe.log_stride_sz =3D mlx5e_mpwqe_get_log_stride_size(mdev, params= , xsk); + rq->mpwqe.log_stride_sz =3D + mlx5e_mpwqe_get_log_stride_size(mdev, params, + rqo); rq->mpwqe.num_strides =3D - BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk)); + BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, rqo)); rq->mpwqe.min_wqe_bulk =3D mlx5e_mpwqe_get_min_wqe_bulk(wq_sz); =20 rq->buff.frame0_sz =3D (1 << rq->mpwqe.log_stride_sz); @@ -947,7 +950,7 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params, goto err_rq_wq_destroy; } =20 - if (xsk) { + if (mlx5e_rqo_xsk_param(rqo)) { err =3D xdp_rxq_info_reg_mem_model(&rq->xdp_rxq, MEM_TYPE_XSK_BUFF_POOL, NULL); if (err) @@ -1324,7 +1327,7 @@ void mlx5e_free_rx_descs(struct mlx5e_rq *rq) } =20 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *rq_p= aram, - struct mlx5e_xsk_param *xsk, int node, u16 q_counter, + struct mlx5e_rq_opt_param *rqo, int node, u16 q_counter, struct mlx5e_rq *rq) { struct mlx5_core_dev *mdev =3D rq->mdev; @@ -1333,7 +1336,7 @@ int mlx5e_open_rq(struct mlx5e_params *params, struct= mlx5e_rq_param *rq_param, if (params->packet_merge.type =3D=3D MLX5E_PACKET_MERGE_SHAMPO) __set_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state); =20 - err =3D mlx5e_alloc_rq(params, xsk, rq_param, node, rq); + err =3D mlx5e_alloc_rq(params, rq_param, rqo, node, rq); if (err) return err; =20 @@ -4587,6 +4590,7 @@ static bool mlx5e_xsk_validate_mtu(struct net_device = *netdev, for (ix =3D 0; ix < chs->params.num_channels; ix++) { struct xsk_buff_pool *xsk_pool =3D mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, ix); + struct mlx5e_rq_opt_param rqo =3D {0}; struct mlx5e_xsk_param xsk; int max_xdp_mtu; =20 @@ -4594,12 +4598,13 @@ static bool mlx5e_xsk_validate_mtu(struct net_devic= e *netdev, continue; =20 mlx5e_build_xsk_param(xsk_pool, &xsk); - max_xdp_mtu =3D mlx5e_xdp_max_mtu(new_params, &xsk); + rqo.xsk =3D &xsk; + max_xdp_mtu =3D mlx5e_xdp_max_mtu(new_params, &rqo); =20 /* Validate XSK params and XDP MTU in advance */ - if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev) || + if (!mlx5e_validate_xsk_param(new_params, &rqo, mdev) || new_params->sw_mtu > max_xdp_mtu) { - u32 hr =3D mlx5e_get_linear_rq_headroom(new_params, &xsk); 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Mon, 23 Feb 2026 12:43:17 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Richard Cochran , , , , , Gal Pressman , Dragos Tatulea , Cosmin Ratiu , Pavel Begunkov , David Wei Subject: [PATCH net-next 07/15] net/mlx5e: Drop unused channel parameters Date: Mon, 23 Feb 2026 22:41:47 +0200 Message-ID: <20260223204155.1783580-8-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260223204155.1783580-1-tariqt@nvidia.com> References: <20260223204155.1783580-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000203:EE_|DM6PR12MB4369:EE_ X-MS-Office365-Filtering-Correlation-Id: 162db9d8-a52f-448e-f0b8-08de731c359e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700013|82310400026|1800799024; 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charset="utf-8" From: Dragos Tatulea The channel parameters from struct mlx5_qmgmt_data are built in mlx5e_queue_mem_alloc() but are not used. mlx5e_open_channel() builds the channel parameters internally and those parameters will be the ones that are used when opening the queue. This patch drops the unused parameters. Signed-off-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 9e406275e243..aca88fed2ac7 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -5555,7 +5555,6 @@ static const struct netdev_stat_ops mlx5e_stat_ops = =3D { =20 struct mlx5_qmgmt_data { struct mlx5e_channel *c; - struct mlx5e_channel_param cparam; }; =20 static int mlx5e_queue_mem_alloc(struct net_device *dev, @@ -5566,7 +5565,6 @@ static int mlx5e_queue_mem_alloc(struct net_device *d= ev, struct mlx5e_priv *priv =3D netdev_priv(dev); struct mlx5e_channels *chs =3D &priv->channels; struct mlx5e_params params =3D chs->params; - struct mlx5_core_dev *mdev; int err; =20 mutex_lock(&priv->state_lock); @@ -5590,11 +5588,6 @@ static int mlx5e_queue_mem_alloc(struct net_device *= dev, goto unlock; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Richard Cochran , , , , , Gal Pressman , Dragos Tatulea , Cosmin Ratiu , Pavel Begunkov , David Wei Subject: [PATCH net-next 08/15] net/mlx5e: SHAMPO, Always calculate page size Date: Mon, 23 Feb 2026 22:41:48 +0200 Message-ID: <20260223204155.1783580-9-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260223204155.1783580-1-tariqt@nvidia.com> References: <20260223204155.1783580-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000208:EE_|CY3PR12MB9703:EE_ X-MS-Office365-Filtering-Correlation-Id: 117ed158-063d-488b-24ca-08de731c39ad X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?7JFra4iSUdAO8zgx7kA+23XbcH55zV3k2ppFBahibsKFo6jDmYOeDXccgkVR?= =?us-ascii?Q?iHdxUBpqE4u91+7MmFeEMUtWw1WRrFZ4kLRpxa+N/z+AExN+iHRdiVM7VKFo?= =?us-ascii?Q?UQ1AVLwtfbpC1hwD0d6whh4A7QIfly1Dga+289sh0epId/0bndN51Xrrzjea?= =?us-ascii?Q?4iAHpNSsGrWsfNPFV8cBP+x2nsysy87d+4C85yVmVKP5IHI8avQYIgVIX52w?= =?us-ascii?Q?NtiF56T2Q50c0HhtSKRKORNt0wwefznkmWQkGUCT9dwp8QVXpLvZKqfIoirc?= =?us-ascii?Q?kK543nFeDHirKNQ9tk3qvBRkE59TIm1XpYiVE3QJlHJKGrIEoNANVdCJIRqw?= =?us-ascii?Q?y61a9sF0yzJgEOTuVLOCHV1kCo5sO+K0T5zfxuUC3JknlDnhPNtwbRKON4It?= =?us-ascii?Q?fBYJcxS9GcSzJJ8pYEv77Bjuuz6N/STDEEJ27dIcdY2gEv8ccf0iNcK35sG1?= =?us-ascii?Q?4Q5+41eKN9bC/KEj3aZeCkTNWuT9kxtal82/0N+cg1gEGP5UTbdecaO7DAnc?= =?us-ascii?Q?QYHGkXujGVXkOp8pWKDOfl5Om7xAIlLHQZGo6gcHciNUmIlPDCjc3bJ0SHHi?= =?us-ascii?Q?ycUzcEis45NBPX0EABL+Na70Oth3eKUTXF97b0+LKXMDcQAs4i9ASlUdB5u5?= =?us-ascii?Q?3XQ4Pzv5W5Zr2Jjj8zQxbItRqNIjaCcUe2F+06E7ldhoJmdheL08cU/AVIgA?= =?us-ascii?Q?aNTGUvn9W7MxEmQ9NL/6PNYA+Ea2yh2hm7rsYGaoWAb33dW9mf2mppPJmIUV?= =?us-ascii?Q?UheDUaP2qhKwxC+S6nY2iv3YJItBX4jkdCAhtesQRd7dQRMgrjSEOdgw3Ji7?= =?us-ascii?Q?eq0CIHFe6gkmTjj4W9mKPzJPsNFmznwvOtfXGIA77dR/ymH2JZC3dhXhwsO7?= =?us-ascii?Q?OwxH7mQdXMDX7CNodU1HrMKg7V3qkYYOH2l/GffTagnuX1Sk501EvDEqHQoP?= =?us-ascii?Q?mi9Y8AthDXDqT2m5wMJF9aH44GvALYLWaPI3r9wuIWn7s4joJpm2F+0vNcNi?= =?us-ascii?Q?a467ebN9+mU7+oXFKv/ewNGTfHAO/Km9VgqMTY2pdgH3NaZ20c/HOmV2HSqP?= =?us-ascii?Q?M5FHJw6te7PN+xo6FNkN6H9w4RxaDvL0dV4say+KUFaHCRxEMkTK+aSFnXHT?= =?us-ascii?Q?P/waC07Q3p9maVuXIFJX+VTZb5IpN610dOvRxWAY8a93/qslFxV9/4jbvBNC?= =?us-ascii?Q?lQKFIvS++OHo53pXZYtYdg/Bnlqh5VxvAkpA24fhwlYR2uc4fLplsqfE0C//?= =?us-ascii?Q?vN09rupVoo7bynz6MlsaAoCAl2F4bpmcu1OGB2Wa8oMExRxK3pc4e4ur8rBF?= =?us-ascii?Q?l9Dyx67cYQ0Rdmtf/RnNKwhIPrtBV/N/z99+RH/nIlCp2Vw5Wx+FTRUrTWCa?= =?us-ascii?Q?KfWobaYlwfBFuBNma15CdxromMfVOkE6aUtGTFLKJT17BvwUI+nmvWzDbILH?= =?us-ascii?Q?MsnCiB1aTzIvUsxAa+3whGjBHcGIz/XGYNHeU6IEWVDhvtJs8Gn/Wd9jE/lf?= =?us-ascii?Q?q8ynyWL30g17WYwkXWRNgL7Inz+zf6THMdq6XNf7UQ2ulzUdQCbuZD/9CrHF?= =?us-ascii?Q?roxcusYvXdU0itY7UJefeq8ldvb6J04JLQ7zJ/xpChXEdwGFsgP4eWgIQkyZ?= =?us-ascii?Q?TuswyiNFqvN5OsHsI9ESV9gHWga7/LdKaQHCOeJXGnqgsVZsTz3h2RoVdaYg?= =?us-ascii?Q?bpJhSA=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0tslJGv1CYYc3+LKq8JjMVF8OMhcbpHHGOK9E57EohSbxLV7OwkJxgE8TeKr7sDn2LUrgS0vo6lIKlvkuust2vrQyBjHV8iHeC8XO1qcEGNPx6Iva6X4/ZpsKUjMbxyoprij59nN0hFKiuzVHVtdvebanFH/9OoAeM39UcZzZ8oQaYcMH7+k1ZgTTj712B28AdXBqfPV/FX9Ek/V8t7d8aFEOBZTnrPY03CaFU12MTAy+PEMhMQ6Ki+30SKBwLwnbY47S4tRV6GukI5WT12dy6RFJMuuLXYMBC2xGmJfhnNpm8ly67NKstnvM1wfBVPC0QsdItQSRyiUl/uSHFGGzjGeTjP2KoFbY/P0RGZwtkN2kd8/mx5/nfuOyFfGTwfNxU+UXa5m3dU7U3DTlt8Ib78uHZT2frdfDKjbbVvpLo1rnbV+GjlercD6tUnLyi5D X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Feb 2026 20:43:39.6811 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 117ed158-063d-488b-24ca-08de731c39ad X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000208.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY3PR12MB9703 Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea Adapt the rx path in SHAMPO mode to calculate page size based on configured page_shift when dealing with payload data. This is necessary as an upcoming patch will add support for using different page sizes. This change has no functional changes. Signed-off-by: Dragos Tatulea Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en_rx.c | 34 ++++++++++++------- 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/= ethernet/mellanox/mlx5/core/en_rx.c index efcfcddab376..fc95ea00666b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c @@ -1847,11 +1847,14 @@ mlx5e_shampo_fill_skb_data(struct sk_buff *skb, str= uct mlx5e_rq *rq, struct mlx5e_frag_page *frag_page, u32 data_bcnt, u32 data_offset) { + u32 page_size =3D BIT(rq->mpwqe.page_shift); + net_prefetchw(skb->data); =20 do { /* Non-linear mode, hence non-XSK, which always uses PAGE_SIZE. */ - u32 pg_consumed_bytes =3D min_t(u32, PAGE_SIZE - data_offset, data_bcnt); + u32 pg_consumed_bytes =3D min_t(u32, page_size - data_offset, + data_bcnt); unsigned int truesize =3D pg_consumed_bytes; =20 mlx5e_add_skb_frag(rq, skb, frag_page, data_offset, @@ -1872,6 +1875,7 @@ mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *r= q, struct mlx5e_mpw_info *w u16 headlen =3D min_t(u16, MLX5E_RX_MAX_HEAD, cqe_bcnt); struct mlx5e_frag_page *head_page =3D frag_page; struct mlx5e_xdp_buff *mxbuf =3D &rq->mxbuf; + u32 page_size =3D BIT(rq->mpwqe.page_shift); u32 frag_offset =3D head_offset; u32 byte_cnt =3D cqe_bcnt; struct skb_shared_info *sinfo; @@ -1926,9 +1930,9 @@ mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *r= q, struct mlx5e_mpw_info *w linear_hr =3D skb_headroom(skb); linear_data_len =3D headlen; linear_frame_sz =3D MLX5_SKB_FRAG_SZ(skb_end_offset(skb)); - if (unlikely(frag_offset >=3D PAGE_SIZE)) { + if (unlikely(frag_offset >=3D page_size)) { frag_page++; - frag_offset -=3D PAGE_SIZE; + frag_offset -=3D page_size; } } =20 @@ -1940,7 +1944,7 @@ mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *r= q, struct mlx5e_mpw_info *w while (byte_cnt) { /* Non-linear mode, hence non-XSK, which always uses PAGE_SIZE. */ pg_consumed_bytes =3D - min_t(u32, PAGE_SIZE - frag_offset, byte_cnt); + min_t(u32, page_size - frag_offset, byte_cnt); =20 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) truesize +=3D pg_consumed_bytes; @@ -1978,7 +1982,7 @@ mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *r= q, struct mlx5e_mpw_info *w nr_frags_free =3D old_nr_frags - sinfo->nr_frags; if (unlikely(nr_frags_free)) { frag_page -=3D nr_frags_free; - truesize -=3D (nr_frags_free - 1) * PAGE_SIZE + + truesize -=3D (nr_frags_free - 1) * page_size + ALIGN(pg_consumed_bytes, BIT(rq->mpwqe.log_stride_sz)); } @@ -2166,15 +2170,16 @@ mlx5e_shampo_flush_skb(struct mlx5e_rq *rq, struct = mlx5_cqe64 *cqe, bool match) rq->hw_gro_data->skb =3D NULL; } =20 -static bool -mlx5e_hw_gro_skb_has_enough_space(struct sk_buff *skb, u16 data_bcnt) +static bool mlx5e_hw_gro_skb_has_enough_space(struct sk_buff *skb, + u16 data_bcnt, + u32 page_size) { int nr_frags =3D skb_shinfo(skb)->nr_frags; =20 - if (PAGE_SIZE >=3D GRO_LEGACY_MAX_SIZE) + if (page_size >=3D GRO_LEGACY_MAX_SIZE) return skb->len + data_bcnt <=3D GRO_LEGACY_MAX_SIZE; else - return PAGE_SIZE * nr_frags + data_bcnt <=3D GRO_LEGACY_MAX_SIZE; + return page_size * nr_frags + data_bcnt <=3D GRO_LEGACY_MAX_SIZE; } =20 static void mlx5e_handle_rx_cqe_mpwrq_shampo(struct mlx5e_rq *rq, struct m= lx5_cqe64 *cqe) @@ -2183,18 +2188,19 @@ static void mlx5e_handle_rx_cqe_mpwrq_shampo(struct= mlx5e_rq *rq, struct mlx5_cq u16 header_index =3D mlx5e_shampo_get_cqe_header_index(rq, cqe); u32 wqe_offset =3D be32_to_cpu(cqe->shampo.data_offset); u16 cstrides =3D mpwrq_get_cqe_consumed_strides(cqe); - u32 data_offset =3D wqe_offset & (PAGE_SIZE - 1); u32 cqe_bcnt =3D mpwrq_get_cqe_byte_cnt(cqe); u16 wqe_id =3D be16_to_cpu(cqe->wqe_id); - u32 page_idx =3D wqe_offset >> PAGE_SHIFT; u16 head_size =3D cqe->shampo.header_size; struct sk_buff **skb =3D &rq->hw_gro_data->skb; bool flush =3D cqe->shampo.flush; bool match =3D cqe->shampo.match; + u32 page_size =3D BIT(rq->mpwqe.page_shift); struct mlx5e_rq_stats *stats =3D rq->stats; struct mlx5e_rx_wqe_ll *wqe; struct mlx5e_mpw_info *wi; struct mlx5_wq_ll *wq; + u32 data_offset; + u32 page_idx; =20 wi =3D mlx5e_get_mpw_info(rq, wqe_id); wi->consumed_strides +=3D cstrides; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Richard Cochran , , , , , Gal Pressman , Dragos Tatulea , Cosmin Ratiu , Pavel Begunkov , David Wei Subject: [PATCH net-next 09/15] net/mlx5e: Set page_pool order based on calculated page_shift Date: Mon, 23 Feb 2026 22:41:49 +0200 Message-ID: <20260223204155.1783580-10-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260223204155.1783580-1-tariqt@nvidia.com> References: <20260223204155.1783580-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF0000020A:EE_|BL1PR12MB5948:EE_ X-MS-Office365-Filtering-Correlation-Id: bcfafbd2-f57f-4489-f925-08de731c3fab X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|376014|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?VEwqqjk7fsNOCclVDjsfvfk+sKwMgAbiOfGDzBDamLscCaGE4a6oU4oExEdz?= =?us-ascii?Q?siPzC7GpfEgie+LKpJFsQvZwaw8bucMbobQVDN1r85HZrHsdPq3DPxHa2lpI?= =?us-ascii?Q?GAIpa6WZ1B99FxlboGNIUBjzfMkJoTvewvrtWCrtPtkVqvpvg1iJlNsBG8Jq?= =?us-ascii?Q?waBe3Eyu/wr0+AMNOQpxAgyf3c9hA9kE2MJ6AMwKDUw/m87GgKnMeclBxtbg?= =?us-ascii?Q?BhhhHllrzo+lvnNRORHb+ndWsoA4HnpiWH+7jgVzrh4itDaLemnxnhUAzyvY?= =?us-ascii?Q?+FOAVdiWV0Ypuq09SJVS1xg0vnrzCacp5oktofglQVefErTdU6S8ztWfdL0x?= =?us-ascii?Q?jx09gPgA2RTK4IO2yVue59z/6RwGn7xAA1Wmir+ifmGBevGlmaSuIbH5oYO/?= =?us-ascii?Q?63oq4Sb9L4tYWla3K+G6LsVaE6nbPQX7a62iklRlrhLrkucgZXmSh696j1sL?= =?us-ascii?Q?KLwuUZGZ74hbztgAdkpEgYqjrJbadddW+UNiE98jc3bTF3i3p60bveQ483xa?= =?us-ascii?Q?NwQH+iocWWWNn/plMsmVNNPhw8tpjCXRb6x5PRoYU3hfIuQK0aI2HJg0uUjr?= =?us-ascii?Q?mznlhTW+1lyuDSa8z4nQTbuCoJh8M+Svhg7OGjLA5Kudx5DRBluMRMMAULMR?= =?us-ascii?Q?qfK3jtak6NnMVr4NW1aML+9BgQCMk0PCaArHVfRz+pK32tYbds3wMDoEPyyO?= =?us-ascii?Q?wICcsG1DlcvCJjHqcf7pyy1aWC+tsMVZOLCCr4rMxq8eBnHbIVyYcCeECJ0a?= =?us-ascii?Q?tE6IiXhhEpBJWNrhFkXpQGxWmWx0k5ik2KJxXVsZcMR1lIpRuUxW217Ws/ml?= =?us-ascii?Q?28CThJCTyEnGfue6rEq8uqb80nLkftJJH9bUSwZ3C6yZQ4YAIcpZnBEjCBI+?= =?us-ascii?Q?2Y1v2SP37R60i2WL1V9B1b3cB8Pf9tWCKlBGbh3XDF3vOOIZafmcL4iAUji+?= =?us-ascii?Q?sZV38/aIW5AlYoMHR3A7S8uM7nzoTzZWM59EGP+lEgVVWMRS1E5Gl1d7yb45?= =?us-ascii?Q?YVJofvgJ2+ESK5GqgPaJQOjWcrNk03itjkCiQsvno65e0I9UnjldlQM+OEnA?= =?us-ascii?Q?tdu8uRItaSMh5HtlWEqkwrJE8GgLMarW2jq3s06Rg/HOGsRqGY00kCWngQYE?= =?us-ascii?Q?2eXbYsZYO2vUq+hZ34R3yAE/13yw1/s9GWqb8wuu4o1M6VAP+SGq9vFWs2wo?= =?us-ascii?Q?yz6te5ZP0ijW9idg93W7Jj0+xLUzyIXjDZYL/lIKaZxlZ3ooXBy6XWSW/khx?= =?us-ascii?Q?Oa46ao6ho/yP5kkRuUNVxDilh5gyQKnOkNSFbO8Yab0aB3jdiYb+Zpzk2uMp?= =?us-ascii?Q?IXGONm5g9G+imFDEnSMzzm6bZybPM53c4WUrgT6vJBVU+e1YJAEUhJExKEW8?= =?us-ascii?Q?Bm/9oPn3hmbOPcj3ctez5jHxDzR8/nGtniZ1hVees+GL3jjF1hzYWVqxCh8+?= =?us-ascii?Q?kY3wqiihCpDPPoO0CcKGk0B9pUaohtAQFJ7ruCAV4oUJZe2nPVE+x/meEQL0?= =?us-ascii?Q?XN7anr3VQYvZ+tjoSWDeLvZ1PpzO9C0/NQSLZPzoLnJJ094JFWQxWYmpD94c?= =?us-ascii?Q?MRL0/ERHyyW8eAlmt2lMzaTBPDwJ5XTp0uI007aYbbIimhqqI9OCB+cozMUt?= =?us-ascii?Q?HGrzJLoy/0BpGDInVfgIIo+H0Ldf5mn6iE2OFRFfxNo+H53GzjnUBgYZ9MdP?= =?us-ascii?Q?mtBuZQ=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(376014)(7416014);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: jyY2a/iwL4kNq1g0i2fC/AyJuDJG48g2rK0U/ywV/WXPIpr/q5+gvI9J3oZ5YEv5Cpm1BNfiSB0FO4F+bDXDpiCe94fWVLlgMyox86te25Azlsrwl9b0IO/gRt/4g185Jae+Ep3VeQY/BIZnCinJA1iG9oh2lCZfNdSH3IMmr31koyjPKL4H4hHUri60OM/CwTBHi8N+q1sW/VePXhaVVclclOM2QoC8jv4yKQp1s+2ZFHrYfbNH5nQ0DzX4XRlvEwSIlH9SSKVVtpxFGPKtwFczsBTH5WSb/QgshjQv7oBvsGWFVJghAclU/Uk+1cYa4CtZ2WamuExnLt/B3YHhWc0nRCRaPRfdPHUOnL40V+fVo3H0W5e6aJLXcJoy6BuqUjAoIFzbsvOT9fOFCSKLE1k42rIdi+0bgOF1nXeNLjT+vWa34NGm/1WbV+pzpghw X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Feb 2026 20:43:49.7429 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bcfafbd2-f57f-4489-f925-08de731c3fab X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF0000020A.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5948 Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea Instead of unconditionally setting the page_pool to 0, calculate it from page_shift for MPWQE case. Signed-off-by: Dragos Tatulea Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index aca88fed2ac7..6344dbb6335e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -857,6 +857,7 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params, { void *rqc_wq =3D MLX5_ADDR_OF(rqc, rq_param->rqc, wq); struct mlx5_core_dev *mdev =3D rq->mdev; + u32 pool_order =3D 0; u32 pool_size; int wq_sz; int err; @@ -905,6 +906,7 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params, =20 pool_size =3D rq->mpwqe.pages_per_wqe << mlx5e_mpwqe_get_log_rq_size(mdev, params, rqo); + pool_order =3D rq->mpwqe.page_shift - PAGE_SHIFT; =20 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, rqo) && params->xdp_prog) @@ -960,7 +962,7 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params, /* Create a page_pool and register it with rxq */ struct page_pool_params pp_params =3D { 0 }; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Richard Cochran , , , , , Gal Pressman , Dragos Tatulea , Cosmin Ratiu , Pavel Begunkov , David Wei Subject: [PATCH net-next 10/15] net/mlx5e: Alloc rq drop page based on calculated page_shift Date: Mon, 23 Feb 2026 22:41:50 +0200 Message-ID: <20260223204155.1783580-11-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260223204155.1783580-1-tariqt@nvidia.com> References: <20260223204155.1783580-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001507:EE_|DM4PR12MB6301:EE_ X-MS-Office365-Filtering-Correlation-Id: 9086bbe7-e3d0-413e-c00e-08de731c4448 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|7416014|376014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?ReS06sdHNhHqy8EK/12BeRWdMWbxlmCSe7GFUzyZxYuSR/CzGv0BwevtRcry?= =?us-ascii?Q?uyKLuvPOAdCXJD7LXOZKm7q2u5lTMqGwqpvB6VEAFoNZIZ//yP6SKNuSDmi2?= =?us-ascii?Q?5b+lnGmTqbScgSMgrn+3itQpPAN16zwSclHPiSC6ng4Xk7Jesirccs14NxeD?= =?us-ascii?Q?x7JPX+aHDnMaCcmMX+ZvWFwsjRTauEmLp6fWDGRysniI57OSoaTgWOnzZXpL?= =?us-ascii?Q?RSUwmMo3JHVSxU5I76J+tYeMi9E4DPjfHgbD22fAz0NVEJE9zAF+Ex2VmiRy?= =?us-ascii?Q?1b3Ux3yX4yONCWps0Lyg3+wS2XG7tRC5Mvj+HvuKgpw7+NfopSa4UcMbZUTP?= =?us-ascii?Q?q3roW2mdrm81opyRn9pXFkAb7Erjo0etz9D/6SOBCJznlX1DXvEUShFNKSqq?= =?us-ascii?Q?r1yIj+Q36qRTQCanNeuN3w9wSiHtFl5VE0ux2ap+NtHMFBKPLOjUyD/dhsn4?= =?us-ascii?Q?D3mT2UywxEKPdrbeCPNmH+iVYr/nTR7U/D6YtHa01cW4rTfUzWUSFCR9LCHx?= =?us-ascii?Q?1fE1NFd6dTyubWToprklq/8RCIQUD83zgsmMcvSehS4rAsyY6DLba1zUKICn?= =?us-ascii?Q?Q/BRh09WNaaoorKDg5EC6Pxk739Ccyf9XT7ahE29dLK4lRK2bprXeJt4ENuj?= =?us-ascii?Q?ferEgoFr5OHNYQJYHcTAq7MQ4z6FZT3wYY0jxwQRVEPzTqSp+FW/f6shrQf/?= =?us-ascii?Q?OO7px9oOCUy26zd7cFGfpalt4VB1cjKJDIXZL+6WVwHGbRUvWSvQJCEqNYRS?= =?us-ascii?Q?BS3BmN0CnoNoAV3y2NrIItJ8Db9LaLu2YL66OKRYA1nRciNtM5OxvSiCvFDD?= =?us-ascii?Q?jOh/1kiRhhlV1MNt3n9SsFSu8UpL2M35XFgSPY82Z0tVMQB7sUmFQz+fnCZ6?= =?us-ascii?Q?uSGAyCeDzIZEOkjmBRYMOnJ2Xw3AdNd+OumaTn0YAvCcQul46lM5ckNmZ81m?= =?us-ascii?Q?oSXTUQDbJqgGxcVLcJkKuYCgz/gocGa5ETgbKyWMT4/AS4thNhlDf4WDkHCQ?= =?us-ascii?Q?9mnMQO65i2rYlrsqMPDbG1RQsahbXEFsuh+NSuYN0I2aykbGzPqijL/hQHnt?= =?us-ascii?Q?6c0xdKynNzJNNXMNyQkRpHaeWzU9WRthmeQGr3gzTDfz0THfn31sQRR8M+3r?= =?us-ascii?Q?StthYsQwSKf8NwBW3RUp4UzrlyCfSfzRoIivDYvGyYTEoZCR243vauo4HsD+?= =?us-ascii?Q?TBtyh0KryEro+qVQFCCWN2hznT/fmdmUzckIRBfFeBAkpYMx0SzPm8dy/VTz?= =?us-ascii?Q?IPcHmLi9e/6Rc/oYt3QASBDOK2ABbvH+ojpRlq/R8a+la4y8s1umnDyFFAmS?= =?us-ascii?Q?Ypr3eaf7/apu6yKCQmWKEjaALJH/X882WM6qfLfCGYfNt5skAkHlWGQfW21y?= =?us-ascii?Q?8XJ47stazh0HBBQUZwq58XP8F2y7s7ry6+TMP0zcI+BAjx+yeeFVq09uIOuP?= =?us-ascii?Q?26iPUhp9S24CViO+aY2Pq5VuiiSsP8YciFjJspGWT2t+GWH9JJ7j/2dyACq8?= =?us-ascii?Q?uDvsjkRQyPLotffVUsA/MAn5RCCFd/QBm0qyBMFpTDHkq6kkYfCP0TDuC7b7?= =?us-ascii?Q?BRBTJAvJ598toGhs0KYFVlREY5ZdrwbFR62XSOFBJsHg72Od6ueqgVDsqPCQ?= =?us-ascii?Q?PevrklEXacJDBm+YgWAi6CGTuf3GBjPaxfZUDXLn9f/5zjsTqkmRR2Mz3qIl?= =?us-ascii?Q?ggrW7A=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(7416014)(376014)(36860700013);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: MuIQ2aO4f1rfeaU/ZhmCWP4FcyF7plaUOQ6gRmBeTLHsC8YYd9sVW+wIzjRs+zbFvD5Kvrpf6n7aOhXXYcrrStRGspe6yXHL2F8AytQSGVaLz1144p1tbFDQta4oNwfBgrwac4+46OEqXRLP6dpBcsWn+5Oj1V3FATTBPsQd7od8k20zCFSUap0cC/Ayvdo6HYnWGWwqzRTtarhz0MWtqS8YQEbPRH3seywx8iVDhxybdPazngIpS3xu+wd/AnR0n4VqvPs7BodAjI3hyyzxrkpAvMDV93m46b5Su59h/T+/nLqwFTZS3a/f0Qo6MQGGvomi75dF7HC6QulMrN4asFgH/QD2FhdZA+nQUFMefprK6B3EdZLsj+iReaFN1xo+YhK2dkXf53KoaNSUEf2mStS+aYv449CzEJkUBgTy4y6ptZEQQd9oz26ryT6iu5Qa X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Feb 2026 20:43:57.3994 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9086bbe7-e3d0-413e-c00e-08de731c4448 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001507.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6301 Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea An upcoming patch will allow setting the page order for RX pages to be greater than 0. Make sure that the drop page will also be allocated with the right size when that happens. Take extra care when calculating the drop page size to account for page_shift < PAGE_SHIFT which can happen for xsk. Signed-off-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en_main.c | 27 ++++++++++++------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 6344dbb6335e..2d3d89707246 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -636,14 +636,18 @@ static void mlx5e_rq_timeout_work(struct work_struct = *timeout_work) =20 static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq) { - rq->wqe_overflow.page =3D alloc_page(GFP_KERNEL); + /* xsk can have page_shift < PAGE_SHIFT */ + u16 page_order =3D max_t(s16, rq->mpwqe.page_shift - PAGE_SHIFT, 0); + u32 page_size =3D BIT(PAGE_SHIFT + page_order); + + rq->wqe_overflow.page =3D alloc_pages(GFP_KERNEL, page_order); if (!rq->wqe_overflow.page) return -ENOMEM; =20 rq->wqe_overflow.addr =3D dma_map_page(rq->pdev, rq->wqe_overflow.page, 0, - PAGE_SIZE, rq->buff.map_dir); + page_size, rq->buff.map_dir); if (dma_mapping_error(rq->pdev, rq->wqe_overflow.addr)) { - __free_page(rq->wqe_overflow.page); + __free_pages(rq->wqe_overflow.page, page_order); return -ENOMEM; } return 0; @@ -651,9 +655,12 @@ static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e= _rq *rq) =20 static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq) { - dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE, - rq->buff.map_dir); - __free_page(rq->wqe_overflow.page); + u16 page_order =3D max_t(s16, rq->mpwqe.page_shift - PAGE_SHIFT, 0); + u32 page_size =3D BIT(PAGE_SHIFT + page_order); + + dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, page_size, + rq->buff.map_dir); + __free_pages(rq->wqe_overflow.page, page_order); } =20 static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params = *params, @@ -884,15 +891,15 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params, if (err) goto err_rq_xdp_prog; =20 - err =3D mlx5e_alloc_mpwqe_rq_drop_page(rq); - if (err) - goto err_rq_wq_destroy; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Richard Cochran , , , , , Gal Pressman , Dragos Tatulea , Cosmin Ratiu , Pavel Begunkov , David Wei Subject: [PATCH net-next 11/15] net/mlx5e: RX, Make page frag bias more robust Date: Mon, 23 Feb 2026 22:41:51 +0200 Message-ID: <20260223204155.1783580-12-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260223204155.1783580-1-tariqt@nvidia.com> References: <20260223204155.1783580-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF0000150A:EE_|CH2PR12MB4072:EE_ X-MS-Office365-Filtering-Correlation-Id: ff709922-3c24-4689-f051-08de731c484e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?KTcK8Ng/IyNXvPry5HmyCSyWCPKNeZiH9Yu9FXgYWWQrPNpn7dBiz+WAaDbv?= =?us-ascii?Q?R/ktjIsBTslOxyYp3EA0whuVRyaVgaMt6E2uFjAy6UBXgEX49xoPQ0kxCAOO?= =?us-ascii?Q?HaN4EoW0AYz/OfVVRi4sPkBhGwl5W6g1cjdauI4GhioMfJz+15UWJs6Q4xIS?= =?us-ascii?Q?G0kbQjOf5racg9vvTeTTpGeI2HJWfzBbuLac5qWBAZiWH4DxUuN5FTf6jMGe?= =?us-ascii?Q?TtP+kKS8LgtnDDUvuRGDn9JjOSgTIk1S3Rx0J4jZWHLJnwbBqd7C0cmKigHZ?= =?us-ascii?Q?LHSd79cd2ZFdFv0UIIigLsns8gjssb41P/gSYRVQeO8LF19Du20q3lKtHbD8?= =?us-ascii?Q?FSexe8mKG5R2pTgZ0FJ1AXndC1d3LNzBds9878hcHFl3i2TKOgE0AZkomLD8?= =?us-ascii?Q?Ox+lIpf2Cl6YZQp5PqhKvwc4wBzn7o+2jqpEvka9BIe1olrPRIbxa8bWAphC?= =?us-ascii?Q?jJbw2RZlzH1m5IwPvJJDcDLU5wxO85f0WshRB58kwZKdysS8pHusZbBHlC/D?= =?us-ascii?Q?yPfeCy+LCHK0+8iazUJCKrCkB2rLwFTQj4rGw9Kw/A5oeNQTPHM9YsTYTUIl?= =?us-ascii?Q?0t4GzU0otyhd/KlzAkm76BRtMrTYur8jTALJ15aaDObvQekQW/4V6MYrJSPf?= =?us-ascii?Q?i7weJ6eNhnw8NQDpAsPtnyxDpQRvHmZD6sY7nCUI7EWYpCBs8DEJf/JkppMm?= =?us-ascii?Q?IVpcFq20tTPNzr30AZr8XbCf9f09F19tuwXHFYRQLROFiJmjsYQAR89AssEX?= =?us-ascii?Q?tU6bV8XbIcFyo1y/sfBS81dXOQQn3jF902tbZZxEro8N4ToxF6jp71Mfr34U?= =?us-ascii?Q?e53OgZBrJrylvuA6W450e9faGXgcKALCRnoFKBJbNztGYBJE0tAaT4NQixYb?= =?us-ascii?Q?PyMb1OlIg2Zjggerj6RiLC0xJhXFmAoybKe5ZPtFOXUaVCYD/wUp+vIz59G4?= =?us-ascii?Q?5gwZVTexkYS+btmUEZCpuuznmtdoFcla2kiRP7SgMm60cjuGo+A+QEcu2RA2?= =?us-ascii?Q?3dFWwbEVpPRBWLjNA04o6Afy/z1tj8ZHrqSda2RXFXhLx5mrc0MM4kd9sbel?= =?us-ascii?Q?txb0ZE7M5DY566WMdoc1Nfb1+p2c9JPeZKZm6hX/Myc2GaLFd0mD90aHSw70?= =?us-ascii?Q?0eTpAujk4kbHHfi4S0S+LWCpGboROyH+4p+tUJR6GmlUxH0obuRb2+7PTerC?= =?us-ascii?Q?y6sBj5BHrESKAvNoF4ORcppvfaITj8DOStDhSPjHlS0AtrRBIhkcpFSSYuxs?= =?us-ascii?Q?59ZG435r6NdvQZLgl8AvgHy7A5SKTxPZkXhaXtiFUlT9qwe73+ZzE9nP8mwV?= =?us-ascii?Q?3mQ2nLCyjLwe8leNjCbV0tDGM1Ps823n0/tcrcKn7YnqC4jRy0lgSJuKscZB?= =?us-ascii?Q?XK/2eTTsyrnszK+W6YzNI4aKTjgPTWERsfT7JIaWbVPYADTd+r9yQXNd53jo?= =?us-ascii?Q?erIa4LYJWHcAFD/U2LITd0foBmilArdApxTMWxrL4xzZfGfOMabklT/8YcHp?= =?us-ascii?Q?ckGtgV/puCe4XT8/4dAtGV0J+zUDzYe9on1oU41aMmWuCEnxQtbJQwYGz8x+?= =?us-ascii?Q?h1ma0DITTDRNd0CgxH/s+shK0HVczpuAr09/n0FcEDABozUuYpIRZ6ac2JcV?= =?us-ascii?Q?gZ3SURDWlLuDTbwUIDXoDW0G4r4n+FsL5IwHQIwYAHzAZZGpYm9DBaT/WF3q?= =?us-ascii?Q?txmnew=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: DI8/vKUwetV8B/ALP+18BeT38vxF2dmNdiHxhSIUyV1nyzQhCdvEF3aOCWNMTfr52EBjNAP5A2dmDrMErgggMSx3hslHnwMPmVk1rvs6xkIag3luBezojTIFAfhBCr+WJHD2ucu7+BGRtrRYJsTkB16nKvZrtFwS2zZq8zUrjRP0C/z6IY1YCyUHpp9S4KCGRFPh8NB+jju1MHjtsmQ4b1OF6DvObzzUZjAmdJOBem9D7EhQm+/g37ujPvrqQAEZyNJe9AZm/4Pxssa1W8OEkZXysK4lrlUTpbHdaJqx1Ln1B0TO26xvuWOr/Nz5LdckxBWTqsoghW8VDbQ3ZlA6AGD1bEppiQtrk/5oae16ZxMQwhN8NfyQYlEGQBqiZdQvSz1lc4qrjFDmfH51G4U5NAcR9ZPhyxBklhWljKg85sTDQs5yEr5quf23riUq/jcq X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Feb 2026 20:44:04.1228 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ff709922-3c24-4689-f051-08de731c484e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF0000150A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4072 Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea The formula uses the system page size but does not account for high order pages. One way to fix this would be to adapt the formula to take into account the pool order. This would require calculating it for every allocation or adding an additional rq struct member to hold the bias max. However, the above is not really needed as the driver doesn't check the bias value. It has other means to calculate the expected number of fragments based on context. This patch simply sets the value to the max possible value. A sanity check is added during queue init phase to avoid having really big pages from using more fragments than the type can fit. Signed-off-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 1 + drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 6 ++++++ drivers/net/ethernet/mellanox/mlx5/core/en_rx.c | 2 -- 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index 5181d6ab39ae..c7ac6ebe8290 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -80,6 +80,7 @@ struct page_pool; #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \ SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) =20 +#define MLX5E_PAGECNT_BIAS_MAX U16_MAX #define MLX5E_RX_MAX_HEAD (256) #define MLX5E_SHAMPO_LOG_HEADER_ENTRY_SIZE (8) #define MLX5E_SHAMPO_WQ_HEADER_PER_PAGE \ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 2d3d89707246..cf977273f753 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -969,6 +969,12 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params, /* Create a page_pool and register it with rxq */ struct page_pool_params pp_params =3D { 0 }; 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A subsequent patch will add support for high order pages in zero-copy mode. Signed-off-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en_main.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index cf977273f753..336e384c143a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -5572,6 +5572,22 @@ struct mlx5_qmgmt_data { struct mlx5e_channel *c; }; =20 +static void mlx5e_queue_default_qcfg(struct net_device *dev, + struct netdev_queue_config *qcfg) +{ + qcfg->rx_page_size =3D PAGE_SIZE; +} + +static int mlx5e_queue_validate_qcfg(struct net_device *dev, + struct netdev_queue_config *qcfg, + struct netlink_ext_ack *extack) +{ + if (qcfg->rx_page_size !=3D PAGE_SIZE) + return -EINVAL; + + return 0; +} + static int mlx5e_queue_mem_alloc(struct net_device *dev, struct netdev_queue_config *qcfg, void *newq, int queue_index) @@ -5682,6 +5698,9 @@ static const struct netdev_queue_mgmt_ops mlx5e_queue= _mgmt_ops =3D { .ndo_queue_start =3D mlx5e_queue_start, .ndo_queue_stop =3D mlx5e_queue_stop, .ndo_queue_get_dma_dev =3D mlx5e_queue_get_dma_dev, + .ndo_default_qcfg =3D mlx5e_queue_default_qcfg, + .ndo_validate_qcfg =3D mlx5e_queue_validate_qcfg, + .supported_params =3D QCFG_RX_PAGE_SIZE, }; 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Mon, 23 Feb 2026 12:43:56 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Richard Cochran , , , , , Gal Pressman , Dragos Tatulea , Cosmin Ratiu , Pavel Begunkov , David Wei Subject: [PATCH net-next 13/15] net/mlx5e: Pass netdev queue config to param calculations Date: Mon, 23 Feb 2026 22:41:53 +0200 Message-ID: <20260223204155.1783580-14-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260223204155.1783580-1-tariqt@nvidia.com> References: <20260223204155.1783580-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A0FE:EE_|LV9PR12MB9806:EE_ X-MS-Office365-Filtering-Correlation-Id: df7fd115-5075-4e28-7728-08de731c5170 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|7416014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?zmKtrkmnDkn5lF7iX1BH4GjXann8WztAbFVC8EDlFcocl6iBanbj5O3JPooX?= =?us-ascii?Q?xXr/T8h6t1JGCkFBpC/YbDosOjHao+pLxrQ+aqK0sYPiYCeNXlmb0IZ+mj2O?= =?us-ascii?Q?xC6/TxI4UcOO82ntOVd7RZcuvqB9X9OhAsTv2/WkNs6TGZ0aVfR9iYBlm5i3?= =?us-ascii?Q?gv7P70sTmpfxCLn22HWUqPwRdpbHi0lJXwaUiIM7uoXEr7RFOYEmDwyXm0yh?= =?us-ascii?Q?dbJoFCJvngZe9c4e1Jy0FOWY1HmmLxNV46Pnoc+iVgOfpX0V1xHsPewUA5zN?= =?us-ascii?Q?slolqn0+nt6Eaajw1UKsIXzMFBI3DTUBXi6nQ5mKqMFI+Kfnpl5+/zoL4o4B?= =?us-ascii?Q?+rTpsOxkZACEOgOMArbUi2rZsq6faSfxVR38g2QBuNYmqIPUaGxzWGK12zg8?= =?us-ascii?Q?3ADkGkLFPBzqhsWPiaxCsTexHO85ATwApPgT8UPFZ61H3bd9wiS3LauZ8t/A?= =?us-ascii?Q?+VYUF3+QIEliv++z4IcTDngWiz4omEJRmX0wpCOyC2OS09M+AFFbuQ9v+v7r?= =?us-ascii?Q?+EOzbizFEv6QbZxoKcGTjWkp7z58Zz3ZFvmjJdYARXH/dWA1IvYnTnhuOLj+?= =?us-ascii?Q?amXeHIZOJIDrQk9bPwojZXaL3M3T1VyusDEA7lvcUSZMDkJdZNYE1eFqQMEe?= =?us-ascii?Q?3yFCrhlUrFocSzljkHFQ0Z0IEPShiRNp1JhB5LbSmYW214j6bE2F9BrTgHDR?= =?us-ascii?Q?BLj16koGpIOGTpvqXKRU1aFUwRNN7gRvCUYHSDBiMquTiAkFQPSM49cSNR6Z?= =?us-ascii?Q?geyY1kUDbO+0WVcmbg+rz3IEhuh4FQ3ML4e9vVH2cgPJ5mAVj+unR67xpB/T?= =?us-ascii?Q?gV1HpCB5VDlbn135cmfnLupPjd9O/4Y2R9WUAbETHyKR8dXMkJjyol9yKdFY?= =?us-ascii?Q?8R1mz3OE8FxyXwLKvVA1oQqm2AK7czIP+0I8UkRph6PZQKYJ7TOqNZ+z/det?= =?us-ascii?Q?nqRDhabyBwxTpZQTwHlvYrIUbYdiwulxOKP++8yDGd37wGB3lLoWF45QaqW0?= =?us-ascii?Q?hf+GJyxGizYuLmap5s6QP5ypiQ29JosfN94/0NRxsJsdyqFOPFe00nU3Qeyp?= =?us-ascii?Q?6x0bwI0nNkGXkBidptSp6Tk7Zo/AmHHTCpWYRzO8VpGEHcHzjq9dwgsUvf6Z?= =?us-ascii?Q?3/ZOowAIXlgwAvfBiVrsEZ/bxDMoIi1OApDqPqv/0ogMVd/m7gUXAajFr1LS?= =?us-ascii?Q?rALxWdta/LeaZBPWsTWLpUwSyZKqdhgFPqrmv9bZRstQy5ItE7z1WnimRzXa?= =?us-ascii?Q?ip6cuJZzQc/LP2HobxG2Pc4onIlp8MSMbW1N/eNziN/32/bC5KVHfKiNaDZH?= =?us-ascii?Q?C1NB1Ewx9/+HE+jVQoHBQb56GMvAgnjkaqHbqx/0RqMRqD1xsZnItk7LD3uS?= =?us-ascii?Q?U2od1q+eyTiWLDOBHkYbtO98P5iLOPtuGJW8gdNHaJDpjcjd4ZOqvAPUut6Y?= =?us-ascii?Q?AuKE5ywIHjpUK+efWkuvcYGMVq0gT0d3+j5znccS+i9Cnb2H0nHjecmGMlg9?= =?us-ascii?Q?K+19REipTW9b4D71EqNqo8ohuOvndcaMtDiUT7obkTb1T3qwXW6cTyt1rHWx?= =?us-ascii?Q?VFtCMl7JXLVLdLIBV+XNfglHeKeUT+7F6Dy2AhyHzzIfvXSPiklkCjZoYkVV?= =?us-ascii?Q?juvyx9yr9rt+X7x3cBaVO3MxjJGGlVdPQWs0KWS6y7z1KhSBGU3C03qVDxJa?= =?us-ascii?Q?dISC4Q=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(7416014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: l+CyuIQJ8cvBQRreE6gSdoATPkSTg6GNethE+SDuluthEmlvWzVNEx+L2Wds6FH2og35EbvNfzmoMN1cE1sMlJy3+vtBxNR1qy+GDEkHiYe4/9WWcLO6C2iM+dlPM/Yf7EecaWZsIzUj8cnDiDbo5lOLW/wFEUJBdJgzZ8TsT3kOq2/0nTLT1W4/uvJWlJuKIgoMk3byWp2SX4LYTo3T1ADL/OzXewy3I2g2YY1R2qMNGircq8a/bI+T1kQKevR45Oxe20mO42OKQGQkb4onpunamHzBDe16n1dAvCTbfpT2zycVzR/ppc56Q9NuVrfPL13z1gzfphzy31s00vZta3KQ2vlVYTSFwQptgiyWC0tQQL1heqx4IVANTljaSxm6NYRHDgv9ZpdbY7nkE2jaBsFg+pSiuqQ3fa0GUQs9BQxc4Ux0fDkRVtSMY1XPmdi5 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Feb 2026 20:44:19.3925 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: df7fd115-5075-4e28-7728-08de731c5170 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV9PR12MB9806 Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea If set, take rx_page_size into consideration when calculating the page shift in Multi Packet WQE mode. The queue config is saved in the mlx5e_rq_opt_param struct which is added to the mlx5e_channel_param struct. Now the configuration can be read from the struct instead of adding it as an argument to all call sites. For consistency, the queue config is assigned in mlx5e_build_channel_param(). The queue configuration is read only from queue management ops as that's the only place where it is currently useful. Furthermore, netdev_queue_config() expects netdev->queue_mgmt_ops to be set which is not always the case (representor netdevs). Signed-off-by: Dragos Tatulea Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/en/params.c | 14 ++++++++++++-- .../ethernet/mellanox/mlx5/core/en/params.h | 2 ++ .../net/ethernet/mellanox/mlx5/core/en_main.c | 19 ++++++++++++------- 3 files changed, 26 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c b/drivers/= net/ethernet/mellanox/mlx5/core/en/params.c index 97f5d1c2adea..304b46ecc8df 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c @@ -10,6 +10,7 @@ #include #include #include +#include =20 #define MLX5_MPWRQ_MAX_LOG_WQE_SZ 18 #define MLX5_REP_MPWRQ_MAX_LOG_WQE_SZ 17 @@ -24,11 +25,17 @@ static u8 mlx5e_mpwrq_min_page_shift(struct mlx5_core_d= ev *mdev) u8 mlx5e_mpwrq_page_shift(struct mlx5_core_dev *mdev, struct mlx5e_rq_opt_param *rqo) { + struct netdev_queue_config *qcfg =3D rqo ? rqo->qcfg : NULL; struct mlx5e_xsk_param *xsk =3D mlx5e_rqo_xsk_param(rqo); u8 min_page_shift =3D mlx5e_mpwrq_min_page_shift(mdev); u8 req_page_shift; =20 - req_page_shift =3D xsk ? order_base_2(xsk->chunk_size) : PAGE_SHIFT; + if (xsk) + req_page_shift =3D order_base_2(xsk->chunk_size); + else if (qcfg && qcfg->rx_page_size) + req_page_shift =3D order_base_2(qcfg->rx_page_size); + else + req_page_shift =3D PAGE_SHIFT; =20 /* Regular RQ uses order-0 pages, the NIC must be able to map them. */ if (WARN_ON_ONCE(!xsk && req_page_shift < min_page_shift)) @@ -1283,12 +1290,15 @@ void mlx5e_build_xdpsq_param(struct mlx5_core_dev *= mdev, =20 int mlx5e_build_channel_param(struct mlx5_core_dev *mdev, struct mlx5e_params *params, + struct netdev_queue_config *qcfg, struct mlx5e_channel_param *cparam) { u8 icosq_log_wq_sz, async_icosq_log_wq_sz; int err; =20 - err =3D mlx5e_build_rq_param(mdev, params, NULL, &cparam->rq); + cparam->rq_opt.qcfg =3D qcfg; + + err =3D mlx5e_build_rq_param(mdev, params, &cparam->rq_opt, &cparam->rq); if (err) return err; =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.h b/drivers/= net/ethernet/mellanox/mlx5/core/en/params.h index 4bce769d48ed..5b6d528bce9b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.h @@ -14,6 +14,7 @@ struct mlx5e_xsk_param { =20 struct mlx5e_rq_opt_param { struct mlx5e_xsk_param *xsk; + struct netdev_queue_config *qcfg; }; =20 struct mlx5e_cq_param { @@ -143,6 +144,7 @@ void mlx5e_build_xdpsq_param(struct mlx5_core_dev *mdev, struct mlx5e_sq_param *param); int mlx5e_build_channel_param(struct mlx5_core_dev *mdev, struct mlx5e_params *params, + struct netdev_queue_config *qcfg, struct mlx5e_channel_param *cparam); =20 void mlx5e_build_xsk_channel_param(struct mlx5_core_dev *mdev, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 336e384c143a..59e38e7e067e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -2524,8 +2524,10 @@ static int mlx5e_set_tx_maxrate(struct net_device *d= ev, int index, u32 rate) return err; } =20 -static int mlx5e_open_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params = *params, - struct mlx5e_rq_param *rq_param) +static int mlx5e_open_rxq_rq(struct mlx5e_channel *c, + struct mlx5e_params *params, + struct mlx5e_rq_param *rq_param, + struct mlx5e_rq_opt_param *rqo) { u16 q_counter =3D c->priv->q_counter[c->sd_ix]; int err; @@ -2534,7 +2536,7 @@ static int mlx5e_open_rxq_rq(struct mlx5e_channel *c,= struct mlx5e_params *param if (err) return err; =20 - return mlx5e_open_rq(params, rq_param, NULL, cpu_to_node(c->cpu), + return mlx5e_open_rq(params, rq_param, rqo, cpu_to_node(c->cpu), q_counter, &c->rq); } =20 @@ -2638,7 +2640,7 @@ static int mlx5e_open_queues(struct mlx5e_channel *c, if (err) goto err_close_icosq; =20 - err =3D mlx5e_open_rxq_rq(c, params, &cparam->rq); + err =3D mlx5e_open_rxq_rq(c, params, &cparam->rq, &cparam->rq_opt); if (err) goto err_close_sqs; =20 @@ -2783,6 +2785,7 @@ static void mlx5e_channel_pick_doorbell(struct mlx5e_= channel *c) =20 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, struct mlx5e_params *params, + struct netdev_queue_config *qcfg, struct xsk_buff_pool *xsk_pool, struct mlx5e_channel **cp) { @@ -2816,7 +2819,7 @@ static int mlx5e_open_channel(struct mlx5e_priv *priv= , int ix, goto err_free; } =20 - err =3D mlx5e_build_channel_param(mdev, params, cparam); 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Signed-off-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en/params.c | 12 ++++++++++++ drivers/net/ethernet/mellanox/mlx5/core/en/params.h | 1 + 2 files changed, 13 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c b/drivers/= net/ethernet/mellanox/mlx5/core/en/params.c index 304b46ecc8df..26bb31c56e45 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c @@ -501,6 +501,18 @@ u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev, return 0; } =20 +u32 mlx5e_mpwrq_max_page_size(struct mlx5_core_dev *mdev) +{ + if (mlx5_core_is_ecpf(mdev)) + return PAGE_SIZE; + + /* Two MTTs are needed to form an octword. Driver is using a + * single page per MTT for simplicity. Hence the limit of having + * at least 2 pages per WQE. + */ + return BIT(MLX5_MPWRQ_MAX_LOG_WQE_SZ - 1); +} + u16 mlx5e_calc_sq_stop_room(struct mlx5_core_dev *mdev, struct mlx5e_param= s *params) { bool is_mpwqe =3D MLX5E_GET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.h b/drivers/= net/ethernet/mellanox/mlx5/core/en/params.h index 5b6d528bce9b..9b1a2aed17c3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.h @@ -121,6 +121,7 @@ u8 mlx5e_mpwqe_get_min_wqe_bulk(unsigned int wq_sz); u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev, struct mlx5e_params *params, struct mlx5e_rq_opt_param *rqo); +u32 mlx5e_mpwrq_max_page_size(struct mlx5_core_dev *mdev); =20 /* Build queue parameters */ =20 --=20 2.44.0 From nobody Fri Apr 17 09:37:52 2026 Received: from DM1PR04CU001.outbound.protection.outlook.com (mail-centralusazon11010036.outbound.protection.outlook.com [52.101.61.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6EC3D37AA68; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Richard Cochran , , , , , Gal Pressman , Dragos Tatulea , Cosmin Ratiu , Pavel Begunkov , David Wei Subject: [PATCH net-next 15/15] net/mlx5e: SHAMPO, Allow high order pages in zerocopy mode Date: Mon, 23 Feb 2026 22:41:55 +0200 Message-ID: <20260223204155.1783580-16-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260223204155.1783580-1-tariqt@nvidia.com> References: <20260223204155.1783580-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A0FC:EE_|SN7PR12MB6789:EE_ X-MS-Office365-Filtering-Correlation-Id: 4d1deeb7-6a7d-41f0-4bd4-08de731c5883 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|7416014|376014|13003099007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?oEOM0XJC1xKJZUMn4uMqUxMQ81LVZnaunGA/3CymgPXfFxkei7GpeW7709mS?= =?us-ascii?Q?iUlww5pwoaHKgNZLyIwSVQXvmJupx1kZ2vEqA1SaejEe8srXyxPwfOewJPyn?= =?us-ascii?Q?LKX/RaYYHzKwn65Sy1RUZm6Pmg6FmOeXCBS7cwwXGHusroeG666577xae32Y?= =?us-ascii?Q?gRGLcWaLYrCzsphpn84q8gk1n84r49D26B8fsRj83kuR6gI8a28sPAJvZG0i?= =?us-ascii?Q?xmd3jQvu6zSuev8QhDL8s6SbUAcCVlj1njqa3/Q8CNUfpLnwlIYpd+jQgreK?= =?us-ascii?Q?1snOCiUt81H61SnoZTH2Ps2HotnCCM8CfxHbcW6TNhvEkvArYAO1POWDfgky?= =?us-ascii?Q?fjll+3MLfiYvSWmQhxMOg0I0WDkH3frzz1aUkZZBALsQQouya8mEvVhq/BSx?= =?us-ascii?Q?Ykgf/qHotpU6R1WgY6k7z0hXT7J50yodirpLwD1gWU/YqfHdPAvPeCKiPX5b?= =?us-ascii?Q?XmK2hGKVZtlNm9Cmfnz/blDf5/NLECNk+ibQmqhPZiQ6q3+RYERknS0PKnHJ?= =?us-ascii?Q?IP4cOX7GFhtriR1Bsd8NYnoTGR45ynay6ZoicC6w/MCCly8HVxsIl+rWcHCn?= =?us-ascii?Q?nJcrPIn1cS4Ie7+XD+2CRyAQ6qQjMvCLMBn6X42A402f/y334uXf5dvdHrfW?= =?us-ascii?Q?uN3DUCUhTbatftE4OSc0UYVx0zRF6LNSp+u6kU2RHMdwmXhnqRLHHmbmt7jP?= =?us-ascii?Q?uPH4z+Y4B+jkUMA4QXtEwRdWCi4Y/1cYPK7PmtKE5NF0iVklZPg67PoyOQPu?= =?us-ascii?Q?2l7BR8f0oL/Qkh6IZpgUg2TsjzZ9GLwdCg5WflYDhaP16PXr+c+/NpwsAnmT?= =?us-ascii?Q?x4T2RMXw874NI7DFnZf1GXTDDCBnH3L7x+Jzs+XvDCdlj+Bs6seEQ6+jSwfW?= =?us-ascii?Q?7YTdXsrhnPVuk980KwnVPlcvoqtS8X58wvWbdlIkl+CQvfcr0MJMAeQkcgDC?= =?us-ascii?Q?NbZ1diddZeikZ4hzzzRCZ4hV0FIy3XeWhdL71HoSgiBqykgQ06nfGVDGcQlh?= =?us-ascii?Q?zexpM8ioOUfkIYB14MHHiuAdY9ST5cQ891ivV/YHDzTG0TI6+s46IEu6nLPU?= =?us-ascii?Q?u70Jf6EHFmHL7/NUwbUaFleN6Rcn9n4yspTU+aIhZhLLi0OzqiSaRc1GxDgm?= =?us-ascii?Q?ORBnpddjjLORT4LKIdlMl+8pbCECYPDrU4h+dyXsuYmb/XVr34jvLDrHCg6m?= =?us-ascii?Q?MLNdR/+czJRKVSiht+i/QS+z2Ih4cG1qeQk2C9j/UUdqlDBgCDKbPmh55/lO?= =?us-ascii?Q?uwds27lArmt2owLdLzxVG7Z3rKupbjWuftLHFGA3D06XBa7BURO0DNmvoSqy?= =?us-ascii?Q?IRgyy8wg34FuORTDztkW5FT1F1IoPtr6imnBZq6NmlsZIqtxOUIg6u8JhMVj?= =?us-ascii?Q?zzp8nSHApMMRDoAIuuW5WhjD1IVGipB9JUVzBRNKTJnm/FEwvz7CyFV/eV8h?= =?us-ascii?Q?U47R1hLh7OlHiI8gQ/r7Ebxmh6ybmwnMbwx+lRWDBO2By5oWgraCqWrsPHjI?= =?us-ascii?Q?BmtcwvJN2qb1y8IOj/QADKEUL7iuBcpAlKfqFa20CSLvGOdtpIFHCMdGBSgI?= =?us-ascii?Q?KU030/c2QqShal4+o1K/eMVPOVnSwUkOIOTKyJJTGZRUtBxJJYkDx2+vA3mT?= =?us-ascii?Q?apC/Xfo42pjiscUKBUxmp5EaCpcEZ3Esaleo9DnMK7H65zIyY7JH+pDRJY+3?= =?us-ascii?Q?X/aSFQ=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(7416014)(376014)(13003099007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: DfThcPOQmAIc8+fPXaeoAOinEAtmWFu5siDTHgYgTpUQ2tCxUUI4uHqAieMyldM4LdNe2E6ZvrYb9HFOQDkkRwQVimS5bP3w3dO7rOLyDauUdC1vN6Sb70jgV1DiME/aUPC31tCnXOSpRKz49nhxFq0TNNrTP1+DVXtbtH+/xF4gT5kII5DIHSb0ijMFsWkUa9ey0rGHFrEBg14kvZOiOdjf/lTVguV4iD45bFx/HiLoJkFTPk4EzsjXLNoVTn8AB/QVIKNtRDBs+ObnQ392iKCDDeakMXaYxjq5RG8EF1MiSuyLba9IHSRt0ojU++2UqSzO/599ak2OR+27tKHQSokGcZjkKZqAHhW6cNZtjCGNkQNp59VeTvirJt5Pu3BuL3iJapiXNby/Jl7t5w6YD9U8U+kX2EDRFCnGPW09ieBsnc8It74PFlhtYpKpnJMN X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Feb 2026 20:44:31.2577 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4d1deeb7-6a7d-41f0-4bd4-08de731c5883 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FC.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6789 Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea Allow high order pages only when SHAMPO mode is enabled (hw-gro) and the queue is used for zerocopy (has memory provider ops set). The limit is 128K and it was chosen for the following reasons: - 256K size requires a special case during MTT calculation to split the page in two. That's because two MTTs are needed to form an octword. - Higher sizes require increasing WQE size and/or reducing the number of WQEs. - Having the RQ lined with too few large pages can lead to refill issues. Results show an increase in BW and a decrease in CPU usage. The benchmark was done with the zcrx samples from liburing [0]. rx_buf_len=3D4K, oncpu [1]: packets=3D3358832 (MB=3D820027), rps=3D55794 (MB/s=3D13621) Average: CPU %usr %nice %sys %iowait %irq %soft %steal %= guest %gnice %idle Average: 9 1.56 0.00 18.09 13.42 0.00 66.80 0.00 = 0.00 0.00 0.12 rx_buf_len=3D128K, oncpu [2]: packets=3D3781376 (MB=3D923187), rps=3D62813 (MB/s=3D15335) Average: CPU %usr %nice %sys %iowait %irq %soft %steal %= guest %gnice %idle Average: 9 0.33 0.00 7.61 18.86 0.00 73.08 0.00 = 0.00 0.00 0.12 rx_buf_len=3D4K, offcpu [3]: packets=3D3460368 (MB=3D844816), rps=3D57481 (MB/s=3D14033) Average: CPU %usr %nice %sys %iowait %irq %soft %steal %= guest %gnice %idle Average: 9 0.00 0.00 0.26 0.00 0.00 92.63 0.00 = 0.00 0.00 7.11 Average: 11 3.04 0.00 68.09 28.87 0.00 0.00 0.00 = 0.00 0.00 0.00 rx_buf_len=3D128K, offcpu [4]: packets=3D4119840 (MB=3D1005820), rps=3D68435 (MB/s=3D16707) Average: CPU %usr %nice %sys %iowait %irq %soft %steal %= guest %gnice %idle Average: 9 0.00 0.00 0.87 0.00 0.00 63.77 0.00 = 0.00 0.00 35.36 Average: 11 1.96 0.00 43.68 54.37 0.00 0.00 0.00 = 0.00 0.00 0.00 [0] https://github.com/isilence/liburing/tree/zcrx/rx-buf-len [1] commands: $> taskset -c 9 ./zcrx 6 -i eth2 -q 9 -A 1 -B 4096 -S 33554432 $> ./send-zerocopy tcp -6 -D 2001:db8::1 -t 60 -C 0 -l 1 -b 1 -n 1 -z 1 -= d -s 256000 [2] commands: $> taskset -c 9 ./zcrx 6 -i eth2 -q 9 -A 1 -B 131072 -S 33554432 $> ./send-zerocopy tcp -6 -D 2001:db8::1 -t 60 -C 0 -l 1 -b 1 -n 1 -z 1 -= d -s 256000 [3] commands: $> taskset -c 11 ./zcrx 6 -i eth2 -q 9 -A 1 -B 4096 -S 33554432 $> ./send-zerocopy tcp -6 -D 2001:db8::1 -t 60 -C 0 -l 1 -b 1 -n 1 -z 1 -= d -s 256000 [4] commands: $> taskset -c 11 ./zcrx 6 -i eth2 -q 9 -A 1 -B 131072 -S 33554432 $> ./send-zerocopy tcp -6 -D 2001:db8::1 -t 60 -C 0 -l 1 -b 1 -n 1 -z 1 -= d -s 256000 Signed-off-by: Dragos Tatulea Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en_main.c | 36 ++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 59e38e7e067e..67dc38981101 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -5586,12 +5586,40 @@ static int mlx5e_queue_validate_qcfg(struct net_dev= ice *dev, struct netdev_queue_config *qcfg, struct netlink_ext_ack *extack) { - if (qcfg->rx_page_size !=3D PAGE_SIZE) + struct mlx5e_priv *priv =3D netdev_priv(dev); + struct mlx5_core_dev *mdev =3D priv->mdev; + u32 max; + + if (!is_power_of_2(qcfg->rx_page_size)) { + netdev_err(priv->netdev, "rx_page_size not power of 2: %u", + qcfg->rx_page_size); return -EINVAL; + } + + max =3D mlx5e_mpwrq_max_page_size(mdev); + if (qcfg->rx_page_size < PAGE_SIZE || qcfg->rx_page_size > max) { + netdev_err(priv->netdev, + "Selected rx_page_size %u not in supported range [%lu, %u]\n", + qcfg->rx_page_size, PAGE_SIZE, max); + return -ERANGE; + } =20 return 0; } =20 +static bool mlx5e_queue_validate_page_size(struct net_device *dev, + struct netdev_queue_config *qcfg, + int queue_index) +{ + if (qcfg->rx_page_size =3D=3D PAGE_SIZE) + return true; + + if (!netif_rxq_has_unreadable_mp(dev, queue_index)) + return false; + + return true; +} + static int mlx5e_queue_mem_alloc(struct net_device *dev, struct netdev_queue_config *qcfg, void *newq, int queue_index) @@ -5623,6 +5651,12 @@ static int mlx5e_queue_mem_alloc(struct net_device *= dev, goto unlock; } =20 + if (!mlx5e_queue_validate_page_size(dev, qcfg, queue_index)) { + netdev_err(priv->netdev, "High order pages are supported only in Zero-Co= py mode\n"); + err =3D -EINVAL; + goto unlock; + } + err =3D mlx5e_open_channel(priv, queue_index, ¶ms, qcfg, NULL, &new->c); unlock: --=20 2.44.0