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Mon, 23 Feb 2026 11:22:41 -0500 (EST) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 61NGMeQa031804 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 23 Feb 2026 11:22:40 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Mon, 23 Feb 2026 11:22:40 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Mon, 23 Feb 2026 11:22:40 -0500 Received: from HYB-b1tGeUj4GP1.ad.analog.com (HYB-b1tGeUj4GP1.ad.analog.com [10.48.65.247]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 61NGMJUc015342; Mon, 23 Feb 2026 11:22:31 -0500 From: Antoniu Miclaus To: Lars-Peter Clausen , Michael Hennerich , Antoniu Miclaus , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan , Mark Brown , Sebastian Reichel , , , , Subject: [PATCH v4 1/5] spi: allow ancillary devices to share parent's chip selects Date: Mon, 23 Feb 2026 18:21:00 +0200 Message-ID: <20260223162110.156746-2-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260223162110.156746-1-antoniu.miclaus@analog.com> References: <20260223162110.156746-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: 9ZNKzmb3SmSWDW5ruQZh0Ngdw9im299n X-Authority-Analysis: v=2.4 cv=RPK+3oi+ c=1 sm=1 tr=0 ts=699c7ed1 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=N--XFCr6TIEc_64PeIT2:22 a=gAnH3GRIAAAA:8 a=IpJZQVW2AAAA:8 a=Brvx10Sw2QwnUvu3_sIA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=IawgGOuG5U0WyFbmm1f5:22 X-Proofpoint-ORIG-GUID: 9ZNKzmb3SmSWDW5ruQZh0Ngdw9im299n X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjIzMDE0MCBTYWx0ZWRfXxHxtdFnD0ODV SKPYc8wwCD4WiLbrB8t91ICK0vllt1OiSywjBOU34xpUrIoGsC/H3diMj4I/y1VAilykuoOYkva Z/GAmyaa1Ji+Yz2tmfsH6IZE8YxuMo5HoIAZGEbR+YGlG+lXqNGksz6Q4wsxo/b6roS0FChrJaQ lHPKTU3TX/5DsHjGmORvQiedP2rlRDKwQUhhJdY0emTukAhIGvHlBk4rIZHeLm8rEbwITm9gaT5 dl5IBFLwR5KQhbYHB8XpXfXR8kMFrT8ywr00K4j7C15MWEvCeKuSm0T5usuDiVgLX/69jfG4jGX 89kXz3hVX6p0RzoDCzkcJ0BKSizdaxdWkMjG2p5MupgjMOsGwmEju6t1RAiuTsAtBJOEJpjo41N CaMioIZzPA8wCOSzKiatCCAzXL/LGPl6Z7AcFpyk6CjSSVZBhXw8Zf0K9r4X7X7+WGhvCQ6sOHP f8H1aN+6gxgx342NeaA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-23_03,2026-02-23_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 impostorscore=0 adultscore=0 priorityscore=1501 spamscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602230140 When registering an ancillary SPI device, the current code flags a chip select conflict with the parent device. This happens because the ancillary device intentionally uses one of the parent's chip selects, but __spi_add_device() checks against all existing devices including the parent. Allow this by passing the parent device pointer to __spi_add_device() and skipping the conflict check when the existing device is the parent. Fixes: 0c79378c0199 ("spi: add ancillary device support") Acked-by: Nuno S=C3=A1 Reviewed-by: David Lechner Signed-off-by: Antoniu Miclaus --- Changes in v4: - Add Fixes tag - Add Acked-by from Nuno S=C3=A1 drivers/spi/spi.c | 29 +++++++++++++++++++++++------ 1 file changed, 23 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index e25df9990f82..693bdcc5a12a 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -641,12 +641,26 @@ static inline int spi_dev_check_cs(struct device *dev, return 0; } =20 +struct spi_dev_check_info { + struct spi_device *new_spi; + struct spi_device *parent; /* set for ancillary devices */ +}; + static int spi_dev_check(struct device *dev, void *data) { struct spi_device *spi =3D to_spi_device(dev); - struct spi_device *new_spi =3D data; + struct spi_dev_check_info *info =3D data; + struct spi_device *new_spi =3D info->new_spi; int status, idx; =20 + /* + * When registering an ancillary device, skip checking against the + * parent device since the ancillary is intentionally using one of + * the parent's chip selects. + */ + if (spi =3D=3D info->parent) + return 0; + if (spi->controller =3D=3D new_spi->controller) { for (idx =3D 0; idx < spi->num_chipselect; idx++) { status =3D spi_dev_check_cs(dev, spi, idx, new_spi, 0); @@ -663,10 +677,11 @@ static void spi_cleanup(struct spi_device *spi) spi->controller->cleanup(spi); } =20 -static int __spi_add_device(struct spi_device *spi) +static int __spi_add_device(struct spi_device *spi, struct spi_device *par= ent) { struct spi_controller *ctlr =3D spi->controller; struct device *dev =3D ctlr->dev.parent; + struct spi_dev_check_info check_info; int status, idx; u8 cs; =20 @@ -710,7 +725,9 @@ static int __spi_add_device(struct spi_device *spi) * chipselect **BEFORE** we call setup(), else we'll trash * its configuration. */ - status =3D bus_for_each_dev(&spi_bus_type, NULL, spi, spi_dev_check); + check_info.new_spi =3D spi; + check_info.parent =3D parent; + status =3D bus_for_each_dev(&spi_bus_type, NULL, &check_info, spi_dev_che= ck); if (status) return status; =20 @@ -772,7 +789,7 @@ int spi_add_device(struct spi_device *spi) spi_dev_set_name(spi); =20 mutex_lock(&ctlr->add_lock); - status =3D __spi_add_device(spi); + status =3D __spi_add_device(spi, NULL); mutex_unlock(&ctlr->add_lock); return status; } @@ -2580,8 +2597,8 @@ struct spi_device *spi_new_ancillary_device(struct sp= i_device *spi, =20 WARN_ON(!mutex_is_locked(&ctlr->add_lock)); =20 - /* Register the new device */ - rc =3D __spi_add_device(ancillary); + /* Register the new device, passing the parent to skip CS conflict check = */ + rc =3D __spi_add_device(ancillary, spi); if (rc) { dev_err(&spi->dev, "failed to register ancillary device\n"); goto err_out; --=20 2.43.0 From nobody Sun Apr 5 18:21:02 2026 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB6E830E0F5; Mon, 23 Feb 2026 16:23:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; 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Mon, 23 Feb 2026 11:22:34 -0500 From: Antoniu Miclaus To: Lars-Peter Clausen , Michael Hennerich , Antoniu Miclaus , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan , Mark Brown , "Sebastian Reichel" , , , , Subject: [PATCH v4 2/5] spi: add devm_spi_new_ancillary_device() Date: Mon, 23 Feb 2026 18:21:01 +0200 Message-ID: <20260223162110.156746-3-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260223162110.156746-1-antoniu.miclaus@analog.com> References: <20260223162110.156746-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: TvdlpOuPdYfz8Hd6-WkXS81e-O-cPPoU X-Authority-Analysis: v=2.4 cv=RPK+3oi+ c=1 sm=1 tr=0 ts=699c7ed5 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=N--XFCr6TIEc_64PeIT2:22 a=gAnH3GRIAAAA:8 a=8fGt7KVEpqQUrG_l--wA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-ORIG-GUID: TvdlpOuPdYfz8Hd6-WkXS81e-O-cPPoU X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjIzMDE0MCBTYWx0ZWRfX4WrH1N79a1W1 dKwPGpeCYXAHAwvWTVVMoR5rAQ0FKBqtY+qjEFfn8jHW9G29BMV8NgA9LN8kSy+zuxzwPeS/3Z2 eio05VQlw8rU3KGY38OQ0qg9cLQ2F6Hf7sThkdV5vw0IGNUuGIs6K0gz1kkQdi23cE6qYet2GX3 P8ZDho0wVIppnVZ3TQ+zn+saHBTkAafS33dEun/pqXXC7VnXbL0mI2YZTkiCl6Ig1BKaij3gg5q +6VigVpWbdf0N0w9KaJhs0e4ETMP4q5BV0ga3k3aQFADj6jR76VTieWHnUSPT7z1bzpeU2bkyLB X3E2RnTxzljrEmiCDQpNtXhJRXuhsMj8a8YoxUgrBsElQEqmugsSosuI0xfaeNipWft0zTKu2/y GFKbrfnMyT3xC2b1xFHcu1Dhs0I3nzHwxCrQ15okRgLa6vJTDNYZQ5KQpl/lhGqubDM7FxBa4IO vmnCu9rUSnA76rr5UnA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-23_03,2026-02-23_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 adultscore=0 priorityscore=1501 spamscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602230140 Add a devres-managed version of spi_new_ancillary_device() that automatically unregisters the ancillary SPI device when the parent device is removed. This follows the same devm_add_action_or_reset() pattern used by the other managed SPI functions (devm_spi_optimize_message, devm_spi_register_controller, etc.) and eliminates the need for drivers to open-code their own devm cleanup callbacks for ancillary devices. Acked-by: Nuno S=C3=A1 Signed-off-by: Antoniu Miclaus --- Changes in v4: - Add Acked-by from Nuno S=C3=A1 drivers/spi/spi.c | 40 ++++++++++++++++++++++++++++++++++++++++ include/linux/spi/spi.h | 1 + 2 files changed, 41 insertions(+) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 693bdcc5a12a..1b48ec67b8e0 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -2612,6 +2612,46 @@ struct spi_device *spi_new_ancillary_device(struct s= pi_device *spi, } EXPORT_SYMBOL_GPL(spi_new_ancillary_device); =20 +static void devm_spi_unregister_device(void *spi) +{ + spi_unregister_device(spi); +} + +/** + * devm_spi_new_ancillary_device() - Register managed ancillary SPI device + * @spi: Pointer to the main SPI device registering the ancillary = device + * @chip_select: Chip Select of the ancillary device + * + * Register an ancillary SPI device; for example some chips have a chip-se= lect + * for normal device usage and another one for setup/firmware upload. + * + * This is the managed version of spi_new_ancillary_device(). The ancillary + * device will be unregistered automatically when the parent SPI device is + * unregistered. + * + * This may only be called from main SPI device's probe routine. + * + * Return: Pointer to new ancillary device on success; ERR_PTR on failure + */ +struct spi_device *devm_spi_new_ancillary_device(struct spi_device *spi, + u8 chip_select) +{ + struct spi_device *ancillary; + int ret; + + ancillary =3D spi_new_ancillary_device(spi, chip_select); + if (IS_ERR(ancillary)) + return ancillary; + + ret =3D devm_add_action_or_reset(&spi->dev, devm_spi_unregister_device, + ancillary); + if (ret) + return ERR_PTR(ret); + + return ancillary; +} +EXPORT_SYMBOL_GPL(devm_spi_new_ancillary_device); + #ifdef CONFIG_ACPI struct acpi_spi_lookup { struct spi_controller *ctlr; diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index cb2c2df31089..9aef1987b12f 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -374,6 +374,7 @@ static inline void spi_unregister_driver(struct spi_dri= ver *sdrv) } =20 extern struct spi_device *spi_new_ancillary_device(struct spi_device *spi,= u8 chip_select); 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This is useful for multi-channel devices that have multiple backends, where looking up by index is more straightforward than using named backends. The new function directly uses the index to find the backend reference in the io-backends property, avoiding the need for io-backend-names. Reviewed-by: Nuno S=C3=A1 Signed-off-by: Antoniu Miclaus --- Changes in v4: - Add Reviewed-by from Nuno S=C3=A1 drivers/iio/industrialio-backend.c | 61 ++++++++++++++++++++---------- include/linux/iio/backend.h | 2 + 2 files changed, 44 insertions(+), 19 deletions(-) diff --git a/drivers/iio/industrialio-backend.c b/drivers/iio/industrialio-= backend.c index 447b694d6d5f..d90a3a0b17c6 100644 --- a/drivers/iio/industrialio-backend.c +++ b/drivers/iio/industrialio-backend.c @@ -949,25 +949,16 @@ int iio_backend_data_transfer_addr(struct iio_backend= *back, u32 address) } EXPORT_SYMBOL_NS_GPL(iio_backend_data_transfer_addr, "IIO_BACKEND"); =20 -static struct iio_backend *__devm_iio_backend_fwnode_get(struct device *de= v, const char *name, - struct fwnode_handle *fwnode) +static struct iio_backend * +__devm_iio_backend_fwnode_get_by_index(struct device *dev, + struct fwnode_handle *fwnode, + unsigned int index) { - struct fwnode_handle *fwnode_back; + struct fwnode_handle *fwnode_back __free(fwnode_handle) =3D + fwnode_find_reference(fwnode, "io-backends", index); struct iio_backend *back; - unsigned int index; int ret; =20 - if (name) { - ret =3D device_property_match_string(dev, "io-backend-names", - name); - if (ret < 0) - return ERR_PTR(ret); - index =3D ret; - } else { - index =3D 0; - } - - fwnode_back =3D fwnode_find_reference(fwnode, "io-backends", index); if (IS_ERR(fwnode_back)) return dev_err_cast_probe(dev, fwnode_back, "Cannot get Firmware reference\n"); @@ -977,21 +968,35 @@ static struct iio_backend *__devm_iio_backend_fwnode_= get(struct device *dev, con if (!device_match_fwnode(back->dev, fwnode_back)) continue; =20 - fwnode_handle_put(fwnode_back); ret =3D __devm_iio_backend_get(dev, back); if (ret) return ERR_PTR(ret); =20 - if (name) - back->idx =3D index; + back->idx =3D index; =20 return back; } =20 - fwnode_handle_put(fwnode_back); return ERR_PTR(-EPROBE_DEFER); } =20 +static struct iio_backend *__devm_iio_backend_fwnode_get(struct device *de= v, const char *name, + struct fwnode_handle *fwnode) +{ + unsigned int index =3D 0; + int ret; + + if (name) { + ret =3D device_property_match_string(dev, "io-backend-names", + name); + if (ret < 0) + return ERR_PTR(ret); + index =3D ret; + } + + return __devm_iio_backend_fwnode_get_by_index(dev, fwnode, index); +} + /** * devm_iio_backend_get - Device managed backend device get * @dev: Consumer device for the backend @@ -1008,6 +1013,24 @@ struct iio_backend *devm_iio_backend_get(struct devi= ce *dev, const char *name) } EXPORT_SYMBOL_NS_GPL(devm_iio_backend_get, "IIO_BACKEND"); =20 +/** + * devm_iio_backend_get_by_index - Device managed backend device get by in= dex + * @dev: Consumer device for the backend + * @index: Index of the backend in the io-backends property + * + * Get's the backend at @index associated with @dev. + * + * RETURNS: + * A backend pointer, negative error pointer otherwise. + */ +struct iio_backend *devm_iio_backend_get_by_index(struct device *dev, + unsigned int index) +{ + return __devm_iio_backend_fwnode_get_by_index(dev, dev_fwnode(dev), + index); +} +EXPORT_SYMBOL_NS_GPL(devm_iio_backend_get_by_index, "IIO_BACKEND"); + /** * devm_iio_backend_fwnode_get - Device managed backend firmware node get * @dev: Consumer device for the backend diff --git a/include/linux/iio/backend.h b/include/linux/iio/backend.h index 7f815f3fed6a..8f18df0ca896 100644 --- a/include/linux/iio/backend.h +++ b/include/linux/iio/backend.h @@ -237,6 +237,8 @@ int iio_backend_extend_chan_spec(struct iio_backend *ba= ck, struct iio_chan_spec *chan); void *iio_backend_get_priv(const struct iio_backend *conv); struct iio_backend *devm_iio_backend_get(struct device *dev, const char *n= ame); +struct iio_backend *devm_iio_backend_get_by_index(struct device *dev, + unsigned int index); struct iio_backend *devm_iio_backend_fwnode_get(struct device *dev, const char *name, struct fwnode_handle *fwnode); --=20 2.43.0 From nobody Sun Apr 5 18:21:02 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84BB130EF7D; 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charset="utf-8" Add support for the AD4880, a dual-channel 20-bit 40MSPS SAR ADC with integrated fully differential amplifiers (FDA). The AD4880 has two independent ADC channels, each with its own SPI configuration interface. This requires: - Two entries in reg property for primary and secondary channel chip selects - Two io-backends entries for the two data channels Signed-off-by: Antoniu Miclaus --- Changes in v4: - Drop redundant maxItems from io-backends since the items list already constrains the maximum count .../bindings/iio/adc/adi,ad4080.yaml | 53 ++++++++++++++++++- 1 file changed, 51 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4080.yaml index ccd6a0ac1539..0cf86c6f9925 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml @@ -18,7 +18,11 @@ description: | service a wide variety of precision, wide bandwidth data acquisition applications. =20 + The AD4880 is a dual-channel variant with two independent ADC channels, + each with its own SPI configuration interface. + https://www.analog.com/media/en/technical-documentation/data-sheets/ad40= 80.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad48= 80.pdf =20 $ref: /schemas/spi/spi-peripheral-props.yaml# =20 @@ -31,9 +35,15 @@ properties: - adi,ad4084 - adi,ad4086 - adi,ad4087 + - adi,ad4880 =20 reg: - maxItems: 1 + minItems: 1 + maxItems: 2 + description: + SPI chip select(s). For single-channel devices, one chip select. + For multi-channel devices like AD4880, two chip selects are required + as each channel has its own SPI configuration interface. =20 spi-max-frequency: description: Configuration of the SPI bus. @@ -57,7 +67,10 @@ properties: vrefin-supply: true =20 io-backends: - maxItems: 1 + minItems: 1 + items: + - description: Backend for channel A (primary) + - description: Backend for channel B (secondary) =20 adi,lvds-cnv-enable: description: Enable the LVDS signal type on the CNV pin. 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Mon, 23 Feb 2026 11:22:44 -0500 From: Antoniu Miclaus To: Antoniu Miclaus , Lars-Peter Clausen , Michael Hennerich , "Jonathan Cameron" , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan , Mark Brown , "Sebastian Reichel" , , , , Subject: [PATCH v4 5/5] iio: adc: ad4080: add support for AD4880 dual-channel ADC Date: Mon, 23 Feb 2026 18:21:04 +0200 Message-ID: <20260223162110.156746-6-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260223162110.156746-1-antoniu.miclaus@analog.com> References: <20260223162110.156746-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjIzMDE0MCBTYWx0ZWRfX/ayXSXvSgJsu iSF3zUTXF7T2pGpKWLATRtXmcsNgD9nRPiPHUTEIMRhgaPChTc2vyjBy6bSr1/Enelt5VK8tK8E CP8cLwjoiuRpBbGVYrWVnB360jt7OplJz5yb71ya3M17AgE5N+Ptd3vyzWQvWbXmm5zXBypwKn/ DqXF0jKVPdecZYMhYRhobvWlLpuUyE977Egld/G+U5WzsOMd+qww30yny9pAFG8Qb5vFLYLxZ0s q/ipX0SA9xyyB/0dhCVC9JpHW21AcJ2DXMkDdZchFQXJbPUWeu/6eQGn8oAHcz+TbcO3flOBOGc gSloiXQxkPr1mCbEfCk0X0+lQM4lG6MHA/v2l5in1OmB+bqX54j4E4rfn+GXX9/AQULV3bnLwME 5dE7MGmQNCy33nVlcOVAyEPyGWjaipngY74aX4Nkz5DI5AlSEygoZfBSU7AMT4RD82SU0/yndd6 4gzyliC/Z6CJNAHYNcw== X-Proofpoint-ORIG-GUID: jc-q32IobbCVVBPO42qUMl0zzWzn3lqQ X-Authority-Analysis: v=2.4 cv=LfgxKzfi c=1 sm=1 tr=0 ts=699c7edd cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=OmVn7CZJonkx5R5zMQLL:22 a=IpJZQVW2AAAA:8 a=gAnH3GRIAAAA:8 a=PfMWlQLGIS_dAahS8X8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=IawgGOuG5U0WyFbmm1f5:22 X-Proofpoint-GUID: jc-q32IobbCVVBPO42qUMl0zzWzn3lqQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-23_03,2026-02-23_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 spamscore=0 phishscore=0 clxscore=1015 adultscore=0 bulkscore=0 malwarescore=0 impostorscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602230140 Add support for the AD4880, a dual-channel 20-bit 40MSPS SAR ADC with integrated fully differential amplifiers (FDA). The AD4880 has two independent ADC channels, each with its own SPI configuration interface. The driver uses spi_new_ancillary_device() to create an additional SPI device for the second channel, allowing both channels to share the same SPI bus with different chip selects. Reviewed-by: David Lechner Reviewed-by: Nuno S=C3=A1 Signed-off-by: Antoniu Miclaus --- Changes in v4: - Use spi_get_chipselect() instead of device_property_read_u32_array() for ancillary device chip select lookup - Add Reviewed-by from Nuno S=C3=A1 drivers/iio/adc/ad4080.c | 243 ++++++++++++++++++++++++++++++--------- 1 file changed, 191 insertions(+), 52 deletions(-) diff --git a/drivers/iio/adc/ad4080.c b/drivers/iio/adc/ad4080.c index 7cf3b6ed7940..2f52ad7b4be0 100644 --- a/drivers/iio/adc/ad4080.c +++ b/drivers/iio/adc/ad4080.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -131,6 +132,9 @@ #define AD4084_CHIP_ID 0x0054 #define AD4086_CHIP_ID 0x0056 #define AD4087_CHIP_ID 0x0057 +#define AD4880_CHIP_ID 0x0750 + +#define AD4080_MAX_CHANNELS 2 =20 #define AD4080_LVDS_CNV_CLK_CNT_MAX 7 =20 @@ -176,8 +180,9 @@ struct ad4080_chip_info { }; =20 struct ad4080_state { - struct regmap *regmap; - struct iio_backend *back; + struct spi_device *spi[AD4080_MAX_CHANNELS]; + struct regmap *regmap[AD4080_MAX_CHANNELS]; + struct iio_backend *back[AD4080_MAX_CHANNELS]; const struct ad4080_chip_info *info; /* * Synchronize access to members the of driver state, and ensure @@ -203,10 +208,11 @@ static int ad4080_reg_access(struct iio_dev *indio_de= v, unsigned int reg, { struct ad4080_state *st =3D iio_priv(indio_dev); =20 + /* Use channel 0 regmap for debugfs access */ if (readval) - return regmap_read(st->regmap, reg, readval); + return regmap_read(st->regmap[0], reg, readval); =20 - return regmap_write(st->regmap, reg, writeval); + return regmap_write(st->regmap[0], reg, writeval); } =20 static int ad4080_get_scale(struct ad4080_state *st, int *val, int *val2) @@ -227,8 +233,9 @@ static unsigned int ad4080_get_dec_rate(struct iio_dev = *dev, struct ad4080_state *st =3D iio_priv(dev); int ret; unsigned int data; + unsigned int ch =3D chan->channel; =20 - ret =3D regmap_read(st->regmap, AD4080_REG_FILTER_CONFIG, &data); + ret =3D regmap_read(st->regmap[ch], AD4080_REG_FILTER_CONFIG, &data); if (ret) return ret; =20 @@ -240,13 +247,14 @@ static int ad4080_set_dec_rate(struct iio_dev *dev, unsigned int mode) { struct ad4080_state *st =3D iio_priv(dev); + unsigned int ch =3D chan->channel; =20 guard(mutex)(&st->lock); =20 if ((st->filter_type >=3D SINC_5 && mode >=3D 512) || mode < 2) return -EINVAL; =20 - return regmap_update_bits(st->regmap, AD4080_REG_FILTER_CONFIG, + return regmap_update_bits(st->regmap[ch], AD4080_REG_FILTER_CONFIG, AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK, FIELD_PREP(AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK, (ilog2(mode) - 1))); @@ -304,23 +312,23 @@ static int ad4080_write_raw(struct iio_dev *indio_dev, } } =20 -static int ad4080_lvds_sync_write(struct ad4080_state *st) +static int ad4080_lvds_sync_write(struct ad4080_state *st, unsigned int ch) { - struct device *dev =3D regmap_get_device(st->regmap); + struct device *dev =3D regmap_get_device(st->regmap[ch]); int ret; =20 - ret =3D regmap_set_bits(st->regmap, AD4080_REG_ADC_DATA_INTF_CONFIG_A, + ret =3D regmap_set_bits(st->regmap[ch], AD4080_REG_ADC_DATA_INTF_CONFIG_A, AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN); if (ret) return ret; =20 - ret =3D iio_backend_interface_data_align(st->back, 10000); + ret =3D iio_backend_interface_data_align(st->back[ch], 10000); if (ret) return dev_err_probe(dev, ret, "Data alignment process failed\n"); =20 dev_dbg(dev, "Success: Pattern correct and Locked!\n"); - return regmap_clear_bits(st->regmap, AD4080_REG_ADC_DATA_INTF_CONFIG_A, + return regmap_clear_bits(st->regmap[ch], AD4080_REG_ADC_DATA_INTF_CONFIG_= A, AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN); } =20 @@ -329,9 +337,10 @@ static int ad4080_get_filter_type(struct iio_dev *dev, { struct ad4080_state *st =3D iio_priv(dev); unsigned int data; + unsigned int ch =3D chan->channel; int ret; =20 - ret =3D regmap_read(st->regmap, AD4080_REG_FILTER_CONFIG, &data); + ret =3D regmap_read(st->regmap[ch], AD4080_REG_FILTER_CONFIG, &data); if (ret) return ret; =20 @@ -343,6 +352,7 @@ static int ad4080_set_filter_type(struct iio_dev *dev, unsigned int mode) { struct ad4080_state *st =3D iio_priv(dev); + unsigned int ch =3D chan->channel; int dec_rate; int ret; =20 @@ -355,11 +365,11 @@ static int ad4080_set_filter_type(struct iio_dev *dev, if (mode >=3D SINC_5 && dec_rate >=3D 512) return -EINVAL; =20 - ret =3D iio_backend_filter_type_set(st->back, mode); + ret =3D iio_backend_filter_type_set(st->back[ch], mode); if (ret) return ret; =20 - ret =3D regmap_update_bits(st->regmap, AD4080_REG_FILTER_CONFIG, + ret =3D regmap_update_bits(st->regmap[ch], AD4080_REG_FILTER_CONFIG, AD4080_FILTER_CONFIG_FILTER_SEL_MSK, FIELD_PREP(AD4080_FILTER_CONFIG_FILTER_SEL_MSK, mode)); @@ -399,6 +409,29 @@ static int ad4080_read_avail(struct iio_dev *indio_dev, } } =20 +static int ad4880_update_scan_mode(struct iio_dev *indio_dev, + const unsigned long *scan_mask) +{ + struct ad4080_state *st =3D iio_priv(indio_dev); + unsigned int ch; + int ret; + + for (ch =3D 0; ch < st->info->num_channels; ch++) { + /* + * Each backend has a single channel (channel 0 from the + * backend's perspective), so always use channel index 0. + */ + if (test_bit(ch, scan_mask)) + ret =3D iio_backend_chan_enable(st->back[ch], 0); + else + ret =3D iio_backend_chan_disable(st->back[ch], 0); + if (ret) + return ret; + } + + return 0; +} + static const struct iio_info ad4080_iio_info =3D { .debugfs_reg_access =3D ad4080_reg_access, .read_raw =3D ad4080_read_raw, @@ -406,6 +439,19 @@ static const struct iio_info ad4080_iio_info =3D { .read_avail =3D ad4080_read_avail, }; =20 +/* + * AD4880 needs update_scan_mode to enable/disable individual backend chan= nels. + * Single-channel devices don't need this as their backends may not implem= ent + * chan_enable/chan_disable operations. + */ +static const struct iio_info ad4880_iio_info =3D { + .debugfs_reg_access =3D ad4080_reg_access, + .read_raw =3D ad4080_read_raw, + .write_raw =3D ad4080_write_raw, + .read_avail =3D ad4080_read_avail, + .update_scan_mode =3D ad4880_update_scan_mode, +}; + static const struct iio_enum ad4080_filter_type_enum =3D { .items =3D ad4080_filter_type_iio_enum, .num_items =3D ARRAY_SIZE(ad4080_filter_type_iio_enum), @@ -420,17 +466,51 @@ static struct iio_chan_spec_ext_info ad4080_ext_info[= ] =3D { { } }; =20 -#define AD4080_CHANNEL_DEFINE(bits, storage) { \ +/* + * AD4880 needs per-channel filter configuration since each channel has + * its own independent ADC with separate SPI interface. + */ +static struct iio_chan_spec_ext_info ad4880_ext_info[] =3D { + IIO_ENUM("filter_type", IIO_SEPARATE, &ad4080_filter_type_enum), + IIO_ENUM_AVAILABLE("filter_type", IIO_SEPARATE, + &ad4080_filter_type_enum), + { } +}; + +#define AD4080_CHANNEL_DEFINE(bits, storage, idx) { \ .type =3D IIO_VOLTAGE, \ .indexed =3D 1, \ - .channel =3D 0, \ + .channel =3D (idx), \ .info_mask_separate =3D BIT(IIO_CHAN_INFO_SCALE), \ .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ .info_mask_shared_by_all_available =3D \ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ .ext_info =3D ad4080_ext_info, \ - .scan_index =3D 0, \ + .scan_index =3D (idx), \ + .scan_type =3D { \ + .sign =3D 's', \ + .realbits =3D (bits), \ + .storagebits =3D (storage), \ + }, \ +} + +/* + * AD4880 has per-channel attributes (filter_type, oversampling_ratio, + * sampling_frequency) since each channel has its own independent ADC + * with separate SPI configuration interface. + */ +#define AD4880_CHANNEL_DEFINE(bits, storage, idx) { \ + .type =3D IIO_VOLTAGE, \ + .indexed =3D 1, \ + .channel =3D (idx), \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .info_mask_separate_available =3D \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .ext_info =3D ad4880_ext_info, \ + .scan_index =3D (idx), \ .scan_type =3D { \ .sign =3D 's', \ .realbits =3D (bits), \ @@ -438,17 +518,22 @@ static struct iio_chan_spec_ext_info ad4080_ext_info[= ] =3D { }, \ } =20 -static const struct iio_chan_spec ad4080_channel =3D AD4080_CHANNEL_DEFINE= (20, 32); +static const struct iio_chan_spec ad4080_channel =3D AD4080_CHANNEL_DEFINE= (20, 32, 0); + +static const struct iio_chan_spec ad4081_channel =3D AD4080_CHANNEL_DEFINE= (20, 32, 0); =20 -static const struct iio_chan_spec ad4081_channel =3D AD4080_CHANNEL_DEFINE= (20, 32); +static const struct iio_chan_spec ad4083_channel =3D AD4080_CHANNEL_DEFINE= (16, 16, 0); =20 -static const struct iio_chan_spec ad4083_channel =3D AD4080_CHANNEL_DEFINE= (16, 16); +static const struct iio_chan_spec ad4084_channel =3D AD4080_CHANNEL_DEFINE= (16, 16, 0); =20 -static const struct iio_chan_spec ad4084_channel =3D AD4080_CHANNEL_DEFINE= (16, 16); +static const struct iio_chan_spec ad4086_channel =3D AD4080_CHANNEL_DEFINE= (14, 16, 0); =20 -static const struct iio_chan_spec ad4086_channel =3D AD4080_CHANNEL_DEFINE= (14, 16); +static const struct iio_chan_spec ad4087_channel =3D AD4080_CHANNEL_DEFINE= (14, 16, 0); =20 -static const struct iio_chan_spec ad4087_channel =3D AD4080_CHANNEL_DEFINE= (14, 16); +static const struct iio_chan_spec ad4880_channels[] =3D { + AD4880_CHANNEL_DEFINE(20, 32, 0), + AD4880_CHANNEL_DEFINE(20, 32, 1), +}; =20 static const struct ad4080_chip_info ad4080_chip_info =3D { .name =3D "ad4080", @@ -510,25 +595,34 @@ static const struct ad4080_chip_info ad4087_chip_info= =3D { .lvds_cnv_clk_cnt_max =3D 1, }; =20 -static int ad4080_setup(struct iio_dev *indio_dev) +static const struct ad4080_chip_info ad4880_chip_info =3D { + .name =3D "ad4880", + .product_id =3D AD4880_CHIP_ID, + .scale_table =3D ad4080_scale_table, + .num_scales =3D ARRAY_SIZE(ad4080_scale_table), + .num_channels =3D 2, + .channels =3D ad4880_channels, + .lvds_cnv_clk_cnt_max =3D AD4080_LVDS_CNV_CLK_CNT_MAX, +}; + +static int ad4080_setup_channel(struct ad4080_state *st, unsigned int ch) { - struct ad4080_state *st =3D iio_priv(indio_dev); - struct device *dev =3D regmap_get_device(st->regmap); + struct device *dev =3D regmap_get_device(st->regmap[ch]); __le16 id_le; u16 id; int ret; =20 - ret =3D regmap_write(st->regmap, AD4080_REG_INTERFACE_CONFIG_A, + ret =3D regmap_write(st->regmap[ch], AD4080_REG_INTERFACE_CONFIG_A, AD4080_INTERFACE_CONFIG_A_SW_RESET); if (ret) return ret; =20 - ret =3D regmap_write(st->regmap, AD4080_REG_INTERFACE_CONFIG_A, + ret =3D regmap_write(st->regmap[ch], AD4080_REG_INTERFACE_CONFIG_A, AD4080_INTERFACE_CONFIG_A_SDO_ENABLE); if (ret) return ret; =20 - ret =3D regmap_bulk_read(st->regmap, AD4080_REG_PRODUCT_ID_L, &id_le, + ret =3D regmap_bulk_read(st->regmap[ch], AD4080_REG_PRODUCT_ID_L, &id_le, sizeof(id_le)); if (ret) return ret; @@ -537,18 +631,18 @@ static int ad4080_setup(struct iio_dev *indio_dev) if (id !=3D st->info->product_id) dev_info(dev, "Unrecognized CHIP_ID 0x%X\n", id); =20 - ret =3D regmap_set_bits(st->regmap, AD4080_REG_GPIO_CONFIG_A, + ret =3D regmap_set_bits(st->regmap[ch], AD4080_REG_GPIO_CONFIG_A, AD4080_GPIO_CONFIG_A_GPO_1_EN); if (ret) return ret; =20 - ret =3D regmap_write(st->regmap, AD4080_REG_GPIO_CONFIG_B, + ret =3D regmap_write(st->regmap[ch], AD4080_REG_GPIO_CONFIG_B, FIELD_PREP(AD4080_GPIO_CONFIG_B_GPIO_1_SEL_MSK, AD4080_GPIO_CONFIG_B_GPIO_FILTER_RES_RDY)); if (ret) return ret; =20 - ret =3D iio_backend_num_lanes_set(st->back, st->num_lanes); + ret =3D iio_backend_num_lanes_set(st->back[ch], st->num_lanes); if (ret) return ret; =20 @@ -556,7 +650,7 @@ static int ad4080_setup(struct iio_dev *indio_dev) return 0; =20 /* Set maximum LVDS Data Transfer Latency */ - ret =3D regmap_update_bits(st->regmap, + ret =3D regmap_update_bits(st->regmap[ch], AD4080_REG_ADC_DATA_INTF_CONFIG_B, AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK, FIELD_PREP(AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK, @@ -565,24 +659,39 @@ static int ad4080_setup(struct iio_dev *indio_dev) return ret; =20 if (st->num_lanes > 1) { - ret =3D regmap_set_bits(st->regmap, AD4080_REG_ADC_DATA_INTF_CONFIG_A, + ret =3D regmap_set_bits(st->regmap[ch], AD4080_REG_ADC_DATA_INTF_CONFIG_= A, AD4080_ADC_DATA_INTF_CONFIG_A_SPI_LVDS_LANES); if (ret) return ret; } =20 - ret =3D regmap_set_bits(st->regmap, + ret =3D regmap_set_bits(st->regmap[ch], AD4080_REG_ADC_DATA_INTF_CONFIG_B, AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_EN); if (ret) return ret; =20 - return ad4080_lvds_sync_write(st); + return ad4080_lvds_sync_write(st, ch); +} + +static int ad4080_setup(struct iio_dev *indio_dev) +{ + struct ad4080_state *st =3D iio_priv(indio_dev); + unsigned int ch; + int ret; + + for (ch =3D 0; ch < st->info->num_channels; ch++) { + ret =3D ad4080_setup_channel(st, ch); + if (ret) + return ret; + } + + return 0; } =20 static int ad4080_properties_parse(struct ad4080_state *st) { - struct device *dev =3D regmap_get_device(st->regmap); + struct device *dev =3D regmap_get_device(st->regmap[0]); =20 st->lvds_cnv_en =3D device_property_read_bool(dev, "adi,lvds-cnv-enable"); =20 @@ -602,6 +711,7 @@ static int ad4080_probe(struct spi_device *spi) struct device *dev =3D &spi->dev; struct ad4080_state *st; struct clk *clk; + unsigned int ch; int ret; =20 indio_dev =3D devm_iio_device_alloc(&spi->dev, sizeof(*st)); @@ -610,6 +720,10 @@ static int ad4080_probe(struct spi_device *spi) =20 st =3D iio_priv(indio_dev); =20 + st->info =3D spi_get_device_match_data(spi); + if (!st->info) + return -ENODEV; + ret =3D devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(ad4080_power_supplies), ad4080_power_supplies); @@ -617,13 +731,27 @@ static int ad4080_probe(struct spi_device *spi) return dev_err_probe(dev, ret, "failed to get and enable supplies\n"); =20 - st->regmap =3D devm_regmap_init_spi(spi, &ad4080_regmap_config); - if (IS_ERR(st->regmap)) - return PTR_ERR(st->regmap); - - st->info =3D spi_get_device_match_data(spi); - if (!st->info) - return -ENODEV; + /* Setup primary SPI device (channel 0) */ + st->spi[0] =3D spi; + st->regmap[0] =3D devm_regmap_init_spi(spi, &ad4080_regmap_config); + if (IS_ERR(st->regmap[0])) + return PTR_ERR(st->regmap[0]); + + /* Setup ancillary SPI devices for additional channels */ + if (st->info->num_channels > 1) { + for (int i =3D 1; i < st->info->num_channels; i++) { + st->spi[i] =3D devm_spi_new_ancillary_device(spi, + spi_get_chipselect(spi, i)); + if (IS_ERR(st->spi[i])) + return dev_err_probe(dev, PTR_ERR(st->spi[i]), + "failed to register ancillary device\n"); + + st->regmap[i] =3D devm_regmap_init_spi(st->spi[i], + &ad4080_regmap_config); + if (IS_ERR(st->regmap[i])) + return PTR_ERR(st->regmap[i]); + } + } =20 ret =3D devm_mutex_init(dev, &st->lock); if (ret) @@ -632,7 +760,8 @@ static int ad4080_probe(struct spi_device *spi) indio_dev->name =3D st->info->name; indio_dev->channels =3D st->info->channels; indio_dev->num_channels =3D st->info->num_channels; - indio_dev->info =3D &ad4080_iio_info; + indio_dev->info =3D st->info->num_channels > 1 ? + &ad4880_iio_info : &ad4080_iio_info; =20 ret =3D ad4080_properties_parse(st); if (ret) @@ -644,15 +773,23 @@ static int ad4080_probe(struct spi_device *spi) =20 st->clk_rate =3D clk_get_rate(clk); =20 - st->back =3D devm_iio_backend_get(dev, NULL); - if (IS_ERR(st->back)) - return PTR_ERR(st->back); + /* Get backends for all channels */ + for (ch =3D 0; ch < st->info->num_channels; ch++) { + st->back[ch] =3D devm_iio_backend_get_by_index(dev, ch); + if (IS_ERR(st->back[ch])) + return PTR_ERR(st->back[ch]); =20 - ret =3D devm_iio_backend_request_buffer(dev, st->back, indio_dev); - if (ret) - return ret; + ret =3D devm_iio_backend_enable(dev, st->back[ch]); + if (ret) + return ret; + } =20 - ret =3D devm_iio_backend_enable(dev, st->back); + /* + * Request buffer from the first backend only. For multi-channel + * devices (e.g., AD4880), all backends share a single IIO buffer + * as data from all ADC channels is interleaved into one stream. + */ + ret =3D devm_iio_backend_request_buffer(dev, st->back[0], indio_dev); if (ret) return ret; =20 @@ -670,6 +807,7 @@ static const struct spi_device_id ad4080_id[] =3D { { "ad4084", (kernel_ulong_t)&ad4084_chip_info }, { "ad4086", (kernel_ulong_t)&ad4086_chip_info }, { "ad4087", (kernel_ulong_t)&ad4087_chip_info }, + { "ad4880", (kernel_ulong_t)&ad4880_chip_info }, { } }; MODULE_DEVICE_TABLE(spi, ad4080_id); @@ -681,6 +819,7 @@ static const struct of_device_id ad4080_of_match[] =3D { { .compatible =3D "adi,ad4084", &ad4084_chip_info }, { .compatible =3D "adi,ad4086", &ad4086_chip_info }, { .compatible =3D "adi,ad4087", &ad4087_chip_info }, + { .compatible =3D "adi,ad4880", &ad4880_chip_info }, { } }; MODULE_DEVICE_TABLE(of, ad4080_of_match); --=20 2.43.0