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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-358a2a768bcsm5623954a91.4.2026.02.22.20.49.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Feb 2026 20:49:30 -0800 (PST) From: Himanshu Chauhan To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, shuah@kernel.org Cc: Himanshu Chauhan Subject: [PATCH v3 1/2] riscv: Introduce support for hardware break/watchpoints Date: Mon, 23 Feb 2026 10:19:17 +0530 Message-ID: <20260223044918.1359983-2-himanshu.chauhan@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260223044918.1359983-1-himanshu.chauhan@oss.qualcomm.com> References: <20260223044918.1359983-1-himanshu.chauhan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=XbWEDY55 c=1 sm=1 tr=0 ts=699bdc5c cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=NdCxyxYjUNQXf4Wx1tIA:9 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjIzMDA0MCBTYWx0ZWRfXwpnm9hVr1fyW ctzx2ddBW9tFa5+NxAq7ywjDJg5Hr3lLYJ6g9z09cJmuH520jeZ2WboPvMA0nGjzU6azcDdieB6 KtLLXPEVj0amfFO4V6kKxtb+gWSN5D5Yg1Y8NGX9XCJ9E65fnCuGxVGxJ907jeojVT+QEjlZaiA L/nYgUsKS5KBIG1Q+HmPH1Q5UaXqGpTADqK9BqAhVqlqVm0mC/CUsYlfMP4GFOtsmWU3UqW2Z+Q TsYdqoYMsWn+Sx7QoJ+p/qgmS0DimgTK7MY+7E+OStjmAcP+vHzMFh1ChCT6anKIUcOACbzzTYv xDFmpyr8WhdlF9iVhy3zjfh8acWLuoCxlGRWihyoUYnU4cONd2clLjL/SrCUU2PTCjfoIYin6Km VRaBrt/xMazsVvJ0z6oOf/N4gRcy9nDPWHZ00hcpLI+2daSKXVK6pbtM5QdA6+iIrIMX5pCdQej g/MIyP69iohn0NfTO6w== X-Proofpoint-ORIG-GUID: xVbTF76w2gmcT1KIHJgxsNfFAbP_IltA X-Proofpoint-GUID: xVbTF76w2gmcT1KIHJgxsNfFAbP_IltA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-23_01,2026-02-20_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 suspectscore=0 malwarescore=0 phishscore=0 priorityscore=1501 adultscore=0 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602230040 Content-Type: text/plain; charset="utf-8" RISC-V hardware breakpoint framework is built on top of perf subsystem and uses SBI debug trigger extension to install/uninstall/update/enable/disable hardware triggers as specified in Sdtrig ISA extension. Signed-off-by: Himanshu Chauhan --- arch/riscv/Kconfig | 1 + arch/riscv/include/asm/hw_breakpoint.h | 332 +++++++++++++ arch/riscv/include/asm/kdebug.h | 3 +- arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/hw_breakpoint.c | 657 +++++++++++++++++++++++++ arch/riscv/kernel/traps.c | 6 + 6 files changed, 999 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/include/asm/hw_breakpoint.h create mode 100644 arch/riscv/kernel/hw_breakpoint.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 90c531e6abf5..ac4b4175763e 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -170,6 +170,7 @@ config RISCV select HAVE_FUNCTION_ERROR_INJECTION select HAVE_GCC_PLUGINS select HAVE_GENERIC_VDSO if MMU + select HAVE_HW_BREAKPOINT if PERF_EVENTS select HAVE_IRQ_TIME_ACCOUNTING select HAVE_KERNEL_BZIP2 if !XIP_KERNEL && !EFI_ZBOOT select HAVE_KERNEL_GZIP if !XIP_KERNEL && !EFI_ZBOOT diff --git a/arch/riscv/include/asm/hw_breakpoint.h b/arch/riscv/include/as= m/hw_breakpoint.h new file mode 100644 index 000000000000..a5ef70fa14a1 --- /dev/null +++ b/arch/riscv/include/asm/hw_breakpoint.h @@ -0,0 +1,332 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2026 Qualcomm Technologies, Inc. + */ + +#ifndef __RISCV_HW_BREAKPOINT_H +#define __RISCV_HW_BREAKPOINT_H + +struct task_struct; + +#ifdef CONFIG_HAVE_HW_BREAKPOINT + +#include + +#if __riscv_xlen =3D=3D 64 +#define cpu_to_le cpu_to_le64 +#define le_to_cpu le64_to_cpu +#elif __riscv_xlen =3D=3D 32 +#define cpu_to_le cpu_to_le32 +#define le_to_cpu le32_to_cpu +#else +#error "Unexpected __riscv_xlen" +#endif + +#define RV_DBTR_BIT(_prefix, _name) \ + RV_DBTR_##_prefix##_##_name##_BIT + +#define RV_DBTR_BIT_MASK(_prefix, _name) \ + RV_DBTR_##_prefix##_name##_BIT_MASK + +#define RV_DBTR_BIT_MASK_VAL(_prefix, _name, _width) \ + (((1UL << (_width)) - 1) << RV_DBTR_BIT(_prefix, _name)) + +#define CLEAR_DBTR_BIT(_target, _prefix, _bit_name) \ + __clear_bit(RV_DBTR_BIT(_prefix, _bit_name), &(_target)) + +#define SET_DBTR_BIT(_target, _prefix, _bit_name) \ + __set_bit(RV_DBTR_BIT(_prefix, _bit_name), &(_target)) + +enum { + RV_DBTR_BP =3D 0, + RV_DBTR_WP =3D 1, +}; + +enum { + RV_DBTR_TRIG_NONE =3D 0, + RV_DBTR_TRIG_LEGACY, + RV_DBTR_TRIG_MCONTROL, + RV_DBTR_TRIG_ICOUNT, + RV_DBTR_TRIG_ITRIGGER, + RV_DBTR_TRIG_ETRIGGER, + RV_DBTR_TRIG_MCONTROL6, +}; + +/* Trigger Data 1 */ +enum { + RV_DBTR_BIT(TDATA1, DATA) =3D 0, +#if __riscv_xlen =3D=3D 64 + RV_DBTR_BIT(TDATA1, DMODE) =3D 59, + RV_DBTR_BIT(TDATA1, TYPE) =3D 60, +#elif __riscv_xlen =3D=3D 32 + RV_DBTR_BIT(TDATA1, DMODE) =3D 27, + RV_DBTR_BIT(TDATA1, TYPE) =3D 28, +#else + #error "Unknown __riscv_xlen" +#endif +}; + +enum { +#if __riscv_xlen =3D=3D 64 + RV_DBTR_BIT_MASK(TDATA1, DATA) =3D RV_DBTR_BIT_MASK_VAL(TDATA1, DATA, 59), +#elif __riscv_xlen =3D=3D 32 + RV_DBTR_BIT_MASK(TDATA1, DATA) =3D RV_DBTR_BIT_MASK_VAL(TDATA1, DATA, 27= ), +#else + #error "Unknown __riscv_xlen" +#endif + RV_DBTR_BIT_MASK(TDAT1, DMODE) =3D RV_DBTR_BIT_MASK_VAL(TDATA1, DMODE, 1), + RV_DBTR_BIT_MASK(TDATA1, TYPE) =3D RV_DBTR_BIT_MASK_VAL(TDATA1, TYPE, 4), +}; + +/* MC - Match Control Type Register */ +enum { + RV_DBTR_BIT(MC, LOAD) =3D 0, + RV_DBTR_BIT(MC, STORE) =3D 1, + RV_DBTR_BIT(MC, EXEC) =3D 2, + RV_DBTR_BIT(MC, U) =3D 3, + RV_DBTR_BIT(MC, S) =3D 4, + RV_DBTR_BIT(MC, RES2) =3D 5, + RV_DBTR_BIT(MC, M) =3D 6, + RV_DBTR_BIT(MC, MATCH) =3D 7, + RV_DBTR_BIT(MC, CHAIN) =3D 11, + RV_DBTR_BIT(MC, ACTION) =3D 12, + RV_DBTR_BIT(MC, SIZELO) =3D 16, + RV_DBTR_BIT(MC, TIMING) =3D 18, + RV_DBTR_BIT(MC, SELECT) =3D 19, + RV_DBTR_BIT(MC, HIT) =3D 20, +#if __riscv_xlen >=3D 64 + RV_DBTR_BIT(MC, SIZEHI) =3D 21, +#endif +#if __riscv_xlen =3D=3D 64 + RV_DBTR_BIT(MC, MASKMAX) =3D 53, + RV_DBTR_BIT(MC, DMODE) =3D 59, + RV_DBTR_BIT(MC, TYPE) =3D 60, +#elif __riscv_xlen =3D=3D 32 + RV_DBTR_BIT(MC, MASKMAX) =3D 21, + RV_DBTR_BIT(MC, DMODE) =3D 27, + RV_DBTR_BIT(MC, TYPE) =3D 28, +#else + #error "Unknown riscv xlen" +#endif +}; + +enum { + RV_DBTR_BIT_MASK(MC, LOAD) =3D RV_DBTR_BIT_MASK_VAL(MC, LOAD, 1), + RV_DBTR_BIT_MASK(MC, STORE) =3D RV_DBTR_BIT_MASK_VAL(MC, STORE, 1), + RV_DBTR_BIT_MASK(MC, EXEC) =3D RV_DBTR_BIT_MASK_VAL(MC, EXEC, 1), + RV_DBTR_BIT_MASK(MC, U) =3D RV_DBTR_BIT_MASK_VAL(MC, U, 1), + RV_DBTR_BIT_MASK(MC, S) =3D RV_DBTR_BIT_MASK_VAL(MC, S, 1), + RV_DBTR_BIT_MASK(MC, RES2) =3D RV_DBTR_BIT_MASK_VAL(MC, RES2, 1), + RV_DBTR_BIT_MASK(MC, M) =3D RV_DBTR_BIT_MASK_VAL(MC, M, 1), + RV_DBTR_BIT_MASK(MC, MATCH) =3D RV_DBTR_BIT_MASK_VAL(MC, MATCH, 4), + RV_DBTR_BIT_MASK(MC, CHAIN) =3D RV_DBTR_BIT_MASK_VAL(MC, CHAIN, 1), + RV_DBTR_BIT_MASK(MC, ACTION) =3D RV_DBTR_BIT_MASK_VAL(MC, ACTION, 4), + RV_DBTR_BIT_MASK(MC, SIZELO) =3D RV_DBTR_BIT_MASK_VAL(MC, SIZELO, 2), + RV_DBTR_BIT_MASK(MC, TIMING) =3D RV_DBTR_BIT_MASK_VAL(MC, TIMING, 1), + RV_DBTR_BIT_MASK(MC, SELECT) =3D RV_DBTR_BIT_MASK_VAL(MC, SELECT, 1), + RV_DBTR_BIT_MASK(MC, HIT) =3D RV_DBTR_BIT_MASK_VAL(MC, HIT, 1), +#if __riscv_xlen >=3D 64 + RV_DBTR_BIT_MASK(MC, SIZEHI) =3D RV_DBTR_BIT_MASK_VAL(MC, SIZEHI, 2), +#endif + RV_DBTR_BIT_MASK(MC, MASKMAX) =3D RV_DBTR_BIT_MASK_VAL(MC, MASKMAX, 6), + RV_DBTR_BIT_MASK(MC, DMODE) =3D RV_DBTR_BIT_MASK_VAL(MC, DMODE, 1), + RV_DBTR_BIT_MASK(MC, TYPE) =3D RV_DBTR_BIT_MASK_VAL(MC, TYPE, 4), +}; + +/* MC6 - Match Control 6 Type Register */ +enum { + RV_DBTR_BIT(MC6, LOAD) =3D 0, + RV_DBTR_BIT(MC6, STORE) =3D 1, + RV_DBTR_BIT(MC6, EXEC) =3D 2, + RV_DBTR_BIT(MC6, U) =3D 3, + RV_DBTR_BIT(MC6, S) =3D 4, + RV_DBTR_BIT(MC6, RES2) =3D 5, + RV_DBTR_BIT(MC6, M) =3D 6, + RV_DBTR_BIT(MC6, MATCH) =3D 7, + RV_DBTR_BIT(MC6, CHAIN) =3D 11, + RV_DBTR_BIT(MC6, ACTION) =3D 12, + RV_DBTR_BIT(MC6, SIZE) =3D 16, + RV_DBTR_BIT(MC6, TIMING) =3D 20, + RV_DBTR_BIT(MC6, SELECT) =3D 21, + RV_DBTR_BIT(MC6, HIT) =3D 22, + RV_DBTR_BIT(MC6, VU) =3D 23, + RV_DBTR_BIT(MC6, VS) =3D 24, +#if __riscv_xlen =3D=3D 64 + RV_DBTR_BIT(MC6, DMODE) =3D 59, + RV_DBTR_BIT(MC6, TYPE) =3D 60, +#elif __riscv_xlen =3D=3D 32 + RV_DBTR_BIT(MC6, DMODE) =3D 27, + RV_DBTR_BIT(MC6, TYPE) =3D 28, +#else + #error "Unknown riscv xlen" +#endif +}; + +enum { + RV_DBTR_BIT_MASK(MC6, LOAD) =3D RV_DBTR_BIT_MASK_VAL(MC6, LOAD, 1), + RV_DBTR_BIT_MASK(MC6, STORE) =3D RV_DBTR_BIT_MASK_VAL(MC6, STORE, 1), + RV_DBTR_BIT_MASK(MC6, EXEC) =3D RV_DBTR_BIT_MASK_VAL(MC6, EXEC, 1), + RV_DBTR_BIT_MASK(MC6, U) =3D RV_DBTR_BIT_MASK_VAL(MC6, U, 1), + RV_DBTR_BIT_MASK(MC6, S) =3D RV_DBTR_BIT_MASK_VAL(MC6, S, 1), + RV_DBTR_BIT_MASK(MC6, RES2) =3D RV_DBTR_BIT_MASK_VAL(MC6, RES2, 1), + RV_DBTR_BIT_MASK(MC6, M) =3D RV_DBTR_BIT_MASK_VAL(MC6, M, 1), + RV_DBTR_BIT_MASK(MC6, MATCH) =3D RV_DBTR_BIT_MASK_VAL(MC6, MATCH, 4), + RV_DBTR_BIT_MASK(MC6, CHAIN) =3D RV_DBTR_BIT_MASK_VAL(MC6, CHAIN, 1), + RV_DBTR_BIT_MASK(MC6, ACTION) =3D RV_DBTR_BIT_MASK_VAL(MC6, ACTION, 4), + RV_DBTR_BIT_MASK(MC6, SIZE) =3D RV_DBTR_BIT_MASK_VAL(MC6, SIZE, 4), + RV_DBTR_BIT_MASK(MC6, TIMING) =3D RV_DBTR_BIT_MASK_VAL(MC6, TIMING, 1), + RV_DBTR_BIT_MASK(MC6, SELECT) =3D RV_DBTR_BIT_MASK_VAL(MC6, SELECT, 1), + RV_DBTR_BIT_MASK(MC6, HIT) =3D RV_DBTR_BIT_MASK_VAL(MC6, HIT, 1), + RV_DBTR_BIT_MASK(MC6, VU) =3D RV_DBTR_BIT_MASK_VAL(MC6, VU, 1), + RV_DBTR_BIT_MASK(MC6, VS) =3D RV_DBTR_BIT_MASK_VAL(MC6, VS, 1), +#if __riscv_xlen =3D=3D 64 + RV_DBTR_BIT_MASK(MC6, DMODE) =3D RV_DBTR_BIT_MASK_VAL(MC6, DMODE, 1), + RV_DBTR_BIT_MASK(MC6, TYPE) =3D RV_DBTR_BIT_MASK_VAL(MC6, TYPE, 4), +#elif __riscv_xlen =3D=3D 32 + RV_DBTR_BIT_MASK(MC6, DMODE) =3D RV_DBTR_BIT_MASK_VAL(MC6, DMODE, 1), + RV_DBTR_BIT_MASK(MC6, TYPE) =3D RV_DBTR_BIT_MASK_VAL(MC6, TYPE, 4), +#else + #error "Unknown riscv xlen" +#endif +}; + +#define RV_DBTR_SET_TDATA1_TYPE(_t1, _type) \ + ({ \ + typeof(_t1) (td1t1) =3D (_t1); \ + (td1t1) &=3D ~RV_DBTR_BIT_MASK(TDATA1, TYPE); \ + (td1t1) |=3D (((unsigned long)(_type) \ + << RV_DBTR_BIT(TDATA1, TYPE)) \ + & RV_DBTR_BIT_MASK(TDATA1, TYPE)); \ + (td1t1); \ + }) + +#define RV_DBTR_SET_MC_TYPE(_t1, _type) \ + ({ \ + typeof(_t1) (mct1) =3D (_t1); \ + (mct1) &=3D ~RV_DBTR_BIT_MASK(MC, TYPE); \ + (mct1) |=3D (((unsigned long)(_type) \ + << RV_DBTR_BIT(MC, TYPE)) \ + & RV_DBTR_BIT_MASK(MC, TYPE)); \ + (mct1); \ + }) + +#define RV_DBTR_SET_MC6_TYPE(_t1, _type) \ + ({ \ + typeof(_t1) (mc6t1) =3D (_t1); \ + (mc6t1) &=3D ~RV_DBTR_BIT_MASK(MC6, TYPE); \ + (mc6t1) |=3D (((unsigned long)(_type) \ + << RV_DBTR_BIT(MC6, TYPE)) \ + & RV_DBTR_BIT_MASK(MC6, TYPE)); \ + (mc6t1); \ + }) + +#define RV_DBTR_SET_MC_EXEC_BIT(_t1) \ + SET_DBTR_BIT(_t1, MC, EXEC) + +#define RV_DBTR_SET_MC_LOAD_BIT(_t1) \ + SET_DBTR_BIT(_t1, MC, LOAD) + +#define RV_DBTR_SET_MC_STORE_BIT(_t1) \ + SET_DBTR_BIT(_t1, MC, STORE) + +#define RV_DBTR_SET_MC_SIZELO(_t1, _val) \ + ({ \ + typeof(_t1) (mcslt1) =3D (_t1); \ + mcslt1 &=3D ~RV_DBTR_BIT_MASK(MC, SIZELO); \ + mcslt1 |=3D (((_val) << RV_DBTR_BIT(MC, SIZELO)) \ + & RV_DBTR_BIT_MASK(MC, SIZELO)); \ + (mcslt1); \ + }) + +#define RV_DBTR_SET_MC_SIZEHI(_t1, _val) \ + ({ \ + typeof(_t1) (mcsht1) =3D (_t1); \ + mcsht1 &=3D ~RV_DBTR_BIT_MASK(MC, SIZEHI); \ + mcsht1 |=3D (((_val) << RV_DBTR_BIT(MC, SIZEHI)) \ + & RV_DBTR_BIT_MASK(MC, SIZEHI)); \ + (mcsht1); \ + }) + +#define RV_DBTR_SET_MC6_EXEC_BIT(_t1) \ + SET_DBTR_BIT(_t1, MC6, EXEC) + +#define RV_DBTR_SET_MC6_LOAD_BIT(_t1) \ + SET_DBTR_BIT(_t1, MC6, LOAD) + +#define RV_DBTR_SET_MC6_STORE_BIT(_t1) \ + SET_DBTR_BIT(_t1, MC6, STORE) + +#define RV_DBTR_SET_MC6_SIZE(_t1, _val) \ + ({ \ + typeof(_t1) (mc6szt1) =3D (_t1); \ + (mc6szt1) &=3D ~RV_DBTR_BIT_MASK(MC6, SIZE); \ + (mc6szt1) |=3D (((_val) << RV_DBTR_BIT(MC6, SIZE)) \ + & RV_DBTR_BIT_MASK(MC6, SIZE)); \ + (mc6szt1); \ + }) + +struct arch_hw_breakpoint { + unsigned long address; + unsigned long len; + unsigned int type; + + /* Trigger configuration data */ + unsigned long tdata1; + unsigned long tdata2; + unsigned long tdata3; +}; + +/* Maximum number of hardware breakpoints supported */ +#define HW_BP_NUM_MAX 32 + +struct perf_event_attr; +struct notifier_block; +struct perf_event; +struct pt_regs; + +int hw_breakpoint_slots(int type); +int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw); +int hw_breakpoint_arch_parse(struct perf_event *bp, + const struct perf_event_attr *attr, + struct arch_hw_breakpoint *hw); +int hw_breakpoint_exceptions_notify(struct notifier_block *unused, + unsigned long val, void *data); + +void arch_enable_hw_breakpoint(struct perf_event *bp); +void arch_update_hw_breakpoint(struct perf_event *bp); +void arch_disable_hw_breakpoint(struct perf_event *bp); +int arch_install_hw_breakpoint(struct perf_event *bp); +void arch_uninstall_hw_breakpoint(struct perf_event *bp); +void hw_breakpoint_pmu_read(struct perf_event *bp); +void clear_ptrace_hw_breakpoint(struct task_struct *tsk); +void flush_ptrace_hw_breakpoint(struct task_struct *tsk); + +#else + +int hw_breakpoint_slots(int type) +{ + return 0; +} + +static inline void clear_ptrace_hw_breakpoint(struct task_struct *tsk) +{ +} + +static inline void flush_ptrace_hw_breakpoint(struct task_struct *tsk) +{ +} + +void arch_enable_hw_breakpoint(struct perf_event *bp) +{ +} + +void arch_update_hw_breakpoint(struct perf_event *bp) +{ +} + +void arch_disable_hw_breakpoint(struct perf_event *bp) +{ +} + +#endif /* CONFIG_HAVE_HW_BREAKPOINT */ +#endif /* __RISCV_HW_BREAKPOINT_H */ diff --git a/arch/riscv/include/asm/kdebug.h b/arch/riscv/include/asm/kdebu= g.h index 85ac00411f6e..53e989781aa1 100644 --- a/arch/riscv/include/asm/kdebug.h +++ b/arch/riscv/include/asm/kdebug.h @@ -6,7 +6,8 @@ enum die_val { DIE_UNUSED, DIE_TRAP, - DIE_OOPS + DIE_OOPS, + DIE_DEBUG }; =20 #endif diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index cabb99cadfb6..590a280762c9 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -100,6 +100,7 @@ obj-$(CONFIG_DYNAMIC_FTRACE) +=3D mcount-dyn.o =20 obj-$(CONFIG_PERF_EVENTS) +=3D perf_callchain.o obj-$(CONFIG_HAVE_PERF_REGS) +=3D perf_regs.o +obj-$(CONFIG_HAVE_HW_BREAKPOINT) +=3D hw_breakpoint.o obj-$(CONFIG_RISCV_SBI) +=3D sbi.o sbi_ecall.o ifeq ($(CONFIG_RISCV_SBI), y) obj-$(CONFIG_SMP) +=3D sbi-ipi.o diff --git a/arch/riscv/kernel/hw_breakpoint.c b/arch/riscv/kernel/hw_break= point.c new file mode 100644 index 000000000000..8076829d23d3 --- /dev/null +++ b/arch/riscv/kernel/hw_breakpoint.c @@ -0,0 +1,657 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 Qualcomm Technologies, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* Registered per-cpu bp/wp */ +static DEFINE_PER_CPU(struct perf_event *, pcpu_hw_bp_events[HW_BP_NUM_MAX= ]); +static DEFINE_PER_CPU(unsigned long, ecall_lock_flags); +static DEFINE_PER_CPU(raw_spinlock_t, ecall_lock); + +/* Per-cpu shared memory between S and M mode */ +static union sbi_dbtr_shmem_entry __percpu *sbi_dbtr_shmem; + +/* number of debug triggers on this cpu . */ +static int dbtr_total_num __ro_after_init; +static int dbtr_type __ro_after_init; +static int dbtr_init __ro_after_init; + +#if __riscv_xlen =3D=3D 64 +#define MEM_HI(_m) 0 +#define MEM_LO(_m) ((u64)(_m)) +#elif __riscv_xlen =3D=3D 32 +#define MEM_HI(_m) ((u64)(_m) >> 32) +#define MEM_LO(_m) ((u64)(_m) & 0xFFFFFFFFUL) +#else +#error "Unknown __riscv_xlen" +#endif + +static int arch_smp_setup_sbi_shmem(unsigned int cpu) +{ + union sbi_dbtr_shmem_entry *dbtr_shmem; + unsigned long shmem_pa; + struct sbiret ret; + int rc =3D 0; + + dbtr_shmem =3D per_cpu_ptr(sbi_dbtr_shmem, cpu); + if (!dbtr_shmem) { + pr_err("Invalid per-cpu shared memory for debug triggers\n"); + return -ENODEV; + } + + shmem_pa =3D __pa(dbtr_shmem); + + ret =3D sbi_ecall(SBI_EXT_DBTR, SBI_EXT_DBTR_SETUP_SHMEM, + MEM_LO(shmem_pa), MEM_HI(shmem_pa), 0, 0, 0, 0); + + if (ret.error) { + switch (ret.error) { + case SBI_ERR_DENIED: + pr_warn("%s: Access denied for shared memory at %lx\n", + __func__, shmem_pa); + rc =3D -EPERM; + break; + + case SBI_ERR_INVALID_PARAM: + case SBI_ERR_INVALID_ADDRESS: + pr_warn("%s: Invalid address parameter (%lu)\n", + __func__, ret.error); + rc =3D -EINVAL; + break; + + case SBI_ERR_ALREADY_AVAILABLE: + pr_warn("%s: Shared memory is already set\n", + __func__); + rc =3D -EADDRINUSE; + break; + + case SBI_ERR_FAILURE: + pr_err("%s: Internal sdtrig state error\n", + __func__); + rc =3D -ENXIO; + break; + + default: + pr_warn("%s: Unknown error %lu\n", __func__, ret.error); + rc =3D -ENXIO; + break; + } + } + + pr_info("CPU %d: HW Breakpoint shared memory registered.\n", cpu); + + return rc; +} + +static int arch_smp_teardown_sbi_shmem(unsigned int cpu) +{ + struct sbiret ret; + + /* Disable shared memory */ + ret =3D sbi_ecall(SBI_EXT_DBTR, SBI_EXT_DBTR_SETUP_SHMEM, + -1UL, -1UL, 0, 0, 0, 0); + + if (ret.error) { + switch (ret.error) { + case SBI_ERR_DENIED: + pr_err("%s: Access denied for shared memory.\n", + __func__); + break; + + case SBI_ERR_INVALID_PARAM: + case SBI_ERR_INVALID_ADDRESS: + pr_err("%s: Invalid address parameter (%lu)\n", + __func__, ret.error); + break; + + case SBI_ERR_ALREADY_AVAILABLE: + pr_err("%s: Shared memory is already set\n", + __func__); + break; + case SBI_ERR_FAILURE: + pr_err("%s: Internal sdtrig state error\n", + __func__); + break; + default: + pr_err("%s: Unknown error %lu\n", __func__, ret.error); + break; + } + } + + pr_warn("CPU %d: HW Breakpoint shared memory disabled.\n", cpu); + + return 0; +} + +static void init_sbi_dbtr(void) +{ + unsigned long tdata1; + struct sbiret ret; + + if (sbi_probe_extension(SBI_EXT_DBTR) <=3D 0) { + pr_warn("%s: SBI_EXT_DBTR is not supported\n", __func__); + dbtr_total_num =3D 0; + goto done; + } + + ret =3D sbi_ecall(SBI_EXT_DBTR, SBI_EXT_DBTR_NUM_TRIGGERS, + 0, 0, 0, 0, 0, 0); + if (ret.error) { + pr_warn("%s: Failed to detect triggers\n", __func__); + dbtr_total_num =3D 0; + goto done; + } + + tdata1 =3D 0; + tdata1 =3D RV_DBTR_SET_TDATA1_TYPE(tdata1, RV_DBTR_TRIG_MCONTROL6); + + ret =3D sbi_ecall(SBI_EXT_DBTR, SBI_EXT_DBTR_NUM_TRIGGERS, + tdata1, 0, 0, 0, 0, 0); + if (ret.error) { + pr_warn("%s: failed to detect mcontrol6 triggers\n", __func__); + } else if (!ret.value) { + pr_warn("%s: type 6 triggers not available\n", __func__); + } else { + dbtr_total_num =3D ret.value; + dbtr_type =3D RV_DBTR_TRIG_MCONTROL6; + pr_warn("%s: mcontrol6 trigger available.\n", __func__); + goto done; + } + + /* fallback to type 2 triggers if type 6 is not available */ + + tdata1 =3D 0; + tdata1 =3D RV_DBTR_SET_TDATA1_TYPE(tdata1, RV_DBTR_TRIG_MCONTROL); + + ret =3D sbi_ecall(SBI_EXT_DBTR, SBI_EXT_DBTR_NUM_TRIGGERS, + tdata1, 0, 0, 0, 0, 0); + if (ret.error) { + pr_warn("%s: failed to detect mcontrol triggers\n", __func__); + } else if (!ret.value) { + pr_warn("%s: type 2 triggers not available\n", __func__); + } else { + dbtr_total_num =3D ret.value; + dbtr_type =3D RV_DBTR_TRIG_MCONTROL; + goto done; + } + +done: + dbtr_init =3D 1; +} + +int hw_breakpoint_slots(int type) +{ + /* + * We can be called early, so don't rely on + * static variables being initialised. + */ + + if (!dbtr_init) + init_sbi_dbtr(); + + return dbtr_total_num; +} + +int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw) +{ + unsigned int len; + unsigned long va; + + va =3D hw->address; + len =3D hw->len; + + return (va >=3D TASK_SIZE) && ((va + len - 1) >=3D TASK_SIZE); +} + +static int rv_init_mcontrol_trigger(const struct perf_event_attr *attr, + struct arch_hw_breakpoint *hw) +{ + switch (attr->bp_type) { + case HW_BREAKPOINT_X: + hw->type =3D RV_DBTR_BP; + RV_DBTR_SET_MC_EXEC_BIT(hw->tdata1); + break; + case HW_BREAKPOINT_R: + hw->type =3D RV_DBTR_WP; + RV_DBTR_SET_MC_LOAD_BIT(hw->tdata1); + break; + case HW_BREAKPOINT_W: + hw->type =3D RV_DBTR_WP; + RV_DBTR_SET_MC_STORE_BIT(hw->tdata1); + break; + case HW_BREAKPOINT_RW: + hw->type =3D RV_DBTR_WP; + RV_DBTR_SET_MC_LOAD_BIT(hw->tdata1); + RV_DBTR_SET_MC_STORE_BIT(hw->tdata1); + break; + default: + return -EINVAL; + } + + switch (attr->bp_len) { + case HW_BREAKPOINT_LEN_1: + hw->len =3D 1; + hw->tdata1 =3D RV_DBTR_SET_MC_SIZELO(hw->tdata1, 1); + break; + case HW_BREAKPOINT_LEN_2: + hw->len =3D 2; + hw->tdata1 =3D RV_DBTR_SET_MC_SIZELO(hw->tdata1, 2); + break; + case HW_BREAKPOINT_LEN_4: + hw->len =3D 4; + hw->tdata1 =3D RV_DBTR_SET_MC_SIZELO(hw->tdata1, 3); + break; +#if __riscv_xlen >=3D 64 + case HW_BREAKPOINT_LEN_8: + hw->len =3D 8; + hw->tdata1 =3D RV_DBTR_SET_MC_SIZELO(hw->tdata1, 1); + hw->tdata1 =3D RV_DBTR_SET_MC_SIZEHI(hw->tdata1, 1); + break; +#endif + default: + return -EINVAL; + } + + hw->tdata1 =3D RV_DBTR_SET_MC_TYPE(hw->tdata1, RV_DBTR_TRIG_MCONTROL); + + CLEAR_DBTR_BIT(hw->tdata1, MC, DMODE); + CLEAR_DBTR_BIT(hw->tdata1, MC, TIMING); + CLEAR_DBTR_BIT(hw->tdata1, MC, SELECT); + CLEAR_DBTR_BIT(hw->tdata1, MC, ACTION); + CLEAR_DBTR_BIT(hw->tdata1, MC, CHAIN); + CLEAR_DBTR_BIT(hw->tdata1, MC, MATCH); + CLEAR_DBTR_BIT(hw->tdata1, MC, M); + + SET_DBTR_BIT(hw->tdata1, MC, S); + SET_DBTR_BIT(hw->tdata1, MC, U); + + return 0; +} + +static int rv_init_mcontrol6_trigger(const struct perf_event_attr *attr, + struct arch_hw_breakpoint *hw) +{ + switch (attr->bp_type) { + case HW_BREAKPOINT_X: + hw->type =3D RV_DBTR_BP; + RV_DBTR_SET_MC6_EXEC_BIT(hw->tdata1); + break; + case HW_BREAKPOINT_R: + hw->type =3D RV_DBTR_WP; + RV_DBTR_SET_MC6_LOAD_BIT(hw->tdata1); + break; + case HW_BREAKPOINT_W: + hw->type =3D RV_DBTR_WP; + RV_DBTR_SET_MC6_STORE_BIT(hw->tdata1); + break; + case HW_BREAKPOINT_RW: + hw->type =3D RV_DBTR_WP; + RV_DBTR_SET_MC6_STORE_BIT(hw->tdata1); + RV_DBTR_SET_MC6_LOAD_BIT(hw->tdata1); + break; + default: + return -EINVAL; + } + + switch (attr->bp_len) { + case HW_BREAKPOINT_LEN_1: + hw->len =3D 1; + hw->tdata1 =3D RV_DBTR_SET_MC6_SIZE(hw->tdata1, 1); + break; + case HW_BREAKPOINT_LEN_2: + hw->len =3D 2; + hw->tdata1 =3D RV_DBTR_SET_MC6_SIZE(hw->tdata1, 2); + break; + case HW_BREAKPOINT_LEN_4: + hw->len =3D 4; + hw->tdata1 =3D RV_DBTR_SET_MC6_SIZE(hw->tdata1, 3); + break; + case HW_BREAKPOINT_LEN_8: + hw->len =3D 8; + hw->tdata1 =3D RV_DBTR_SET_MC6_SIZE(hw->tdata1, 5); + break; + default: + return -EINVAL; + } + + hw->tdata1 =3D RV_DBTR_SET_MC6_TYPE(hw->tdata1, RV_DBTR_TRIG_MCONTROL6); + + CLEAR_DBTR_BIT(hw->tdata1, MC6, DMODE); + CLEAR_DBTR_BIT(hw->tdata1, MC6, TIMING); + CLEAR_DBTR_BIT(hw->tdata1, MC6, SELECT); + CLEAR_DBTR_BIT(hw->tdata1, MC6, ACTION); + CLEAR_DBTR_BIT(hw->tdata1, MC6, CHAIN); + CLEAR_DBTR_BIT(hw->tdata1, MC6, MATCH); + CLEAR_DBTR_BIT(hw->tdata1, MC6, M); + CLEAR_DBTR_BIT(hw->tdata1, MC6, VS); + CLEAR_DBTR_BIT(hw->tdata1, MC6, VU); + + SET_DBTR_BIT(hw->tdata1, MC6, S); + SET_DBTR_BIT(hw->tdata1, MC6, U); + + return 0; +} + +int hw_breakpoint_arch_parse(struct perf_event *bp, + const struct perf_event_attr *attr, + struct arch_hw_breakpoint *hw) +{ + int ret; + + /* Breakpoint address */ + hw->address =3D attr->bp_addr; + hw->tdata2 =3D attr->bp_addr; + hw->tdata3 =3D 0x0; + + switch (dbtr_type) { + case RV_DBTR_TRIG_MCONTROL: + ret =3D rv_init_mcontrol_trigger(attr, hw); + break; + case RV_DBTR_TRIG_MCONTROL6: + ret =3D rv_init_mcontrol6_trigger(attr, hw); + break; + default: + pr_warn("unsupported trigger type\n"); + ret =3D -EOPNOTSUPP; + break; + } + + return ret; +} + +/* + * HW Breakpoint/watchpoint handler + */ +static int hw_breakpoint_handler(struct die_args *args) +{ + int ret =3D NOTIFY_DONE; + struct arch_hw_breakpoint *bp; + struct perf_event *event; + int i; + + for (i =3D 0; i < dbtr_total_num; i++) { + event =3D this_cpu_read(pcpu_hw_bp_events[i]); + if (!event) + continue; + + bp =3D counter_arch_bp(event); + switch (bp->type) { + /* Breakpoint */ + case RV_DBTR_BP: + if (bp->address =3D=3D args->regs->epc) { + perf_bp_event(event, args->regs); + ret =3D NOTIFY_STOP; + } + break; + + /* Watchpoint */ + case RV_DBTR_WP: + if (bp->address =3D=3D csr_read(CSR_STVAL)) { + perf_bp_event(event, args->regs); + ret =3D NOTIFY_STOP; + } + break; + + default: + pr_warn("%s: Unknown type: %u\n", __func__, bp->type); + break; + } + } + + return ret; +} + +int hw_breakpoint_exceptions_notify(struct notifier_block *unused, + unsigned long val, void *data) +{ + if (val !=3D DIE_DEBUG) + return NOTIFY_DONE; + + return hw_breakpoint_handler(data); +} + +/* atomic: counter->ctx->lock is held */ +int arch_install_hw_breakpoint(struct perf_event *event) +{ + struct arch_hw_breakpoint *bp =3D counter_arch_bp(event); + union sbi_dbtr_shmem_entry *shmem =3D this_cpu_ptr(sbi_dbtr_shmem); + struct sbi_dbtr_data_msg *xmit; + struct sbi_dbtr_id_msg *recv; + struct perf_event **slot; + unsigned long idx; + struct sbiret ret; + int err =3D 0; + + raw_spin_lock_irqsave(this_cpu_ptr(&ecall_lock), + *this_cpu_ptr(&ecall_lock_flags)); + + xmit =3D &shmem->data; + recv =3D &shmem->id; + xmit->tdata1 =3D cpu_to_le(bp->tdata1); + xmit->tdata2 =3D cpu_to_le(bp->tdata2); + xmit->tdata3 =3D cpu_to_le(bp->tdata3); + + ret =3D sbi_ecall(SBI_EXT_DBTR, SBI_EXT_DBTR_TRIG_INSTALL, + 1, 0, 0, 0, 0, 0); + + if (ret.error) { + pr_warn("%s: failed to install trigger\n", __func__); + err =3D -EIO; + goto done; + } + + idx =3D le_to_cpu(recv->idx); + if (idx >=3D dbtr_total_num) { + pr_warn("%s: invalid trigger index %lu\n", __func__, idx); + err =3D -EINVAL; + goto done; + } + + slot =3D this_cpu_ptr(&pcpu_hw_bp_events[idx]); + if (*slot) { + pr_warn("%s: slot %lu is in use\n", __func__, idx); + err =3D -EBUSY; + goto done; + } + + pr_debug("Trigger %lu installed at index 0x%lx\n", bp->tdata2, idx); + + /* Save the event - to be looked up in handler */ + *slot =3D event; + +done: + raw_spin_unlock_irqrestore(this_cpu_ptr(&ecall_lock), + *this_cpu_ptr(&ecall_lock_flags)); + return err; +} + +/* atomic: counter->ctx->lock is held */ +void arch_uninstall_hw_breakpoint(struct perf_event *event) +{ + struct sbiret ret; + int i; + + for (i =3D 0; i < dbtr_total_num; i++) { + struct perf_event **slot =3D this_cpu_ptr(&pcpu_hw_bp_events[i]); + + if (*slot =3D=3D event) { + *slot =3D NULL; + break; + } + } + + if (i =3D=3D dbtr_total_num) { + pr_warn("%s: Breakpoint not installed.\n", __func__); + return; + } + + ret =3D sbi_ecall(SBI_EXT_DBTR, SBI_EXT_DBTR_TRIG_UNINSTALL, + i, 1, 0, 0, 0, 0); + if (ret.error) + pr_warn("%s: Failed to uninstall trigger %d.\n", __func__, i); +} + +void arch_enable_hw_breakpoint(struct perf_event *event) +{ + struct sbiret ret; + int i; + struct perf_event **slot; + + for (i =3D 0; i < dbtr_total_num; i++) { + slot =3D this_cpu_ptr(&pcpu_hw_bp_events[i]); + + if (*slot =3D=3D event) + break; + } + + if (i =3D=3D dbtr_total_num) { + pr_warn("%s: Breakpoint not installed.\n", __func__); + return; + } + + ret =3D sbi_ecall(SBI_EXT_DBTR, SBI_EXT_DBTR_TRIG_ENABLE, + i, 1, 0, 0, 0, 0); + + if (ret.error) { + pr_warn("%s: Failed to install trigger %d\n", __func__, i); + return; + } +} +EXPORT_SYMBOL_GPL(arch_enable_hw_breakpoint); + +void arch_update_hw_breakpoint(struct perf_event *event) +{ + struct arch_hw_breakpoint *bp =3D counter_arch_bp(event); + union sbi_dbtr_shmem_entry *shmem =3D this_cpu_ptr(sbi_dbtr_shmem); + struct sbi_dbtr_data_msg *xmit; + struct perf_event **slot; + struct sbiret ret; + int i; + + for (i =3D 0; i < dbtr_total_num; i++) { + slot =3D this_cpu_ptr(&pcpu_hw_bp_events[i]); + + if (*slot =3D=3D event) + break; + } + + if (i =3D=3D dbtr_total_num) { + pr_warn("%s: Breakpoint not installed.\n", __func__); + return; + } + + raw_spin_lock_irqsave(this_cpu_ptr(&ecall_lock), + *this_cpu_ptr(&ecall_lock_flags)); + + xmit =3D &shmem->data; + xmit->tdata1 =3D cpu_to_le(bp->tdata1); + xmit->tdata2 =3D cpu_to_le(bp->tdata2); + xmit->tdata3 =3D cpu_to_le(bp->tdata3); + + ret =3D sbi_ecall(SBI_EXT_DBTR, SBI_EXT_DBTR_TRIG_UPDATE, + i, 1, 0, 0, 0, 0); + if (ret.error) + pr_warn("%s: Failed to update trigger %d.\n", __func__, i); + + raw_spin_unlock_irqrestore(this_cpu_ptr(&ecall_lock), + *this_cpu_ptr(&ecall_lock_flags)); +} +EXPORT_SYMBOL_GPL(arch_update_hw_breakpoint); + +void arch_disable_hw_breakpoint(struct perf_event *event) +{ + struct sbiret ret; + int i; + + for (i =3D 0; i < dbtr_total_num; i++) { + struct perf_event **slot =3D this_cpu_ptr(&pcpu_hw_bp_events[i]); + + if (*slot =3D=3D event) + break; + } + + if (i =3D=3D dbtr_total_num) { + pr_warn("%s: Breakpoint not installed.\n", __func__); + return; + } + + ret =3D sbi_ecall(SBI_EXT_DBTR, SBI_EXT_DBTR_TRIG_DISABLE, + i, 1, 0, 0, 0, 0); + + if (ret.error) { + pr_warn("%s: Failed to uninstall trigger %d.\n", __func__, i); + return; + } +} +EXPORT_SYMBOL_GPL(arch_disable_hw_breakpoint); + +void hw_breakpoint_pmu_read(struct perf_event *bp) +{ + /* TODO */ +} + +void clear_ptrace_hw_breakpoint(struct task_struct *tsk) +{ + /* TODO */ +} + +void flush_ptrace_hw_breakpoint(struct task_struct *tsk) +{ + /* TODO */ +} + +static int __init arch_hw_breakpoint_init(void) +{ + unsigned int cpu; + int rc =3D 0; + + for_each_possible_cpu(cpu) + raw_spin_lock_init(&per_cpu(ecall_lock, cpu)); + + if (!dbtr_init) + init_sbi_dbtr(); + + if (dbtr_total_num) { + pr_info("%s: total number of type %d triggers: %u\n", + __func__, dbtr_type, dbtr_total_num); + } else { + pr_info("%s: No hardware triggers available\n", __func__); + goto out; + } + + /* Allocate per-cpu shared memory */ + sbi_dbtr_shmem =3D __alloc_percpu(sizeof(*sbi_dbtr_shmem) * dbtr_total_nu= m, + PAGE_SIZE); + + if (!sbi_dbtr_shmem) { + pr_warn("%s: Failed to allocate shared memory.\n", __func__); + rc =3D -ENOMEM; + goto out; + } + + /* Hotplug handler to register/unregister shared memory with SBI */ + rc =3D cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, + "riscv/hw_breakpoint:prepare", + arch_smp_setup_sbi_shmem, + arch_smp_teardown_sbi_shmem); + + if (rc < 0) { + pr_warn("%s: Failed to setup CPU hotplug state\n", __func__); + free_percpu(sbi_dbtr_shmem); + return rc; + } + out: + return rc; +} +arch_initcall(arch_hw_breakpoint_init); diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 5fb57fad188a..3024abd26952 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -288,6 +288,12 @@ void handle_break(struct pt_regs *regs) if (probe_breakpoint_handler(regs)) return; =20 +#ifdef CONFIG_HAVE_HW_BREAKPOINT + if (notify_die(DIE_DEBUG, "EBREAK", regs, 0, regs->cause, SIGTRAP) + =3D=3D NOTIFY_STOP) + return; +#endif + current->thread.bad_cause =3D regs->cause; =20 if (user_mode(regs)) --=20 2.43.0 From nobody Sat Apr 11 07:35:02 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A62B137750 for ; Mon, 23 Feb 2026 04:49:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-358a2a768bcsm5623954a91.4.2026.02.22.20.49.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Feb 2026 20:49:34 -0800 (PST) From: Himanshu Chauhan To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, shuah@kernel.org Cc: Himanshu Chauhan Subject: [PATCH v3 2/2] riscv: Add breakpoint and watchpoint test for riscv Date: Mon, 23 Feb 2026 10:19:18 +0530 Message-ID: <20260223044918.1359983-3-himanshu.chauhan@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260223044918.1359983-1-himanshu.chauhan@oss.qualcomm.com> References: <20260223044918.1359983-1-himanshu.chauhan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjIzMDA0MCBTYWx0ZWRfX2pkSYEhaEhmf aWo9uJmG9Zl6cjdqAhzpRAkKmerKeA2ZZD/tnh1+s6Z1HGhkvHxX+s+9wyBj+VrMZ82bgtmYhiv TgZLzRbq44q2Aytpr7wwSBCS+nnIBT47wCxo/mwdgNru5yrvHX+M/WxM+4aC2xRlADnBXGStJMq rgpfhq2XjLbyfiIVgGDOgG0H4ilzcx0CfTLKjYHbtecM5QmgC4jSSUq6Vc3W3BnfytSkRvi1ub9 Od4y9ndjvvqh58HRyo6QH81h0PucXjzJ+HiuZIZb/W+AGkpR3aSyFiT0osBVeZQCLoHXTrqc+gq WPcT/HCrw519IgjDy+YAXmyKM3xtm7JgD4MNpUWSd9TuYX8Ekk5MV6mH36VLwWPk3wvv5kHzoki EE0UBLtYhJHhHlX4U7L/P/rM/vfX6uwfoBFxqjIpw6PTsRWCtLPf8VSK2m2KYwtmhAJhlY/tdM6 fLFysbLxRNM0R4ePFPw== X-Authority-Analysis: v=2.4 cv=UO/Q3Sfy c=1 sm=1 tr=0 ts=699bdc60 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=nrFWDfrXf5gqSM9dz-wA:9 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-GUID: 5rm4Dz1X-v_eclUtT1NoPJuyWZClsCoU X-Proofpoint-ORIG-GUID: 5rm4Dz1X-v_eclUtT1NoPJuyWZClsCoU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-23_01,2026-02-20_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 bulkscore=0 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602230040 Content-Type: text/plain; charset="utf-8" Add self test for riscv architecture. It uses ptrace to ptrace framework to set/unset break/watchpoint and uses signals to check triggers. Signed-off-by: Himanshu Chauhan --- tools/testing/selftests/breakpoints/Makefile | 5 + .../breakpoints/breakpoint_test_riscv.c | 174 ++++++++++++++++++ 2 files changed, 179 insertions(+) create mode 100644 tools/testing/selftests/breakpoints/breakpoint_test_ris= cv.c diff --git a/tools/testing/selftests/breakpoints/Makefile b/tools/testing/s= elftests/breakpoints/Makefile index 9ec2c78de8ca..97ab746908d8 100644 --- a/tools/testing/selftests/breakpoints/Makefile +++ b/tools/testing/selftests/breakpoints/Makefile @@ -12,5 +12,10 @@ ifneq (,$(filter $(ARCH),aarch64 arm64)) TEST_GEN_PROGS +=3D breakpoint_test_arm64 endif =20 +ifneq (,$(filter $(ARCH),riscv)) +CFLAGS +=3D -static +TEST_GEN_PROGS +=3D breakpoint_test_riscv +endif + include ../lib.mk =20 diff --git a/tools/testing/selftests/breakpoints/breakpoint_test_riscv.c b/= tools/testing/selftests/breakpoints/breakpoint_test_riscv.c new file mode 100644 index 000000000000..e07f6fb1cfbd --- /dev/null +++ b/tools/testing/selftests/breakpoints/breakpoint_test_riscv.c @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 Qualcomm Technologies, Inc. + * + * Author: Himanshu Chauhan + */ + +#define _GNU_SOURCE +#include /* Definition of PERF_* constants */ +#include /* Definition of HW_* constants */ +#include /* Definition of SYS_* constants */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int gfd; +sem_t ib_mtx, wp_mtx; +static int bp_triggered, wp_triggered; + +int setup_bp(bool is_x, void *addr, int sig) +{ + struct perf_event_attr pe; + int fd; + + memset(&pe, 0, sizeof(struct perf_event_attr)); + pe.type =3D PERF_TYPE_BREAKPOINT; + pe.size =3D sizeof(struct perf_event_attr); + + pe.config =3D 0; + pe.bp_type =3D is_x ? HW_BREAKPOINT_X : HW_BREAKPOINT_W; + pe.bp_addr =3D (unsigned long)addr; + pe.bp_len =3D sizeof(long); + + pe.sample_period =3D 1; + pe.sample_type =3D PERF_SAMPLE_IP; + pe.wakeup_events =3D 1; + + pe.disabled =3D 1; + pe.exclude_kernel =3D 1; + pe.exclude_hv =3D 1; + + fd =3D syscall(SYS_perf_event_open, &pe, 0, -1, -1, 0); + if (fd < 0) { + printf("Failed to open event: %llx\n", pe.config); + return -1; + } + + fcntl(fd, F_SETFL, O_RDWR | O_NONBLOCK | O_ASYNC); + fcntl(fd, F_SETSIG, sig); + fcntl(fd, F_SETOWN, getpid()); + + ioctl(fd, PERF_EVENT_IOC_RESET, 0); + + return fd; +} + +static void sig_handler_bp(int signum, siginfo_t *oh, void *uc) +{ + int ret; + + bp_triggered++; + + printf("Breakpoint triggered!\n"); + ioctl(gfd, PERF_EVENT_IOC_DISABLE, 0); + ret =3D sem_post(&ib_mtx); + if (ret) { + printf("Failed to report BP success\n"); + return; + } +} + +static void sig_handler_wp(int signum, siginfo_t *oh, void *uc) +{ + int ret; + + printf("Watchpoint triggered!\n"); + ioctl(gfd, PERF_EVENT_IOC_DISABLE, 0); + wp_triggered++; + + ret =3D sem_post(&wp_mtx); + + if (ret) { + printf("Failed to report WP success\n"); + return; + } +} + +static void test_func(void) +{ +} + +static int trigger_bp(void) +{ + struct sigaction sa; + + memset(&sa, 0, sizeof(struct sigaction)); + sa.sa_sigaction =3D (void *)sig_handler_bp; + sa.sa_flags =3D SA_SIGINFO; + + if (sigaction(SIGIO, &sa, NULL) < 0) { + printf("Failed to setup signal handler\n"); + return -1; + } + + gfd =3D setup_bp(1, test_func, SIGIO); + + if (gfd < 0) { + printf("Failed to setup breakpoint.\n"); + return -1; + } + + ioctl(gfd, PERF_EVENT_IOC_ENABLE, 0); + + test_func(); + + ioctl(gfd, PERF_EVENT_IOC_DISABLE, 0); + + close(gfd); +} + +static int trigger_wp(void) +{ + struct sigaction sa; + unsigned long test_data; + + memset(&sa, 0, sizeof(struct sigaction)); + sa.sa_sigaction =3D (void *)sig_handler_wp; + sa.sa_flags =3D SA_SIGINFO; + + if (sigaction(SIGUSR1, &sa, NULL) < 0) { + printf("Failed to setup signal handler\n"); + return -1; + } + + gfd =3D setup_bp(0, &test_data, SIGUSR1); + + if (gfd < 0) { + printf("Failed to setup watchpoint\n"); + return -1; + } + + ioctl(gfd, PERF_EVENT_IOC_ENABLE, 0); + test_data =3D 0xdeadbeef; + ioctl(gfd, PERF_EVENT_IOC_DISABLE, 0); +} + +int main(int argc, char *argv[]) +{ + struct sigaction sa; + + sem_init(&ib_mtx, 0, 0); + trigger_bp(); + sem_wait(&ib_mtx); + + if (bp_triggered) + printf("Breakpoint test passed!\n"); + + sem_init(&wp_mtx, 0, 0); + trigger_wp(); + sem_wait(&wp_mtx); + + if (wp_triggered) + printf("Watchpoint test passed!\n"); + + return 0; +} --=20 2.43.0