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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ad74f619f8sm62249225ad.36.2026.02.22.22.56.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Feb 2026 22:56:17 -0800 (PST) From: Jie Gan Date: Mon, 23 Feb 2026 14:55:41 +0800 Subject: [PATCH v13 1/8] coresight: core: Refactoring ctcu_get_active_port and make it generic Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260223-enable-byte-cntr-for-ctcu-v13-1-9cb44178b250@oss.qualcomm.com> References: <20260223-enable-byte-cntr-for-ctcu-v13-0-9cb44178b250@oss.qualcomm.com> In-Reply-To: <20260223-enable-byte-cntr-for-ctcu-v13-0-9cb44178b250@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tingwei Zhang , Mao Jinlong , Bjorn Andersson , Konrad Dybcio Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Jie Gan , Mike Leach X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771829765; l=3771; i=jie.gan@oss.qualcomm.com; s=20250909; h=from:subject:message-id; bh=nzaF2yP3ATiqQC37LSxmXVL9MqWLOY4wwOUNTmvz/UA=; b=94yEoy4nSurylGbRJ0V5DPEndCwAjFuBsRD2bm90sDL2wEYpjo+ftcY8uF8dOdxn5+dK39Pel aqeOr/cHOkmDuryVpmHsj9VAY7E/kW2NMP6mlBzkXRgdZD//Fi9xYV4 X-Developer-Key: i=jie.gan@oss.qualcomm.com; a=ed25519; pk=3LxxUZRPCNkvPDlWOvXfJNqNO4SfGdy3eghMb8puHuk= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjIzMDA1OSBTYWx0ZWRfX9OGd8D8ObUXF v0e1Yhm0FnFOmxvEJL2mmmwGAEf4bYy5+FzBqga6J1g33ABk5+VuOdsJyqjZ2dyPLwftgMepFtR v+jKpudBysbFe+/zCbuyrt2jv/ZUbEuT0eXRqPGM5T+Fhxx9FMxTsQZbWnlZbA9FR2M3EFRCjBy G/v4BlRliYU/VIzOPxdsKFjd/mZ5HWiFClIG0gQJkrsAi6rlKkJ1DCrmtCQ9/s8Mx56GCYu6BlW 7JeIrmYE+aFpTCJKz4lUdGREkhMTrP6H9RUWcAsLDzpSzJ9y2BdNJPpS9/iFSIz82mDcME+CPVP g0jTNFxhbG58XhjK4EQSX7Eup0I1GWRG+tOdnSDBIdc2cbK3sTG0OG32NOHnnG6cequCxmJzv4c f4dGWJ6z61Q/sVR6TlOsiZK2/X5KUgXUeN2i1pYWouujaMdPsLZcyhvk/8ecZEX6Ex2rqBmDAhm ybN7umLo6qfWbjum7yw== X-Authority-Analysis: v=2.4 cv=T5KBjvKQ c=1 sm=1 tr=0 ts=699bfa13 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=qQZ2XtAyJf2dEkEvaVsA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: GrnXHZ-8a2A5lW8PKwYHKt1lwVcm6LLC X-Proofpoint-ORIG-GUID: GrnXHZ-8a2A5lW8PKwYHKt1lwVcm6LLC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-23_01,2026-02-20_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 phishscore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602230059 Remove ctcu_get_active_port from CTCU module and add it to the core framework. The port number is crucial for the CTCU device to identify which ETR it serves. With the port number we can correctly get required parameters of the CTCU device in TMC module. Reviewed-by: Mike Leach Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/coresight-core.c | 24 +++++++++++++++++++= ++++ drivers/hwtracing/coresight/coresight-ctcu-core.c | 19 +----------------- drivers/hwtracing/coresight/coresight-priv.h | 2 ++ 3 files changed, 27 insertions(+), 18 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtraci= ng/coresight/coresight-core.c index c660cf8adb1c..5f55f0c510e4 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -585,6 +585,30 @@ struct coresight_device *coresight_get_sink(struct cor= esight_path *path) } EXPORT_SYMBOL_GPL(coresight_get_sink); =20 +/** + * coresight_get_in_port: Find the input port number at @remote where the = @csdev + * device is connected to. + * + * @csdev: csdev of the device. + * @remote: csdev of the remote device which is connected to @csdev. + * + * Return: port number upon success or -EINVAL for fail. + */ +int coresight_get_in_port(struct coresight_device *csdev, + struct coresight_device *remote) +{ + struct coresight_platform_data *pdata =3D remote->pdata; + int i; + + for (i =3D 0; i < pdata->nr_inconns; ++i) { + if (pdata->in_conns[i]->src_dev =3D=3D csdev) + return pdata->in_conns[i]->dest_port; + } + + return -EINVAL; +} +EXPORT_SYMBOL_GPL(coresight_get_in_port); + u32 coresight_get_sink_id(struct coresight_device *csdev) { if (!csdev->ea) diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hw= tracing/coresight/coresight-ctcu-core.c index abed15eb72b4..78be783b3cb2 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu-core.c +++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c @@ -118,23 +118,6 @@ static int __ctcu_set_etr_traceid(struct coresight_dev= ice *csdev, u8 traceid, in return 0; } =20 -/* - * Searching the sink device from helper's view in case there are multiple= helper devices - * connected to the sink device. - */ -static int ctcu_get_active_port(struct coresight_device *sink, struct core= sight_device *helper) -{ - struct coresight_platform_data *pdata =3D helper->pdata; - int i; - - for (i =3D 0; i < pdata->nr_inconns; ++i) { - if (pdata->in_conns[i]->src_dev =3D=3D sink) - return pdata->in_conns[i]->dest_port; - } - - return -EINVAL; -} - static int ctcu_set_etr_traceid(struct coresight_device *csdev, struct cor= esight_path *path, bool enable) { @@ -147,7 +130,7 @@ static int ctcu_set_etr_traceid(struct coresight_device= *csdev, struct coresight return -EINVAL; } =20 - port_num =3D ctcu_get_active_port(sink, csdev); + port_num =3D coresight_get_in_port(sink, csdev); if (port_num < 0) return -EINVAL; =20 diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtraci= ng/coresight/coresight-priv.h index fd896ac07942..cbf80b83e5ce 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -155,6 +155,8 @@ void coresight_remove_links(struct coresight_device *or= ig, u32 coresight_get_sink_id(struct coresight_device *csdev); void coresight_path_assign_trace_id(struct coresight_path *path, enum cs_mode mode); +int coresight_get_in_port(struct coresight_device *csdev, + struct coresight_device *remote); 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ad74f619f8sm62249225ad.36.2026.02.22.22.56.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Feb 2026 22:56:22 -0800 (PST) From: Jie Gan Date: Mon, 23 Feb 2026 14:55:42 +0800 Subject: [PATCH v13 2/8] coresight: tmc: add create/clean functions for etr_buf_list Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260223-enable-byte-cntr-for-ctcu-v13-2-9cb44178b250@oss.qualcomm.com> References: <20260223-enable-byte-cntr-for-ctcu-v13-0-9cb44178b250@oss.qualcomm.com> In-Reply-To: <20260223-enable-byte-cntr-for-ctcu-v13-0-9cb44178b250@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tingwei Zhang , Mao Jinlong , Bjorn Andersson , Konrad Dybcio Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Jie Gan , Mike Leach X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771829766; l=6164; i=jie.gan@oss.qualcomm.com; s=20250909; h=from:subject:message-id; bh=fR8lvHhL4oSY/n5eSl541nai+feNwPd8lhB8kmyGxEU=; b=TAasXX83LQMCDwpga9xn06zrx2OoGZ2NngshkxWMFt8//DaX67J1pXx4PXUmtHwqDy374Amms e1JXTevSTNOAkkHxIt4ga6716mNRdc4HbZbCMQgS2pUGjPECOovKf4N X-Developer-Key: i=jie.gan@oss.qualcomm.com; a=ed25519; pk=3LxxUZRPCNkvPDlWOvXfJNqNO4SfGdy3eghMb8puHuk= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjIzMDA1OSBTYWx0ZWRfX3fDDYL1xYYYp i8JqtKCqLvOUq/guho4icQJXqrcfPZIxN3jjyoUKmcvfPBcyt5unfmYBNpziWh0f4nLHyrfdD// Wjd66FGoWsMgEerXq3/WDSedujO7MuvSk+6+daWUIE5kpdsoFKjK5iuIOhxs7mmZy88E81ba1iN AdkhRSzS7KHVbDtTdiNgNGd9vLcQfNtS4IUdEhVTPciLhCQeC1prV2CsJhcsksNKyjchP58M62l cX+IJTePMO75g1tCMclKAhvOVs9aG6mAglq7/LkBXU4ppUb3mDrzB/57VoIkYdrTT39DKqzwnto ObciZXRPN/lGIL0dIvRkF7AQzw0Zr+MUUoGsS+IF5MS2lbVwzDrW93Kvj2PyDzbEYGbklF92907 LudzoFTvjm0bFq65NQEc0aOXM+XUc796JRZYj/66eeDS+Vp7F++RxSuN0q36WXJnM0WivKB5zuw uStP6A8RxJ/6gMwoIdQ== X-Authority-Analysis: v=2.4 cv=UO/Q3Sfy c=1 sm=1 tr=0 ts=699bfa19 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=pN8Znu5onTEf3dnVCfUA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: kF9Tb1d_vRVD7VdzsTT-_4JV4wy_p0T1 X-Proofpoint-ORIG-GUID: kF9Tb1d_vRVD7VdzsTT-_4JV4wy_p0T1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-23_01,2026-02-20_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 bulkscore=0 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602230059 Introduce functions for creating and inserting or removing the etr_buf_node to/from the etr_buf_list. The byte-cntr functionality requires two etr_buf to receive trace data. The active etr_buf collects the trace data from source device, while the byte-cntr reading function accesses the deactivated etr_buf after is has been filled and synced, transferring data to the userspace. Reviewed-by: Mike Leach Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/coresight-tmc-core.c | 1 + drivers/hwtracing/coresight/coresight-tmc-etr.c | 94 ++++++++++++++++++++= ++++ drivers/hwtracing/coresight/coresight-tmc.h | 19 +++++ 3 files changed, 114 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index 36599c431be6..1ea255ffa67c 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -840,6 +840,7 @@ static int __tmc_probe(struct device *dev, struct resou= rce *res) idr_init(&drvdata->idr); mutex_init(&drvdata->idr_mutex); dev_list =3D &etr_devs; + INIT_LIST_HEAD(&drvdata->etr_buf_list); break; case TMC_CONFIG_TYPE_ETF: desc.groups =3D coresight_etf_groups; diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index cee82e52c4ea..081498162011 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1920,6 +1920,100 @@ const struct coresight_ops tmc_etr_cs_ops =3D { .panic_ops =3D &tmc_etr_sync_ops, }; =20 +/** + * tmc_clean_etr_buf_list - clean the etr_buf_list. + * @drvdata: driver data of the TMC device. + * + * Remove the allocated node from the list and free the extra buffer. + */ +void tmc_clean_etr_buf_list(struct tmc_drvdata *drvdata) +{ + struct etr_buf_node *nd, *next; + + list_for_each_entry_safe(nd, next, &drvdata->etr_buf_list, node) { + if (nd->sysfs_buf =3D=3D drvdata->sysfs_buf) { + if (coresight_get_mode(drvdata->csdev) =3D=3D CS_MODE_DISABLED) { + drvdata->sysfs_buf =3D NULL; + tmc_free_etr_buf(nd->sysfs_buf); + nd->sysfs_buf =3D NULL; + } + list_del(&nd->node); + kfree(nd); + } else { + /* Free allocated buffers which are not utilized by ETR */ + list_del(&nd->node); + tmc_free_etr_buf(nd->sysfs_buf); + nd->sysfs_buf =3D NULL; + kfree(nd); + } + } +} +EXPORT_SYMBOL_GPL(tmc_clean_etr_buf_list); + +/** + * tmc_create_etr_buf_list - create a list to manage the etr_buf_node. + * @drvdata: driver data of the TMC device. + * @num_nodes: number of nodes want to create with the list. + * + * Return 0 upon success and return the error number if fail. + */ +int tmc_create_etr_buf_list(struct tmc_drvdata *drvdata, int num_nodes) +{ + struct etr_buf_node *new_node; + struct etr_buf *sysfs_buf; + int i =3D 0, ret =3D 0; + + /* We dont need a list if there is only one node */ + if (num_nodes < 2) + return -EINVAL; + + /* We expect that sysfs_buf in drvdata has already been allocated. */ + if (drvdata->sysfs_buf) { + /* Directly insert the allocated sysfs_buf into the list first */ + new_node =3D kzalloc_obj(*new_node, GFP_KERNEL); + if (IS_ERR(new_node)) + return PTR_ERR(new_node); + + new_node->sysfs_buf =3D drvdata->sysfs_buf; + new_node->is_free =3D false; + list_add(&new_node->node, &drvdata->etr_buf_list); + i++; + } + + while (i < num_nodes) { + new_node =3D kzalloc_obj(*new_node, GFP_KERNEL); + if (IS_ERR(new_node)) { + ret =3D PTR_ERR(new_node); + break; + } + + sysfs_buf =3D tmc_alloc_etr_buf(drvdata, drvdata->size, 0, cpu_to_node(0= ), NULL); + if (IS_ERR(sysfs_buf)) { + kfree(new_node); + ret =3D PTR_ERR(sysfs_buf); + break; + } + + /* We dont have a available sysfs_buf in drvdata, setup one */ + if (!drvdata->sysfs_buf) { + drvdata->sysfs_buf =3D sysfs_buf; + new_node->is_free =3D false; + } else + new_node->is_free =3D true; + + new_node->sysfs_buf =3D sysfs_buf; + list_add(&new_node->node, &drvdata->etr_buf_list); + i++; + } + + /* Clean the list if there is an error */ + if (ret) + tmc_clean_etr_buf_list(drvdata); + + return ret; +} +EXPORT_SYMBOL_GPL(tmc_create_etr_buf_list); + int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) { int ret =3D 0; diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index 319a354ede9f..57d8394d09b7 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -208,6 +208,19 @@ struct tmc_resrv_buf { s64 len; }; =20 +/** + * @sysfs_buf: Allocated sysfs_buf. + * @is_free: Indicates whether the buffer is free to choose. + * @pos: Position of the buffer. + * @node: Node in etr_buf_list. + */ +struct etr_buf_node { + struct etr_buf *sysfs_buf; + bool is_free; + loff_t pos; + struct list_head node; +}; + /** * struct tmc_drvdata - specifics associated to an TMC component * @atclk: optional clock for the core parts of the TMC. @@ -245,6 +258,8 @@ struct tmc_resrv_buf { * (after crash) by default. * @crash_mdata: Reserved memory for storing tmc crash metadata. * Used by ETR/ETF. + * @etr_buf_list: List that is used to manage allocated etr_buf. + * @reading_node: Available buffer_node for byte-cntr reading. */ struct tmc_drvdata { struct clk *atclk; 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Reviewed-by: Mike Leach Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/coresight-tmc-core.c | 51 ++++++++++----------= ---- drivers/hwtracing/coresight/coresight-tmc.h | 15 +++++++ 2 files changed, 37 insertions(+), 29 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index 1ea255ffa67c..32ca2ec994de 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -232,17 +232,10 @@ static int tmc_read_prepare(struct tmc_drvdata *drvda= ta) { int ret =3D 0; =20 - switch (drvdata->config_type) { - case TMC_CONFIG_TYPE_ETB: - case TMC_CONFIG_TYPE_ETF: - ret =3D tmc_read_prepare_etb(drvdata); - break; - case TMC_CONFIG_TYPE_ETR: - ret =3D tmc_read_prepare_etr(drvdata); - break; - default: + if (drvdata->sysfs_ops) + ret =3D drvdata->sysfs_ops->read_prepare(drvdata); + else ret =3D -EINVAL; - } =20 if (!ret) dev_dbg(&drvdata->csdev->dev, "TMC read start\n"); @@ -254,17 +247,10 @@ static int tmc_read_unprepare(struct tmc_drvdata *drv= data) { int ret =3D 0; =20 - switch (drvdata->config_type) { - case TMC_CONFIG_TYPE_ETB: - case TMC_CONFIG_TYPE_ETF: - ret =3D tmc_read_unprepare_etb(drvdata); - break; - case TMC_CONFIG_TYPE_ETR: - ret =3D tmc_read_unprepare_etr(drvdata); - break; - default: + if (drvdata->sysfs_ops) + ret =3D drvdata->sysfs_ops->read_unprepare(drvdata); + else ret =3D -EINVAL; - } =20 if (!ret) dev_dbg(&drvdata->csdev->dev, "TMC read end\n"); @@ -291,15 +277,7 @@ static int tmc_open(struct inode *inode, struct file *= file) static ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata, loff_t pos= , size_t len, char **bufpp) { - switch (drvdata->config_type) { - case TMC_CONFIG_TYPE_ETB: - case TMC_CONFIG_TYPE_ETF: - return tmc_etb_get_sysfs_trace(drvdata, pos, len, bufpp); - case TMC_CONFIG_TYPE_ETR: - return tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp); - } - - return -EINVAL; + return drvdata->sysfs_ops->get_trace_data(drvdata, pos, len, bufpp); } =20 static ssize_t tmc_read(struct file *file, char __user *data, size_t len, @@ -769,6 +747,18 @@ static void register_crash_dev_interface(struct tmc_dr= vdata *drvdata, "Valid crash tracedata found\n"); } =20 +static const struct tmc_sysfs_ops etb_sysfs_ops =3D { + .read_prepare =3D tmc_read_prepare_etb, + .read_unprepare =3D tmc_read_unprepare_etb, + .get_trace_data =3D tmc_etb_get_sysfs_trace, +}; + +static const struct tmc_sysfs_ops etr_sysfs_ops =3D { + .read_prepare =3D tmc_read_prepare_etr, + .read_unprepare =3D tmc_read_unprepare_etr, + .get_trace_data =3D tmc_etr_get_sysfs_trace, +}; + static int __tmc_probe(struct device *dev, struct resource *res) { int ret =3D 0; @@ -828,6 +818,7 @@ static int __tmc_probe(struct device *dev, struct resou= rce *res) desc.subtype.sink_subtype =3D CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; desc.ops =3D &tmc_etb_cs_ops; dev_list =3D &etb_devs; + drvdata->sysfs_ops =3D &etb_sysfs_ops; break; case TMC_CONFIG_TYPE_ETR: desc.groups =3D coresight_etr_groups; @@ -841,6 +832,7 @@ static int __tmc_probe(struct device *dev, struct resou= rce *res) mutex_init(&drvdata->idr_mutex); dev_list =3D &etr_devs; INIT_LIST_HEAD(&drvdata->etr_buf_list); + drvdata->sysfs_ops =3D &etr_sysfs_ops; break; case TMC_CONFIG_TYPE_ETF: desc.groups =3D coresight_etf_groups; @@ -849,6 +841,7 @@ static int __tmc_probe(struct device *dev, struct resou= rce *res) desc.subtype.link_subtype =3D CORESIGHT_DEV_SUBTYPE_LINK_FIFO; desc.ops =3D &tmc_etf_cs_ops; dev_list =3D &etf_devs; + drvdata->sysfs_ops =3D &etb_sysfs_ops; break; default: pr_err("%s: Unsupported TMC config\n", desc.name); diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index 57d8394d09b7..92ffaf771fea 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -260,6 +260,7 @@ struct etr_buf_node { * Used by ETR/ETF. * @etr_buf_list: List that is used to manage allocated etr_buf. * @reading_node: Available buffer_node for byte-cntr reading. + * @sysfs_ops: Read operations for sysfs mode. */ struct tmc_drvdata { struct clk *atclk; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ad74f619f8sm62249225ad.36.2026.02.22.22.56.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Feb 2026 22:56:33 -0800 (PST) From: Jie Gan Date: Mon, 23 Feb 2026 14:55:44 +0800 Subject: [PATCH v13 4/8] coresight: etr: add a new function to retrieve the CTCU device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260223-enable-byte-cntr-for-ctcu-v13-4-9cb44178b250@oss.qualcomm.com> References: <20260223-enable-byte-cntr-for-ctcu-v13-0-9cb44178b250@oss.qualcomm.com> In-Reply-To: <20260223-enable-byte-cntr-for-ctcu-v13-0-9cb44178b250@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tingwei Zhang , Mao Jinlong , Bjorn Andersson , Konrad Dybcio Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Jie Gan X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771829766; l=2348; i=jie.gan@oss.qualcomm.com; s=20250909; h=from:subject:message-id; bh=XbEF7lfm+dBjOkALDpKb/LLjuMBdmQi6ikgLxJ96uLY=; b=QJIHdDQoxMLI/29FPVLu0wdWv1rJIOmKOHjVUElhbthI9G7PX5B7KPuwGLB5111xzHa2ft75Y TyCCmRN9yxDAGDLW+yMFfP00U/IFyqq2+LFPAEf2aYHWye/yebQipbE X-Developer-Key: i=jie.gan@oss.qualcomm.com; a=ed25519; pk=3LxxUZRPCNkvPDlWOvXfJNqNO4SfGdy3eghMb8puHuk= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjIzMDA1OSBTYWx0ZWRfX0wrsBf/3hF/u xlQ7ekul2R4BJuFCXWhFINgbkGIQZGL/AQHmeYGH9Q2KlW59G7gUg7iOwZS6dRNSTwzSUSV7A4a doK7tFBwwJ6QFlTIU66r1tqXIZAdcGr94HMysodtMfNWrCYRloPSRCbz/FM9oK1KhkvXWs33QOA Sa+g0bOwAO8YTPQRKf2uMvyHor3NgD93KpvTEunNSclRc0nCNRpSXPQmnlZS5Q2oz9aHkrU0Tr5 IZIReXRkgqaQGZ/KDoimyNyHmrWZd7ufmPNGDA/PX7W63PcWDZssNxx8t/Ym/QdqLazZnV3FbaX 0pVuiqHRwf70A8hmtNu5ZXnLDTsO/gCAkzkFhv5pGw5p7G1+bHRSm59v87lGieDTs2ZLCVdsv4/ liXi6T3IXDvsW/Zmcp/xxgVlEBQE6OuUGxg5R4ot9WrXqeLIAs5wSJc3+mbkqPTRSHQTLsEPxQR eJDakXORcMqcuZ4UHeA== X-Proofpoint-GUID: agOflsvf8YeuEZd9LvJY-40d7CIXefTN X-Authority-Analysis: v=2.4 cv=X71f6WTe c=1 sm=1 tr=0 ts=699bfa24 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=FuIWbRVyn4pKkvqW11oA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-ORIG-GUID: agOflsvf8YeuEZd9LvJY-40d7CIXefTN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-23_01,2026-02-20_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 priorityscore=1501 adultscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 spamscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602230059 Add tmc_etr_get_ctcu_device function to find the ptr of the coresight_device of the CTCU device if the CTCU device is connected to the TMC ETR device. Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 24 +++++++++++++++++++++= +++ drivers/hwtracing/coresight/coresight-tmc.h | 1 + 2 files changed, 25 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index 081498162011..32353980964a 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -867,6 +867,30 @@ tmc_etr_get_catu_device(struct tmc_drvdata *drvdata) } EXPORT_SYMBOL_GPL(tmc_etr_get_catu_device); =20 +/* + * TMC ETR could be connected to a CTCU device, which can provide ATID fil= ter + * and byte-cntr service. This is represented by the output port of the TMC + * (ETR) connected to the input port of the CTCU. + * + * Retruns : coresight_device ptr for the CTCU device if a CTCU is found. + * : NULL otherwise. + */ +struct coresight_device * +tmc_etr_get_ctcu_device(struct tmc_drvdata *drvdata) +{ + struct coresight_device *etr =3D drvdata->csdev; + union coresight_dev_subtype ctcu_subtype =3D { + .helper_subtype =3D CORESIGHT_DEV_SUBTYPE_HELPER_CTCU + }; + + if (!IS_ENABLED(CONFIG_CORESIGHT_CTCU)) + return NULL; + + return coresight_find_output_type(etr->pdata, CORESIGHT_DEV_TYPE_HELPER, + ctcu_subtype); +} +EXPORT_SYMBOL_GPL(tmc_etr_get_ctcu_device); + static const struct etr_buf_operations *etr_buf_ops[] =3D { [ETR_MODE_FLAT] =3D &etr_flat_buf_ops, [ETR_MODE_ETR_SG] =3D &etr_sg_buf_ops, diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index 92ffaf771fea..27dd72065c60 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -472,6 +472,7 @@ static inline uint32_t find_crash_tracedata_crc(struct = tmc_drvdata *drvdata, } =20 struct coresight_device *tmc_etr_get_catu_device(struct tmc_drvdata *drvda= ta); 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The interrupt will be triggered when the data size in the ETR buffer exceeds the threshold of the BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL register of CTCU device will enable the interrupt. Acked-by: Krzysztof Kozlowski Reviewed-by: Mike Leach Signed-off-by: Jie Gan --- Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 10 ++++++= ++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml= b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml index e002f87361ad..2981001a7d7f 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml @@ -44,6 +44,11 @@ properties: items: - const: apb =20 + interrupts: + items: + - description: Interrupt for the ETR device connected to in-port0. + - description: Interrupt for the ETR device connected to in-port1. + label: description: Description of a coresight device. @@ -65,6 +70,8 @@ additionalProperties: false =20 examples: - | + #include + ctcu@1001000 { compatible =3D "qcom,sa8775p-ctcu"; reg =3D <0x1001000 0x1000>; @@ -72,6 +79,9 @@ examples: clocks =3D <&aoss_qmp>; clock-names =3D "apb"; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ad74f619f8sm62249225ad.36.2026.02.22.22.56.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Feb 2026 22:56:44 -0800 (PST) From: Jie Gan Date: Mon, 23 Feb 2026 14:55:46 +0800 Subject: [PATCH v13 6/8] coresight: ctcu: enable byte-cntr for TMC ETR devices Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260223-enable-byte-cntr-for-ctcu-v13-6-9cb44178b250@oss.qualcomm.com> References: <20260223-enable-byte-cntr-for-ctcu-v13-0-9cb44178b250@oss.qualcomm.com> In-Reply-To: <20260223-enable-byte-cntr-for-ctcu-v13-0-9cb44178b250@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tingwei Zhang , Mao Jinlong , Bjorn Andersson , Konrad Dybcio Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Jie Gan X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771829766; l=24560; i=jie.gan@oss.qualcomm.com; s=20250909; h=from:subject:message-id; bh=PSFyCTD8XsFN5DnKm90Bf8IQfG9qwIw/GufXvDirK9w=; b=uzVIycWnN4sWS5HsT3ZSvRv8QAfUa3e2S0T5a5qDXqbvxFDw6QIK+ha8vj8T+ltH7W/btdb2S Hyoj8BinH5hDVuMgizPjQQEsAxC7nSnE+qneABA1uVs1PpV+9D8m1Ob X-Developer-Key: i=jie.gan@oss.qualcomm.com; a=ed25519; pk=3LxxUZRPCNkvPDlWOvXfJNqNO4SfGdy3eghMb8puHuk= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjIzMDA1OSBTYWx0ZWRfX/Qu8mLZGgn/b L0jZ4jCh6k+nMVhvNyUBRBknTCsIlnPMwWeNXBlQTYhR0ibX2WNWo0eF/U2Ohx3zSViAXWXG7+m QgKr2yANqc9xwi4WhrVEaDxCauax+Q8SQMSL1bi+/Wr9tFGwlL+I7i8SuzivzvbdVnj0namdkj5 91H5KPwlNIWbVzBZsH5yHmEfnWPExp0FpwO6ZSsOtk7UzXD7beoj5aGOCarXSQDfUEw4cAVuMmQ yrcw3j9n9aQsTLq1PvGRXGUmG0LPdEXRBLj/8lMinBkNhYshpq0WBBj2ZgavlxhXhRaq2BTy+L0 ajhEADmlzpRx0uSNgJ2yUqTxWhjyYhtY/X0BkNm8c0j6KdAOhxTZlXaq7XrGbay9pI0v2HZHZih 22PTVi1ZJQg+PEx05hPdPGI2tXZPfA5X5NHcbaVRSqPkhx3XRiSX2PDWNRjTG0GQSLdpk/tgbjj vld8oySDe2dVqbMFLwQ== X-Authority-Analysis: v=2.4 cv=W+A1lBWk c=1 sm=1 tr=0 ts=699bfa2e cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=TrPPj8Ph-2G9coJyck8A:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-GUID: H6jHABzH6jsajJSY0AHTDZvuxlj95v3H X-Proofpoint-ORIG-GUID: H6jHABzH6jsajJSY0AHTDZvuxlj95v3H X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-23_01,2026-02-20_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 phishscore=0 suspectscore=0 spamscore=0 bulkscore=0 adultscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602230059 The byte-cntr function provided by the CTCU device is used to transfer data from the ETR buffer to the userspace. An interrupt is triggered if the data size exceeds the threshold set in the BYTECNTRVAL register. The interrupt handler counts the number of triggered interruptions and the read function will read the data from the synced ETR buffer. Switching the sysfs_buf when current buffer is full or the timeout is triggered and resets rrp and rwp registers after switched the buffer. The synced buffer will become available for reading after the switch. Signed-off-by: Jie Gan --- .../ABI/testing/sysfs-bus-coresight-devices-ctcu | 8 + drivers/hwtracing/coresight/Makefile | 2 +- .../hwtracing/coresight/coresight-ctcu-byte-cntr.c | 367 +++++++++++++++++= ++++ drivers/hwtracing/coresight/coresight-ctcu-core.c | 103 +++++- drivers/hwtracing/coresight/coresight-ctcu.h | 77 ++++- drivers/hwtracing/coresight/coresight-tmc-etr.c | 18 + drivers/hwtracing/coresight/coresight-tmc.h | 1 + 7 files changed, 563 insertions(+), 13 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu b/D= ocumentation/ABI/testing/sysfs-bus-coresight-devices-ctcu new file mode 100644 index 000000000000..a58a05491f7a --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu @@ -0,0 +1,8 @@ +What: /sys/bus/coresight/devices//irq_threshold[0:1] +Date: February 2026 +KernelVersion: 7.1 +Contact: Tingwei Zhang ; Jinlong Ma= o ; Jie Gan +Description: + (RW) Configure the byte-cntr IRQ register for the specified ETR device + based on its port number. An interrupt is generated when the data size + exceeds the value set in the IRQ register. diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/cores= ight/Makefile index ab16d06783a5..821a1b06b20c 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -55,5 +55,5 @@ coresight-cti-y :=3D coresight-cti-core.o coresight-cti-p= latform.o \ obj-$(CONFIG_ULTRASOC_SMB) +=3D ultrasoc-smb.o obj-$(CONFIG_CORESIGHT_DUMMY) +=3D coresight-dummy.o obj-$(CONFIG_CORESIGHT_CTCU) +=3D coresight-ctcu.o -coresight-ctcu-y :=3D coresight-ctcu-core.o +coresight-ctcu-y :=3D coresight-ctcu-core.o coresight-ctcu-byte-cntr.o obj-$(CONFIG_CORESIGHT_KUNIT_TESTS) +=3D coresight-kunit-tests.o diff --git a/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c b/drive= rs/hwtracing/coresight/coresight-ctcu-byte-cntr.c new file mode 100644 index 000000000000..bf59e654465b --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c @@ -0,0 +1,367 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include + +#include "coresight-ctcu.h" +#include "coresight-priv.h" +#include "coresight-tmc.h" + +static irqreturn_t byte_cntr_handler(int irq, void *data) +{ + struct ctcu_byte_cntr *byte_cntr_data =3D (struct ctcu_byte_cntr *)data; + + atomic_inc(&byte_cntr_data->irq_cnt); + wake_up(&byte_cntr_data->wq); + + return IRQ_HANDLED; +} + +static void ctcu_reset_sysfs_buf(struct tmc_drvdata *drvdata) +{ + u32 sts; + + CS_UNLOCK(drvdata->base); + tmc_write_rrp(drvdata, drvdata->sysfs_buf->hwaddr); + tmc_write_rwp(drvdata, drvdata->sysfs_buf->hwaddr); + sts =3D readl_relaxed(drvdata->base + TMC_STS) & ~TMC_STS_FULL; + writel_relaxed(sts, drvdata->base + TMC_STS); + CS_LOCK(drvdata->base); +} + +static void ctcu_cfg_byte_cntr_reg(struct tmc_drvdata *drvdata, u32 val, u= 32 offset) +{ + struct ctcu_drvdata *ctcu_drvdata; + struct coresight_device *helper; + + helper =3D tmc_etr_get_ctcu_device(drvdata); + if (!helper) + return; + + ctcu_drvdata =3D dev_get_drvdata(helper->dev.parent); + /* A one value for IRQCTRL register represents 8 bytes */ + ctcu_program_register(ctcu_drvdata, val / 8, offset); +} + +static struct ctcu_byte_cntr *ctcu_get_byte_cntr_data(struct tmc_drvdata *= drvdata) +{ + struct ctcu_byte_cntr *byte_cntr_data; + struct ctcu_drvdata *ctcu_drvdata; + struct coresight_device *helper; + int port; + + helper =3D tmc_etr_get_ctcu_device(drvdata); + if (!helper) + return NULL; + + port =3D coresight_get_in_port(drvdata->csdev, helper); + if (port < 0) + return NULL; + + ctcu_drvdata =3D dev_get_drvdata(helper->dev.parent); + byte_cntr_data =3D &ctcu_drvdata->byte_cntr_data[port]; + return byte_cntr_data; +} + +static bool ctcu_byte_cntr_switch_buffer(struct tmc_drvdata *drvdata, + struct ctcu_byte_cntr *byte_cntr_data) +{ + struct etr_buf_node *nd, *next, *curr_node, *picked_node; + struct etr_buf *curr_buf =3D drvdata->sysfs_buf; + bool found_free_buf =3D false; + + if (WARN_ON(!drvdata || !byte_cntr_data)) + return found_free_buf; + + /* Stop the ETR before we start the switch */ + if (coresight_get_mode(drvdata->csdev) !=3D CS_MODE_DISABLED) + tmc_etr_enable_disable_hw(drvdata, false); + + list_for_each_entry_safe(nd, next, &drvdata->etr_buf_list, node) { + /* curr_buf is free for next round */ + if (nd->sysfs_buf =3D=3D curr_buf) { + nd->is_free =3D true; + curr_node =3D nd; + } + + if (!found_free_buf && nd->is_free && nd->sysfs_buf !=3D curr_buf) { + picked_node =3D nd; + found_free_buf =3D true; + } + } + + if (found_free_buf) { + curr_node->pos =3D 0; + drvdata->reading_node =3D curr_node; + drvdata->sysfs_buf =3D picked_node->sysfs_buf; + drvdata->etr_buf =3D picked_node->sysfs_buf; + picked_node->is_free =3D false; + /* Reset irq_cnt for next etr_buf */ + atomic_set(&byte_cntr_data->irq_cnt, 0); + /* Reset rrp and rwp when the system has switched the buffer*/ + ctcu_reset_sysfs_buf(drvdata); + /* Restart the ETR when we find a free buffer */ + if (coresight_get_mode(drvdata->csdev) !=3D CS_MODE_DISABLED) + tmc_etr_enable_disable_hw(drvdata, true); + } + + return found_free_buf; +} + +/* + * ctcu_byte_cntr_get_data() - reads data from the deactivated and filled = buffer. + * The byte-cntr reading work reads data from the deactivated and filled b= uffer. + * The read operation waits for a buffer to become available, either fille= d or + * upon timeout, and then reads trace data from the synced buffer. + */ +static ssize_t ctcu_byte_cntr_get_data(struct tmc_drvdata *drvdata, loff_t= pos, + size_t len, char **bufpp) +{ + struct etr_buf *sysfs_buf =3D drvdata->sysfs_buf; + struct device *dev =3D &drvdata->csdev->dev; + ssize_t actual, size =3D sysfs_buf->size; + struct ctcu_byte_cntr *byte_cntr_data; + size_t thresh_val; + atomic_t *irq_cnt; + int ret; + + byte_cntr_data =3D ctcu_get_byte_cntr_data(drvdata); + if (!byte_cntr_data) + return -EINVAL; + + thresh_val =3D byte_cntr_data->thresh_val; + irq_cnt =3D &byte_cntr_data->irq_cnt; + +wait_buffer: + if (!byte_cntr_data->reading_buf) { + ret =3D wait_event_interruptible_timeout(byte_cntr_data->wq, + ((atomic_read(irq_cnt) + 1) * thresh_val >=3D size) || + !byte_cntr_data->enable, + BYTE_CNTR_TIMEOUT); + if (ret < 0) + return ret; + /* + * The current etr_buf is almost full or timeout is triggered, + * so switch the buffer and mark the switched buffer as reading. + */ + if (byte_cntr_data->enable) { + if (!ctcu_byte_cntr_switch_buffer(drvdata, byte_cntr_data)) { + dev_err(dev, "Switch buffer failed for byte-cntr\n"); + return -EINVAL; + } + + byte_cntr_data->reading_buf =3D true; + } else { + /* + * TMC-ETR has been disabled, so directly reads data from + * the drvdata->sysfs_buf. + */ + actual =3D drvdata->sysfs_ops->get_trace_data(drvdata, pos, len, bufpp); + if (actual > 0) { + byte_cntr_data->total_size +=3D actual; + return actual; + } + + /* Exit byte-cntr reading */ + return 0; + } + } + + /* Check the status of current etr_buf*/ + if ((atomic_read(irq_cnt) + 1) * thresh_val >=3D size) + /* + * Unlikely to find a free buffer to switch, so just disable + * the ETR for a while. + */ + if (!ctcu_byte_cntr_switch_buffer(drvdata, byte_cntr_data)) + dev_warn(dev, "No available buffer to store data, disable ETR\n"); + + pos =3D drvdata->reading_node->pos; + actual =3D drvdata->sysfs_ops->get_trace_data(drvdata, pos, len, bufpp); + if (actual <=3D 0) { + /* Reset flags upon reading is finished or failed */ + byte_cntr_data->reading_buf =3D false; + drvdata->reading_node =3D NULL; + + /* + * Nothing in the buffer, waiting for the next buffer + * to be filled. + */ + if (actual =3D=3D 0) + goto wait_buffer; + } else + byte_cntr_data->total_size +=3D actual; + + return actual; +} + +static int ctcu_read_prepare_byte_cntr(struct tmc_drvdata *drvdata) +{ + struct ctcu_byte_cntr *byte_cntr_data; + unsigned long flags; + int ret =3D 0; + + /* config types are set a boot time and never change */ + if (WARN_ON_ONCE(drvdata->config_type !=3D TMC_CONFIG_TYPE_ETR)) + return -EINVAL; + + /* + * Byte counter reading should start only after the TMC-ETR has been + * enabled, which implies that the sysfs_buf has already been setup + * in drvdata. + */ + if (!drvdata->sysfs_buf) + return -EINVAL; + + byte_cntr_data =3D ctcu_get_byte_cntr_data(drvdata); + if (!byte_cntr_data) + return -EINVAL; + + /* + * The threshold value must not exceed the buffer size. + * A margin should be maintained between the two values to account + * for the time gap between the interrupt and buffer switching. + */ + if (byte_cntr_data->thresh_val + SZ_16K >=3D drvdata->size) { + dev_err(&drvdata->csdev->dev, "The threshold value is too large\n"); + return -EINVAL; + } + + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + if (byte_cntr_data->reading) { + ret =3D -EBUSY; + goto out_unlock; + } + + byte_cntr_data->reading =3D true; + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + /* Setup an available etr_buf_list for byte-cntr */ + ret =3D tmc_create_etr_buf_list(drvdata, 2); + if (ret) + goto out; + + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + atomic_set(&byte_cntr_data->irq_cnt, 0); + /* Configure the byte-cntr register to enable IRQ */ + ctcu_cfg_byte_cntr_reg(drvdata, byte_cntr_data->thresh_val, + byte_cntr_data->irq_ctrl_offset); + enable_irq_wake(byte_cntr_data->irq); + byte_cntr_data->total_size =3D 0; + +out_unlock: + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + +out: + return ret; +} + +static int ctcu_read_unprepare_byte_cntr(struct tmc_drvdata *drvdata) +{ + struct device *dev =3D &drvdata->csdev->dev; + struct ctcu_byte_cntr *byte_cntr_data; + unsigned long flags; + + byte_cntr_data =3D ctcu_get_byte_cntr_data(drvdata); + if (!byte_cntr_data) + return -EINVAL; + + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + /* Configure the byte-cntr register to disable IRQ */ + ctcu_cfg_byte_cntr_reg(drvdata, 0, byte_cntr_data->irq_ctrl_offset); + disable_irq_wake(byte_cntr_data->irq); + byte_cntr_data->reading =3D false; + byte_cntr_data->reading_buf =3D false; + drvdata->reading_node =3D NULL; + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + dev_dbg(dev, "send data total size:%llu bytes\n", byte_cntr_data->total_s= ize); + tmc_clean_etr_buf_list(drvdata); + + return 0; +} + +static const struct tmc_sysfs_ops byte_cntr_sysfs_ops =3D { + .read_prepare =3D ctcu_read_prepare_byte_cntr, + .read_unprepare =3D ctcu_read_unprepare_byte_cntr, + .get_trace_data =3D ctcu_byte_cntr_get_data, +}; + +/* Start the byte-cntr function when the path is enabled. */ +void ctcu_byte_cntr_start(struct coresight_device *csdev, struct coresight= _path *path) +{ + struct ctcu_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); + struct coresight_device *sink =3D coresight_get_sink(path); + struct ctcu_byte_cntr *byte_cntr_data; + int port_num; + + if (!sink) + return; + + port_num =3D coresight_get_in_port(sink, csdev); + if (port_num < 0) + return; + + byte_cntr_data =3D &drvdata->byte_cntr_data[port_num]; + /* Don't start byte-cntr function when threshold is not set. */ + if (!byte_cntr_data->thresh_val || byte_cntr_data->enable) + return; + + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); + byte_cntr_data->enable =3D true; + byte_cntr_data->reading_buf =3D false; +} + +/* Stop the byte-cntr function when the path is disabled. */ +void ctcu_byte_cntr_stop(struct coresight_device *csdev, struct coresight_= path *path) +{ + struct ctcu_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); + struct coresight_device *sink =3D coresight_get_sink(path); + struct ctcu_byte_cntr *byte_cntr_data; + int port_num; + + if (!sink || coresight_get_mode(sink) =3D=3D CS_MODE_SYSFS) + return; + + port_num =3D coresight_get_in_port(sink, csdev); + if (port_num < 0) + return; + + byte_cntr_data =3D &drvdata->byte_cntr_data[port_num]; + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); + byte_cntr_data->enable =3D false; +} + +void ctcu_byte_cntr_init(struct device *dev, struct ctcu_drvdata *drvdata,= int etr_num) +{ + struct ctcu_byte_cntr *byte_cntr_data; + struct device_node *nd =3D dev->of_node; + int irq_num, ret, i; + + drvdata->byte_cntr_sysfs_ops =3D &byte_cntr_sysfs_ops; + for (i =3D 0; i < etr_num; i++) { + byte_cntr_data =3D &drvdata->byte_cntr_data[i]; + irq_num =3D of_irq_get(nd, i); + if (irq_num < 0) { + dev_err(dev, "Failed to get IRQ from DT for port%d\n", i); + continue; + } + + ret =3D devm_request_irq(dev, irq_num, byte_cntr_handler, + IRQF_TRIGGER_RISING | IRQF_SHARED, + dev_name(dev), byte_cntr_data); + if (ret) { + dev_err(dev, "Failed to register IRQ for port%d\n", i); + continue; + } + + byte_cntr_data->irq =3D irq_num; + init_waitqueue_head(&byte_cntr_data->wq); + raw_spin_lock_init(&drvdata->spin_lock); + } +} diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hw= tracing/coresight/coresight-ctcu-core.c index 78be783b3cb2..0e5cadaac350 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu-core.c +++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c @@ -15,6 +15,7 @@ #include #include #include +#include =20 #include "coresight-ctcu.h" #include "coresight-priv.h" @@ -45,17 +46,21 @@ DEFINE_CORESIGHT_DEVLIST(ctcu_devs, "ctcu"); =20 #define CTCU_ATID_REG_BIT(traceid) (traceid % 32) #define CTCU_ATID_REG_SIZE 0x10 +#define CTCU_ETR0_IRQCTRL 0x6c +#define CTCU_ETR1_IRQCTRL 0x70 #define CTCU_ETR0_ATID0 0xf8 #define CTCU_ETR1_ATID0 0x108 =20 static const struct ctcu_etr_config sa8775p_etr_cfgs[] =3D { { - .atid_offset =3D CTCU_ETR0_ATID0, - .port_num =3D 0, + .atid_offset =3D CTCU_ETR0_ATID0, + .irq_ctrl_offset =3D CTCU_ETR0_IRQCTRL, + .port_num =3D 0, }, { - .atid_offset =3D CTCU_ETR1_ATID0, - .port_num =3D 1, + .atid_offset =3D CTCU_ETR1_ATID0, + .irq_ctrl_offset =3D CTCU_ETR1_IRQCTRL, + .port_num =3D 1, }, }; =20 @@ -64,6 +69,88 @@ static const struct ctcu_config sa8775p_cfgs =3D { .num_etr_config =3D ARRAY_SIZE(sa8775p_etr_cfgs), }; =20 +void ctcu_program_register(struct ctcu_drvdata *drvdata, u32 val, u32 offs= et) +{ + CS_UNLOCK(drvdata->base); + ctcu_writel(drvdata, val, offset); + CS_LOCK(drvdata->base); +} + +static ssize_t irq_threshold_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct ctcu_byte_cntr_irq_attribute *irq_attr =3D + container_of(attr, struct ctcu_byte_cntr_irq_attribute, attr); + struct ctcu_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + u8 port =3D irq_attr->port; + + if (!drvdata->byte_cntr_data[port].irq_ctrl_offset) + return -EINVAL; + + return sysfs_emit(buf, "%u\n", + (unsigned int)drvdata->byte_cntr_data[port].thresh_val); +} + +static ssize_t irq_threshold_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct ctcu_byte_cntr_irq_attribute *irq_attr =3D + container_of(attr, struct ctcu_byte_cntr_irq_attribute, attr); + struct ctcu_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + u8 port =3D irq_attr->port; + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + /* Threshold 0 disables the interruption. */ + guard(raw_spinlock_irqsave)(&drvdata->spin_lock); + /* A small threshold will result in a large number of interruptions */ + if (val && val < SZ_4K) + return -EINVAL; + + if (drvdata->byte_cntr_data[port].irq_ctrl_offset) + drvdata->byte_cntr_data[port].thresh_val =3D val; + + return size; +} + +static umode_t irq_threshold_is_visible(struct kobject *kobj, + struct attribute *attr, int n) +{ + struct device_attribute *dev_attr =3D + container_of(attr, struct device_attribute, attr); + struct ctcu_byte_cntr_irq_attribute *irq_attr =3D + container_of(dev_attr, struct ctcu_byte_cntr_irq_attribute, attr); + struct device *dev =3D kobj_to_dev(kobj); + struct ctcu_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + u8 port =3D irq_attr->port; + + if (drvdata && drvdata->byte_cntr_data[port].irq_ctrl_offset) + return attr->mode; + + return 0; +} + +static struct attribute *ctcu_attrs[] =3D { + ctcu_byte_cntr_irq_rw(0), + ctcu_byte_cntr_irq_rw(1), + NULL, +}; + +static struct attribute_group ctcu_attr_grp =3D { + .attrs =3D ctcu_attrs, + .is_visible =3D irq_threshold_is_visible, +}; + +static const struct attribute_group *ctcu_attr_grps[] =3D { + &ctcu_attr_grp, + NULL, +}; + static void ctcu_program_atid_register(struct ctcu_drvdata *drvdata, u32 r= eg_offset, u8 bit, bool enable) { @@ -142,11 +229,15 @@ static int ctcu_set_etr_traceid(struct coresight_devi= ce *csdev, struct coresight static int ctcu_enable(struct coresight_device *csdev, enum cs_mode mode, struct coresight_path *path) { + ctcu_byte_cntr_start(csdev, path); + return ctcu_set_etr_traceid(csdev, path, true); } =20 static int ctcu_disable(struct coresight_device *csdev, struct coresight_p= ath *path) { + ctcu_byte_cntr_stop(csdev, path); + return ctcu_set_etr_traceid(csdev, path, false); } =20 @@ -197,7 +288,10 @@ static int ctcu_probe(struct platform_device *pdev) for (i =3D 0; i < cfgs->num_etr_config; i++) { etr_cfg =3D &cfgs->etr_cfgs[i]; drvdata->atid_offset[i] =3D etr_cfg->atid_offset; + drvdata->byte_cntr_data[i].irq_ctrl_offset =3D + etr_cfg->irq_ctrl_offset; } + ctcu_byte_cntr_init(dev, drvdata, cfgs->num_etr_config); } } =20 @@ -209,6 +303,7 @@ static int ctcu_probe(struct platform_device *pdev) desc.subtype.helper_subtype =3D CORESIGHT_DEV_SUBTYPE_HELPER_CTCU; desc.pdata =3D pdata; desc.dev =3D dev; + desc.groups =3D ctcu_attr_grps; desc.ops =3D &ctcu_ops; desc.access =3D CSDEV_ACCESS_IOMEM(base); =20 diff --git a/drivers/hwtracing/coresight/coresight-ctcu.h b/drivers/hwtraci= ng/coresight/coresight-ctcu.h index e9594c38dd91..bc833482c8bc 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu.h +++ b/drivers/hwtracing/coresight/coresight-ctcu.h @@ -5,19 +5,26 @@ =20 #ifndef _CORESIGHT_CTCU_H #define _CORESIGHT_CTCU_H + +#include #include "coresight-trace-id.h" =20 /* Maximum number of supported ETR devices for a single CTCU. */ #define ETR_MAX_NUM 2 =20 +#define BYTE_CNTR_TIMEOUT (5 * HZ) + /** * struct ctcu_etr_config * @atid_offset: offset to the ATID0 Register. - * @port_num: in-port number of CTCU device that connected to ETR. + * @port_num: in-port number of the CTCU device that connected to ETR. + * @irq_ctrl_offset: offset to the BYTECNTRVAL register. + * @irq_name: IRQ name in dt node. */ struct ctcu_etr_config { const u32 atid_offset; const u32 port_num; + const u32 irq_ctrl_offset; }; =20 struct ctcu_config { @@ -25,15 +32,69 @@ struct ctcu_config { int num_etr_config; }; =20 -struct ctcu_drvdata { - void __iomem *base; - struct clk *apb_clk; - struct device *dev; - struct coresight_device *csdev; +/** + * struct ctcu_byte_cntr + * @enable: indicates that byte_cntr function is enabled or not. + * @reading: indicates that byte-cntr reading is started. + * @reading_buf: indicates that byte-cntr is reading data from the buffer. + * @thresh_val: threshold to trigger a interruption. + * @total_size: total size of transferred data. + * @irq: allocated number of the IRQ. + * @irq_cnt: IRQ count number for triggered interruptions. + * @wq: waitqueue for reading data from ETR buffer. + * @spin_lock: spinlock of byte_cntr_data. + * @irq_ctrl_offset: offset to the BYTECNTVAL Register. + */ +struct ctcu_byte_cntr { + bool enable; + bool reading; + bool reading_buf; + u32 thresh_val; + u64 total_size; + int irq; + atomic_t irq_cnt; + wait_queue_head_t wq; raw_spinlock_t spin_lock; - u32 atid_offset[ETR_MAX_NUM]; + u32 irq_ctrl_offset; +}; + +struct ctcu_drvdata { + void __iomem *base; + struct clk *apb_clk; + struct device *dev; + struct coresight_device *csdev; + struct ctcu_byte_cntr byte_cntr_data[ETR_MAX_NUM]; + raw_spinlock_t spin_lock; + u32 atid_offset[ETR_MAX_NUM]; /* refcnt for each traceid of each sink */ - u8 traceid_refcnt[ETR_MAX_NUM][CORESIGHT_TRACE_ID_RES_TOP]; + u8 traceid_refcnt[ETR_MAX_NUM][CORESIGHT_TRACE_ID_RES_TOP]; + const struct tmc_sysfs_ops *byte_cntr_sysfs_ops; }; =20 +/** + * struct ctcu_irq_thresh_attribute + * @attr: The device attribute. + * @idx: port number. + */ +struct ctcu_byte_cntr_irq_attribute { + struct device_attribute attr; + u8 port; +}; + +#define ctcu_byte_cntr_irq_rw(port) \ + (&((struct ctcu_byte_cntr_irq_attribute[]) { \ + { \ + __ATTR(irq_threshold##port, 0644, irq_threshold_show, \ + irq_threshold_store), \ + port, \ + } \ + })[0].attr.attr) + +void ctcu_program_register(struct ctcu_drvdata *drvdata, u32 val, u32 offs= et); + +/* Byte-cntr functions */ +void ctcu_byte_cntr_start(struct coresight_device *csdev, struct coresight= _path *path); +void ctcu_byte_cntr_stop(struct coresight_device *csdev, struct coresight_= path *path); +void ctcu_byte_cntr_init(struct device *dev, struct ctcu_drvdata *drvdata,= int port_num); + #endif diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index 32353980964a..83514966df5a 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1187,6 +1187,10 @@ ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *= drvdata, ssize_t actual =3D len; struct etr_buf *etr_buf =3D drvdata->sysfs_buf; =20 + /* Reading the buffer from the buf_node if it exists*/ + if (drvdata->reading_node) + etr_buf =3D drvdata->reading_node->sysfs_buf; + if (pos + actual > etr_buf->len) actual =3D etr_buf->len - pos; if (actual <=3D 0) @@ -1250,6 +1254,20 @@ static void __tmc_etr_disable_hw(struct tmc_drvdata = *drvdata) =20 } =20 +/** + * tmc_etr_enable_disable_hw - enable/disable the ETR hw. + * @drvdata: drvdata of the TMC device. + * @enable: indicates enable/disable. + */ +void tmc_etr_enable_disable_hw(struct tmc_drvdata *drvdata, bool enable) +{ + if (enable) + __tmc_etr_enable_hw(drvdata); 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ad74f619f8sm62249225ad.36.2026.02.22.22.56.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Feb 2026 22:56:48 -0800 (PST) From: Jie Gan Date: Mon, 23 Feb 2026 14:55:47 +0800 Subject: [PATCH v13 7/8] coresight: tmc: integrate byte-cntr's sysfs_ops with tmc sysfs file_ops Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260223-enable-byte-cntr-for-ctcu-v13-7-9cb44178b250@oss.qualcomm.com> References: <20260223-enable-byte-cntr-for-ctcu-v13-0-9cb44178b250@oss.qualcomm.com> In-Reply-To: <20260223-enable-byte-cntr-for-ctcu-v13-0-9cb44178b250@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tingwei Zhang , Mao Jinlong , Bjorn Andersson , Konrad Dybcio Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Jie Gan X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771829766; l=3465; i=jie.gan@oss.qualcomm.com; s=20250909; h=from:subject:message-id; bh=+caVanCR1MkRvTlDCUseywuTVg2NMA0xm0dQkI5ZlEc=; b=8vsvryV3p2tlaIsnZJ203CuZuyviTZHwaN5/VtguGF/hW91zHbcV3jaD9RDG2KEfmTEvONd3V 5XpDOIs4WHvDzDUtP80ER6gRoG/p72gCkbi45WTlPUhyAkx3etFoqta X-Developer-Key: i=jie.gan@oss.qualcomm.com; a=ed25519; pk=3LxxUZRPCNkvPDlWOvXfJNqNO4SfGdy3eghMb8puHuk= X-Proofpoint-ORIG-GUID: ktduf1fXzdd1ByQ0hZh7vE9X3ewVm_D4 X-Authority-Analysis: v=2.4 cv=UZlciaSN c=1 sm=1 tr=0 ts=699bfa32 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=i2GxayCjj04of9N-vEoA:9 a=+jEqtf1s3R9VXZ0wqowq2kgwd+I=:19 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: ktduf1fXzdd1ByQ0hZh7vE9X3ewVm_D4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjIzMDA1OSBTYWx0ZWRfX0sQ89sSisjE8 p/QXDhpCwar8xr7e4qnJfiYNhNYqYb0+bpxk5Qulg0ShcB/AVWk594EyKPS7LGTslCbXRVqjcRR tPkTcdhMn+p2xXPzrc4H6r/8eTh40/C/IiLS7yND/6/qmhvz8unkWchSCxDD+h/aR3suaV/Ev9W fa/aa8Wz/mJLQGW6J2sV9DpNlONXRwwIlDK/WPc1mUyIZJ5W2V+LukA7InLUXHsMFOLs5pdVJxp D/ft97LWNdwLO6vKTPKZxWJOrDPdK8p+/c/LWbtXvxedg/15fUiZJRnZmAY0qHTxU27TUJb4nQ9 JbesEiUMzElLTpw1M3oLFbY/c/JeUb4HMRVrgKxWuyskUyV3uFuAwBRcxuJizXynmmj0b4T75uZ Jl/Ex2TE2hUx1nfARyb/B7GzqOkatOmDhxzEqwlzUafXjQVfxuKeDhl6IvL78Sy5OjrbV59B+zV s0Gw8wAaqIUAC21BtRg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-23_01,2026-02-20_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 phishscore=0 spamscore=0 malwarescore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602230059 Add code logic to invoke byte-cntr's tmc_sysfs_ops if the byte-cntr is enabled. Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/coresight-tmc-core.c | 53 ++++++++++++++++++++= +++- 1 file changed, 52 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index 32ca2ec994de..6486bdafdddc 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -31,6 +31,7 @@ =20 #include "coresight-priv.h" #include "coresight-tmc.h" +#include "coresight-ctcu.h" =20 DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb"); DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf"); @@ -228,15 +229,47 @@ static int tmc_prepare_crashdata(struct tmc_drvdata *= drvdata) return 0; } =20 +/* Return the byte-cntr's tmc_sysfs_ops if in using */ +static const struct tmc_sysfs_ops *tmc_get_byte_cntr_sysfs_ops(struct tmc_= drvdata *drvdata) +{ + struct ctcu_byte_cntr *byte_cntr_data; + struct ctcu_drvdata *ctcu_drvdata; + struct coresight_device *ctcu; + int port; + + ctcu =3D tmc_etr_get_ctcu_device(drvdata); + if (!ctcu) + return NULL; + + port =3D coresight_get_in_port(drvdata->csdev, ctcu); + if (port < 0) + return NULL; + + ctcu_drvdata =3D dev_get_drvdata(ctcu->dev.parent); + byte_cntr_data =3D &ctcu_drvdata->byte_cntr_data[port]; + if (byte_cntr_data && byte_cntr_data->thresh_val) + return ctcu_drvdata->byte_cntr_sysfs_ops; + + return NULL; +} + static int tmc_read_prepare(struct tmc_drvdata *drvdata) { + const struct tmc_sysfs_ops *byte_cntr_sysfs_ops; int ret =3D 0; =20 + byte_cntr_sysfs_ops =3D tmc_get_byte_cntr_sysfs_ops(drvdata); + if (byte_cntr_sysfs_ops) { + ret =3D byte_cntr_sysfs_ops->read_prepare(drvdata); + goto out; + } + if (drvdata->sysfs_ops) ret =3D drvdata->sysfs_ops->read_prepare(drvdata); else ret =3D -EINVAL; =20 +out: if (!ret) dev_dbg(&drvdata->csdev->dev, "TMC read start\n"); =20 @@ -245,13 +278,21 @@ static int tmc_read_prepare(struct tmc_drvdata *drvda= ta) =20 static int tmc_read_unprepare(struct tmc_drvdata *drvdata) { + const struct tmc_sysfs_ops *byte_cntr_sysfs_ops; int ret =3D 0; =20 + byte_cntr_sysfs_ops =3D tmc_get_byte_cntr_sysfs_ops(drvdata); + if (byte_cntr_sysfs_ops) { + ret =3D byte_cntr_sysfs_ops->read_unprepare(drvdata); + goto out; + } + if (drvdata->sysfs_ops) ret =3D drvdata->sysfs_ops->read_unprepare(drvdata); else ret =3D -EINVAL; =20 +out: if (!ret) dev_dbg(&drvdata->csdev->dev, "TMC read end\n"); =20 @@ -277,6 +318,12 @@ static int tmc_open(struct inode *inode, struct file *= file) static ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata, loff_t pos= , size_t len, char **bufpp) { + const struct tmc_sysfs_ops *byte_cntr_sysfs_ops; + + byte_cntr_sysfs_ops =3D tmc_get_byte_cntr_sysfs_ops(drvdata); + if (byte_cntr_sysfs_ops) + return byte_cntr_sysfs_ops->get_trace_data(drvdata, pos, len, bufpp); + return drvdata->sysfs_ops->get_trace_data(drvdata, pos, len, bufpp); } =20 @@ -297,7 +344,11 @@ static ssize_t tmc_read(struct file *file, char __user= *data, size_t len, return -EFAULT; } =20 - *ppos +=3D actual; + if (drvdata->reading_node) + drvdata->reading_node->pos +=3D actual; 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Reviewed-by: Konrad Dybcio Signed-off-by: Jie Gan --- arch/arm64/boot/dts/qcom/lemans.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qco= m/lemans.dtsi index 808827b83553..e8a20789cd58 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -2800,6 +2800,9 @@ ctcu@4001000 { clocks =3D <&aoss_qmp>; clock-names =3D "apb"; =20 + interrupts =3D , + ; + in-ports { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.34.1