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Signed-off-by: Odelu Kukatla Reviewed-by: Krzysztof Kozlowski Signed-off-by: Abel Vesa --- .../bindings/interconnect/qcom,eliza-rpmh.yaml | 142 +++++++++++++++++= ++++ include/dt-bindings/interconnect/qcom,eliza-rpmh.h | 136 +++++++++++++++++= +++ 2 files changed, 278 insertions(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,eliza-rpmh= .yaml b/Documentation/devicetree/bindings/interconnect/qcom,eliza-rpmh.yaml new file mode 100644 index 000000000000..998d889e7d7d --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,eliza-rpmh.yaml @@ -0,0 +1,142 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,eliza-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on Eliza SoC + +maintainers: + - Odelu Kukatla + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provide= r is + able to communicate with the BCM through the Resource State Coordinator = (RSC) + associated with each execution environment. Provider nodes must point to= at + least one RPMh device child node pertaining to their RSC and each provid= er + can map to multiple RPMh resources. + + See also: include/dt-bindings/interconnect/qcom,eliza-rpmh.h + +properties: + compatible: + enum: + - qcom,eliza-aggre1-noc + - qcom,eliza-aggre2-noc + - qcom,eliza-clk-virt + - qcom,eliza-cnoc-cfg + - qcom,eliza-cnoc-main + - qcom,eliza-gem-noc + - qcom,eliza-lpass-ag-noc + - qcom,eliza-lpass-lpiaon-noc + - qcom,eliza-lpass-lpicx-noc + - qcom,eliza-mc-virt + - qcom,eliza-mmss-noc + - qcom,eliza-nsp-noc + - qcom,eliza-pcie-anoc + - qcom,eliza-system-noc + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + +required: + - compatible + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,eliza-clk-virt + - qcom,eliza-mc-virt + then: + properties: + reg: false + else: + required: + - reg + + - if: + properties: + compatible: + contains: + enum: + - qcom,eliza-aggre1-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre USB3 PRIM AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,eliza-aggre2-noc + then: + properties: + clocks: + items: + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,eliza-pcie-anoc + then: + properties: + clocks: + items: + - description: aggre-NOC PCIe AXI clock + - description: cfg-NOC PCIe a-NOC AHB clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,eliza-aggre1-noc + - qcom,eliza-aggre2-noc + - qcom,eliza-pcie-anoc + then: + required: + - clocks + else: + properties: + clocks: false + +unevaluatedProperties: false + +examples: + - | + gem_noc: interconnect@24100000 { + compatible =3D "qcom,eliza-gem-noc"; + reg =3D <0x24100000 0x163080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mc_virt: interconnect-2 { + compatible =3D "qcom,eliza-mc-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible =3D "qcom,eliza-aggre1-noc"; + reg =3D <0x16e0000 0x16400>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + clocks =3D <&gcc_aggre_usb3_prim_axi_clk>; + }; diff --git a/include/dt-bindings/interconnect/qcom,eliza-rpmh.h b/include/d= t-bindings/interconnect/qcom,eliza-rpmh.h new file mode 100644 index 000000000000..95db2fe647de --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,eliza-rpmh.h @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_ELIZA_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_ELIZA_H + +#define MASTER_QSPI_0 0 +#define MASTER_QUP_1 1 +#define MASTER_UFS_MEM 2 +#define MASTER_USB3_0 3 +#define SLAVE_A1NOC_SNOC 4 + +#define MASTER_QUP_2 0 +#define MASTER_CRYPTO 1 +#define MASTER_IPA 2 +#define MASTER_SOCCP_AGGR_NOC 3 +#define MASTER_QDSS_ETR 4 +#define MASTER_QDSS_ETR_1 5 +#define MASTER_SDCC_1 6 +#define MASTER_SDCC_2 7 +#define SLAVE_A2NOC_SNOC 8 + +#define MASTER_QUP_CORE_1 0 +#define MASTER_QUP_CORE_2 1 +#define SLAVE_QUP_CORE_1 2 +#define SLAVE_QUP_CORE_2 3 + +#define MASTER_CNOC_CFG 0 +#define SLAVE_AHB2PHY_SOUTH 1 +#define SLAVE_AHB2PHY_NORTH 2 +#define SLAVE_CAMERA_CFG 3 +#define SLAVE_CLK_CTL 4 +#define SLAVE_CRYPTO_0_CFG 5 +#define SLAVE_DISPLAY_CFG 6 +#define SLAVE_GFX3D_CFG 7 +#define SLAVE_I3C_IBI0_CFG 8 +#define SLAVE_I3C_IBI1_CFG 9 +#define SLAVE_IMEM_CFG 10 +#define SLAVE_CNOC_MSS 11 +#define SLAVE_PCIE_0_CFG 12 +#define SLAVE_PRNG 13 +#define SLAVE_QDSS_CFG 14 +#define SLAVE_QSPI_0 15 +#define SLAVE_QUP_1 16 +#define SLAVE_QUP_2 17 +#define SLAVE_SDCC_2 18 +#define SLAVE_TCSR 19 +#define SLAVE_TLMM 20 +#define SLAVE_UFS_MEM_CFG 21 +#define SLAVE_USB3_0 22 +#define SLAVE_VENUS_CFG 23 +#define SLAVE_VSENSE_CTRL_CFG 24 +#define SLAVE_CNOC_MNOC_HF_CFG 25 +#define SLAVE_CNOC_MNOC_SF_CFG 26 +#define SLAVE_PCIE_ANOC_CFG 27 +#define SLAVE_QDSS_STM 28 +#define SLAVE_TCU 29 + +#define MASTER_GEM_NOC_CNOC 0 +#define MASTER_GEM_NOC_PCIE_SNOC 1 +#define SLAVE_AOSS 2 +#define SLAVE_IPA_CFG 3 +#define SLAVE_IPC_ROUTER_CFG 4 +#define SLAVE_SOCCP 5 +#define SLAVE_TME_CFG 6 +#define SLAVE_APPSS 7 +#define SLAVE_CNOC_CFG 8 +#define SLAVE_DDRSS_CFG 9 +#define SLAVE_BOOT_IMEM 10 +#define SLAVE_IMEM 11 +#define SLAVE_BOOT_IMEM_2 12 +#define SLAVE_SERVICE_CNOC 13 +#define SLAVE_PCIE_0 14 +#define SLAVE_PCIE_1 15 + +#define MASTER_GPU_TCU 0 +#define MASTER_SYS_TCU 1 +#define MASTER_APPSS_PROC 2 +#define MASTER_GFX3D 3 +#define MASTER_LPASS_GEM_NOC 4 +#define MASTER_MSS_PROC 5 +#define MASTER_MNOC_HF_MEM_NOC 6 +#define MASTER_MNOC_SF_MEM_NOC 7 +#define MASTER_COMPUTE_NOC 8 +#define MASTER_ANOC_PCIE_GEM_NOC 9 +#define MASTER_SNOC_SF_MEM_NOC 10 +#define MASTER_WLAN_Q6 11 +#define MASTER_GIC 12 +#define SLAVE_GEM_NOC_CNOC 13 +#define SLAVE_LLCC 14 +#define SLAVE_MEM_NOC_PCIE_SNOC 15 + +#define MASTER_LPIAON_NOC 0 +#define SLAVE_LPASS_GEM_NOC 1 + +#define MASTER_LPASS_LPINOC 0 +#define SLAVE_LPIAON_NOC_LPASS_AG_NOC 1 + +#define MASTER_LPASS_PROC 0 +#define SLAVE_LPICX_NOC_LPIAON_NOC 1 + +#define MASTER_LLCC 0 +#define SLAVE_EBI1 1 + +#define MASTER_CAMNOC_NRT_ICP_SF 0 +#define MASTER_CAMNOC_RT_CDM_SF 1 +#define MASTER_CAMNOC_SF 2 +#define MASTER_VIDEO_MVP 3 +#define MASTER_VIDEO_V_PROC 4 +#define MASTER_CNOC_MNOC_SF_CFG 5 +#define MASTER_CAMNOC_HF 6 +#define MASTER_MDP 7 +#define MASTER_CNOC_MNOC_HF_CFG 8 +#define SLAVE_MNOC_SF_MEM_NOC 9 +#define SLAVE_SERVICE_MNOC_SF 10 +#define SLAVE_MNOC_HF_MEM_NOC 11 +#define SLAVE_SERVICE_MNOC_HF 12 + +#define MASTER_CDSP_PROC 0 +#define SLAVE_CDSP_MEM_NOC 1 + +#define MASTER_PCIE_ANOC_CFG 0 +#define MASTER_PCIE_0 1 +#define MASTER_PCIE_1 2 +#define SLAVE_ANOC_PCIE_GEM_NOC 3 +#define SLAVE_SERVICE_PCIE_ANOC 4 + +#define MASTER_A1NOC_SNOC 0 +#define MASTER_A2NOC_SNOC 1 +#define MASTER_CNOC_SNOC 2 +#define MASTER_NSINOC_SNOC 3 +#define SLAVE_SNOC_GEM_NOC_SF 4 + +#endif --=20 2.48.1 From nobody Fri Apr 17 06:16:00 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 488353659F4 for ; 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The topology consists of several NoCs that are controlled by a remote processor that collects the aggregated bandwidth for each master-slave pairs. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Odelu Kukatla Signed-off-by: Abel Vesa --- drivers/interconnect/qcom/Kconfig | 9 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/eliza.c | 1585 ++++++++++++++++++++++++++++++++= ++++ 3 files changed, 1596 insertions(+) diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/= Kconfig index bb1cb8a640c1..d18afe4392f1 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -8,6 +8,15 @@ config INTERCONNECT_QCOM config INTERCONNECT_QCOM_BCM_VOTER tristate =20 +config INTERCONNECT_QCOM_ELIZA + tristate "Qualcomm Eliza interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER + help + This is a driver for the Qualcomm Network-on-Chip on Eliza-based + platforms. + config INTERCONNECT_QCOM_GLYMUR tristate "Qualcomm GLYMUR interconnect driver" depends on INTERCONNECT_QCOM_RPMH_POSSIBLE diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom= /Makefile index 6eedff043b41..cdf2c6c9fbf3 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM) +=3D interconnect_qcom.o =20 interconnect_qcom-y :=3D icc-common.o icc-bcm-voter-objs :=3D bcm-voter.o +qnoc-eliza-objs :=3D eliza.o qnoc-glymur-objs :=3D glymur.o qnoc-kaanapali-objs :=3D kaanapali.o qnoc-milos-objs :=3D milos.o @@ -48,6 +49,7 @@ qnoc-x1e80100-objs :=3D x1e80100.o icc-smd-rpm-objs :=3D smd-rpm.o icc-rpm.o icc-rpm-clocks.o =20 obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) +=3D icc-bcm-voter.o +obj-$(CONFIG_INTERCONNECT_QCOM_ELIZA) +=3D qnoc-eliza.o obj-$(CONFIG_INTERCONNECT_QCOM_GLYMUR) +=3D qnoc-glymur.o obj-$(CONFIG_INTERCONNECT_QCOM_KAANAPALI) +=3D qnoc-kaanapali.o obj-$(CONFIG_INTERCONNECT_QCOM_MILOS) +=3D qnoc-milos.o diff --git a/drivers/interconnect/qcom/eliza.c b/drivers/interconnect/qcom/= eliza.c new file mode 100644 index 000000000000..a4f7903f0524 --- /dev/null +++ b/drivers/interconnect/qcom/eliza.c @@ -0,0 +1,1585 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include + +#include "bcm-voter.h" +#include "icc-rpmh.h" + +static struct qcom_icc_node qup1_core_slave =3D { + .name =3D "qup1_core_slave", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qup2_core_slave =3D { + .name =3D "qup2_core_slave", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ahb2phy0 =3D { + .name =3D "qhs_ahb2phy0", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ahb2phy1 =3D { + .name =3D "qhs_ahb2phy1", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_camera_cfg =3D { + .name =3D "qhs_camera_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_clk_ctl =3D { + .name =3D "qhs_clk_ctl", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg =3D { + .name =3D "qhs_crypto0_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_display_cfg =3D { + .name =3D "qhs_display_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg =3D { + .name =3D "qhs_gpuss_cfg", + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qhs_i3c_ibi0_cfg =3D { + .name =3D "qhs_i3c_ibi0_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_i3c_ibi1_cfg =3D { + .name =3D "qhs_i3c_ibi1_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_imem_cfg =3D { + .name =3D "qhs_imem_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_mss_cfg =3D { + .name =3D "qhs_mss_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie_0_cfg =3D { + .name =3D "qhs_pcie_0_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_prng =3D { + .name =3D "qhs_prng", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg =3D { + .name =3D "qhs_qdss_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qspi =3D { + .name =3D "qhs_qspi", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup1 =3D { + .name =3D "qhs_qup1", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup2 =3D { + .name =3D "qhs_qup2", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_sdc2 =3D { + .name =3D "qhs_sdc2", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tcsr =3D { + .name =3D "qhs_tcsr", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tlmm =3D { + .name =3D "qhs_tlmm", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg =3D { + .name =3D "qhs_ufs_mem_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3_0 =3D { + .name =3D "qhs_usb3_0", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_venus_cfg =3D { + .name =3D "qhs_venus_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { + .name =3D "qhs_vsense_ctrl_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_qdss_stm =3D { + .name =3D "xs_qdss_stm", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg =3D { + .name =3D "xs_sys_tcu_cfg", + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qhs_aoss =3D { + .name =3D "qhs_aoss", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ipa =3D { + .name =3D "qhs_ipa", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ipc_router =3D { + .name =3D "qhs_ipc_router", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_soccp =3D { + .name =3D "qhs_soccp", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tme_cfg =3D { + .name =3D "qhs_tme_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qss_apss =3D { + .name =3D "qss_apss", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qss_ddrss_cfg =3D { + .name =3D "qss_ddrss_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qxs_boot_imem =3D { + .name =3D "qxs_boot_imem", + .channels =3D 1, + .buswidth =3D 16, +}; + +static struct qcom_icc_node qxs_imem =3D { + .name =3D "qxs_imem", + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qxs_modem_boot_imem =3D { + .name =3D "qxs_modem_boot_imem", + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node srvc_cnoc_main =3D { + .name =3D "srvc_cnoc_main", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_pcie_0 =3D { + .name =3D "xs_pcie_0", + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node xs_pcie_1 =3D { + .name =3D "xs_pcie_1", + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node ebi =3D { + .name =3D "ebi", + .channels =3D 4, + .buswidth =3D 4, +}; + +static struct qcom_icc_node srvc_mnoc_sf =3D { + .name =3D "srvc_mnoc_sf", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node srvc_mnoc_hf =3D { + .name =3D "srvc_mnoc_hf", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node srvc_pcie_aggre_noc =3D { + .name =3D "srvc_pcie_aggre_noc", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qup1_core_master =3D { + .name =3D "qup1_core_master", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qup1_core_slave }, +}; + +static struct qcom_icc_node qup2_core_master =3D { + .name =3D "qup2_core_master", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qup2_core_slave }, +}; + +static struct qcom_icc_node qnm_gemnoc_pcie =3D { + .name =3D "qnm_gemnoc_pcie", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 2, + .link_nodes =3D { &xs_pcie_0, &xs_pcie_1 }, +}; + +static struct qcom_icc_node llcc_mc =3D { + .name =3D "llcc_mc", + .channels =3D 4, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &ebi }, +}; + +static struct qcom_icc_node qsm_sf_mnoc_cfg =3D { + .name =3D "qsm_sf_mnoc_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &srvc_mnoc_sf }, +}; + +static struct qcom_icc_node qsm_hf_mnoc_cfg =3D { + .name =3D "qsm_hf_mnoc_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &srvc_mnoc_hf }, +}; + +static struct qcom_icc_node qsm_pcie_anoc_cfg =3D { + .name =3D "qsm_pcie_anoc_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &srvc_pcie_aggre_noc }, +}; + +static struct qcom_icc_node qss_mnoc_hf_cfg =3D { + .name =3D "qss_mnoc_hf_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qsm_hf_mnoc_cfg }, +}; + +static struct qcom_icc_node qss_mnoc_sf_cfg =3D { + .name =3D "qss_mnoc_sf_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qsm_sf_mnoc_cfg }, +}; + +static struct qcom_icc_node qss_pcie_anoc_cfg =3D { + .name =3D "qss_pcie_anoc_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qsm_pcie_anoc_cfg }, +}; + +static struct qcom_icc_node qns_llcc =3D { + .name =3D "qns_llcc", + .channels =3D 2, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &llcc_mc }, +}; + +static struct qcom_icc_node qns_pcie =3D { + .name =3D "qns_pcie", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &qnm_gemnoc_pcie }, +}; + +static struct qcom_icc_node qsm_cfg =3D { + .name =3D "qsm_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 29, + .link_nodes =3D { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_crypto0_cfg, &qhs_display_cfg, + &qhs_gpuss_cfg, &qhs_i3c_ibi0_cfg, + &qhs_i3c_ibi1_cfg, &qhs_imem_cfg, + &qhs_mss_cfg, &qhs_pcie_0_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup1, + &qhs_qup2, &qhs_sdc2, + &qhs_tcsr, &qhs_tlmm, + &qhs_ufs_mem_cfg, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qss_mnoc_hf_cfg, &qss_mnoc_sf_cfg, + &qss_pcie_anoc_cfg, &xs_qdss_stm, + &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_node xm_gic =3D { + .name =3D "xm_gic", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x15d000 }, + .prio =3D 4, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_llcc }, +}; + +static struct qcom_icc_node qss_cfg =3D { + .name =3D "qss_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qsm_cfg }, +}; + +static struct qcom_icc_node qnm_gemnoc_cnoc =3D { + .name =3D "qnm_gemnoc_cnoc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 12, + .link_nodes =3D { &qhs_aoss, &qhs_ipa, + &qhs_ipc_router, &qhs_soccp, + &qhs_tme_cfg, &qss_apss, + &qss_cfg, &qss_ddrss_cfg, + &qxs_boot_imem, &qxs_imem, + &qxs_modem_boot_imem, &srvc_cnoc_main }, +}; + +static struct qcom_icc_node qns_gem_noc_cnoc =3D { + .name =3D "qns_gem_noc_cnoc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &qnm_gemnoc_cnoc }, +}; + +static struct qcom_icc_qosbox alm_gpu_tcu_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x155000 }, + .prio =3D 1, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + +static struct qcom_icc_node alm_gpu_tcu =3D { + .name =3D "alm_gpu_tcu", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &alm_gpu_tcu_qos, + .num_links =3D 2, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_qosbox alm_sys_tcu_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x157000 }, + .prio =3D 6, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + +static struct qcom_icc_node alm_sys_tcu =3D { + .name =3D "alm_sys_tcu", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &alm_sys_tcu_qos, + .num_links =3D 2, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node chm_apps =3D { + .name =3D "chm_apps", + .channels =3D 3, + .buswidth =3D 32, + .num_links =3D 3, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_qosbox qnm_gpu_qos =3D { + .num_ports =3D 2, + .port_offsets =3D { 0x31000, 0xb1000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, +}; + +static struct qcom_icc_node qnm_gpu =3D { + .name =3D "qnm_gpu", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &qnm_gpu_qos, + .num_links =3D 2, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_qosbox qnm_lpass_gemnoc_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x159000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, +}; + +static struct qcom_icc_node qnm_lpass_gemnoc =3D { + .name =3D "qnm_lpass_gemnoc", + .channels =3D 1, + .buswidth =3D 16, + .qosbox =3D &qnm_lpass_gemnoc_qos, + .num_links =3D 3, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_mdsp =3D { + .name =3D "qnm_mdsp", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 3, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_qosbox qnm_mnoc_hf_qos =3D { + .num_ports =3D 2, + .port_offsets =3D { 0x33000, 0xb3000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, +}; + +static struct qcom_icc_node qnm_mnoc_hf =3D { + .name =3D "qnm_mnoc_hf", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &qnm_mnoc_hf_qos, + .num_links =3D 2, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_qosbox qnm_mnoc_sf_qos =3D { + .num_ports =3D 2, + .port_offsets =3D { 0x35000, 0xb5000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 0, +}; + +static struct qcom_icc_node qnm_mnoc_sf =3D { + .name =3D "qnm_mnoc_sf", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &qnm_mnoc_sf_qos, + .num_links =3D 2, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_qosbox qnm_nsp_gemnoc_qos =3D { + .num_ports =3D 2, + .port_offsets =3D { 0x37000, 0xb7000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, +}; + +static struct qcom_icc_node qnm_nsp_gemnoc =3D { + .name =3D "qnm_nsp_gemnoc", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &qnm_nsp_gemnoc_qos, + .num_links =3D 3, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_qosbox qnm_pcie_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x15b000 }, + .prio =3D 2, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, +}; + +static struct qcom_icc_node qnm_pcie =3D { + .name =3D "qnm_pcie", + .channels =3D 1, + .buswidth =3D 16, + .qosbox =3D &qnm_pcie_qos, + .num_links =3D 2, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node qnm_snoc_sf =3D { + .name =3D "qnm_snoc_sf", + .channels =3D 1, + .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x15f000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 3, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qxm_wlan_q6 =3D { + .name =3D "qxm_wlan_q6", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 3, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qns_lpass_ag_noc_gemnoc =3D { + .name =3D "qns_lpass_ag_noc_gemnoc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &qnm_lpass_gemnoc }, +}; + +static struct qcom_icc_node qns_mem_noc_sf =3D { + .name =3D "qns_mem_noc_sf", + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qnm_mnoc_sf }, +}; + +static struct qcom_icc_node qns_mem_noc_hf =3D { + .name =3D "qns_mem_noc_hf", + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qnm_mnoc_hf }, +}; + +static struct qcom_icc_node qns_nsp_gemnoc =3D { + .name =3D "qns_nsp_gemnoc", + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qnm_nsp_gemnoc }, +}; + +static struct qcom_icc_node qns_pcie_mem_noc =3D { + .name =3D "qns_pcie_mem_noc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &qnm_pcie }, +}; + +static struct qcom_icc_node qns_gemnoc_sf =3D { + .name =3D "qns_gemnoc_sf", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &qnm_snoc_sf }, +}; + +static struct qcom_icc_node qnm_lpiaon_noc =3D { + .name =3D "qnm_lpiaon_noc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &qns_lpass_ag_noc_gemnoc }, +}; + +static struct qcom_icc_qosbox qnm_camnoc_nrt_icp_sf_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x25000 }, + .prio =3D 4, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + +static struct qcom_icc_node qnm_camnoc_nrt_icp_sf =3D { + .name =3D "qnm_camnoc_nrt_icp_sf", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &qnm_camnoc_nrt_icp_sf_qos, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_camnoc_rt_cdm_sf =3D { + .name =3D "qnm_camnoc_rt_cdm_sf", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x2c000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_camnoc_sf =3D { + .name =3D "qnm_camnoc_sf", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x26000, 0x27000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video_mvp =3D { + .name =3D "qnm_video_mvp", + .channels =3D 1, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x28000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video_v_cpu =3D { + .name =3D "qnm_video_v_cpu", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x2b000 }, + .prio =3D 4, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_camnoc_hf =3D { + .name =3D "qnm_camnoc_hf", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x64000, 0x65000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_node qnm_mdp =3D { + .name =3D "qnm_mdp", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x66000, 0x67000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_node qxm_nsp =3D { + .name =3D "qxm_nsp", + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qns_nsp_gemnoc }, +}; + +static struct qcom_icc_node xm_pcie3_0 =3D { + .name =3D "xm_pcie3_0", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb000 }, + .prio =3D 3, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_pcie_mem_noc }, +}; + +static struct qcom_icc_node xm_pcie3_1 =3D { + .name =3D "xm_pcie3_1", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xc000 }, + .prio =3D 3, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_pcie_mem_noc }, +}; + +static struct qcom_icc_node qnm_aggre1_noc =3D { + .name =3D "qnm_aggre1_noc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qnm_aggre2_noc =3D { + .name =3D "qnm_aggre2_noc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qnm_cnoc_data =3D { + .name =3D "qnm_cnoc_data", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x1d000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qnm_nsinoc_snoc =3D { + .name =3D "qnm_nsinoc_snoc", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x1c000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qns_a1noc_snoc =3D { + .name =3D "qns_a1noc_snoc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_node qns_a2noc_snoc =3D { + .name =3D "qns_a2noc_snoc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_node qns_lpass_aggnoc =3D { + .name =3D "qns_lpass_aggnoc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &qnm_lpiaon_noc }, +}; + +static struct qcom_icc_node qhm_qspi =3D { + .name =3D "qhm_qspi", + .channels =3D 1, + .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xc000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qhm_qup1 =3D { + .name =3D "qhm_qup1", + .channels =3D 1, + .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xd000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_ufs_mem =3D { + .name =3D "xm_ufs_mem", + .channels =3D 1, + .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xf000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_usb3_0 =3D { + .name =3D "xm_usb3_0", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x10000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qhm_qup2 =3D { + .name =3D "qhm_qup2", + .channels =3D 1, + .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x14000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qxm_crypto =3D { + .name =3D "qxm_crypto", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x15000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qxm_ipa =3D { + .name =3D "qxm_ipa", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x16000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qxm_soccp =3D { + .name =3D "qxm_soccp", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x1a000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node xm_qdss_etr_0 =3D { + .name =3D "xm_qdss_etr_0", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x17000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node xm_qdss_etr_1 =3D { + .name =3D "xm_qdss_etr_1", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x18000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node xm_sdc1 =3D { + .name =3D "xm_sdc1", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x13000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node xm_sdc2 =3D { + .name =3D "xm_sdc2", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x19000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qnm_lpass_lpinoc =3D { + .name =3D "qnm_lpass_lpinoc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &qns_lpass_aggnoc }, +}; + +static struct qcom_icc_node qns_lpi_aon_noc =3D { + .name =3D "qns_lpi_aon_noc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &qnm_lpass_lpinoc }, +}; + +static struct qcom_icc_node qxm_lpinoc_dsp_axim =3D { + .name =3D "qxm_lpinoc_dsp_axim", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &qns_lpi_aon_noc }, +}; + +static struct qcom_icc_bcm bcm_ce0 =3D { + .name =3D "CE0", + .num_nodes =3D 1, + .nodes =3D { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 =3D { + .name =3D "CN0", + .enable_mask =3D BIT(0), + .keepalive =3D true, + .num_nodes =3D 43, + .nodes =3D { &qsm_cfg, &qhs_ahb2phy0, + &qhs_ahb2phy1, &qhs_camera_cfg, + &qhs_clk_ctl, &qhs_crypto0_cfg, + &qhs_gpuss_cfg, &qhs_i3c_ibi0_cfg, + &qhs_i3c_ibi1_cfg, &qhs_imem_cfg, + &qhs_mss_cfg, &qhs_pcie_0_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_sdc2, + &qhs_tcsr, &qhs_tlmm, + &qhs_ufs_mem_cfg, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qss_mnoc_hf_cfg, &qss_mnoc_sf_cfg, + &qss_pcie_anoc_cfg, &xs_qdss_stm, + &xs_sys_tcu_cfg, &qnm_gemnoc_cnoc, + &qnm_gemnoc_pcie, &qhs_aoss, + &qhs_ipa, &qhs_ipc_router, + &qhs_soccp, &qhs_tme_cfg, + &qss_apss, &qss_cfg, + &qss_ddrss_cfg, &qxs_boot_imem, + &qxs_imem, &qxs_modem_boot_imem, + &srvc_cnoc_main, &xs_pcie_0, + &xs_pcie_1 }, +}; + +static struct qcom_icc_bcm bcm_cn1 =3D { + .name =3D "CN1", + .num_nodes =3D 3, + .nodes =3D { &qhs_display_cfg, &qhs_qup1, + &qhs_qup2 }, +}; + +static struct qcom_icc_bcm bcm_co0 =3D { + .name =3D "CO0", + .enable_mask =3D BIT(0), + .num_nodes =3D 2, + .nodes =3D { &qxm_nsp, &qns_nsp_gemnoc }, +}; + +static struct qcom_icc_bcm bcm_lp0 =3D { + .name =3D "LP0", + .num_nodes =3D 2, + .nodes =3D { &qnm_lpass_lpinoc, &qns_lpass_aggnoc }, +}; + +static struct qcom_icc_bcm bcm_mc0 =3D { + .name =3D "MC0", + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mm0 =3D { + .name =3D "MM0", + .num_nodes =3D 1, + .nodes =3D { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_mm1 =3D { + .name =3D "MM1", + .enable_mask =3D BIT(0), + .num_nodes =3D 7, + .nodes =3D { &qnm_camnoc_nrt_icp_sf, &qnm_camnoc_rt_cdm_sf, + &qnm_camnoc_sf, &qnm_video_mvp, + &qnm_video_v_cpu, &qnm_camnoc_hf, + &qns_mem_noc_sf }, +}; + +static struct qcom_icc_bcm bcm_qup1 =3D { + .name =3D "QUP1", + .vote_scale =3D 1, + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &qup1_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup2 =3D { + .name =3D "QUP2", + .vote_scale =3D 1, + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &qup2_core_slave }, +}; + +static struct qcom_icc_bcm bcm_sh0 =3D { + .name =3D "SH0", + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh1 =3D { + .name =3D "SH1", + .enable_mask =3D BIT(0), + .num_nodes =3D 14, + .nodes =3D { &alm_gpu_tcu, &alm_sys_tcu, + &chm_apps, &qnm_gpu, + &qnm_mdsp, &qnm_mnoc_hf, + &qnm_mnoc_sf, &qnm_nsp_gemnoc, + &qnm_pcie, &qnm_snoc_sf, + &qxm_wlan_q6, &xm_gic, + &qns_gem_noc_cnoc, &qns_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn0 =3D { + .name =3D "SN0", + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn2 =3D { + .name =3D "SN2", + .num_nodes =3D 1, + .nodes =3D { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn3 =3D { + .name =3D "SN3", + .num_nodes =3D 1, + .nodes =3D { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn4 =3D { + .name =3D "SN4", + .num_nodes =3D 1, + .nodes =3D { &qns_pcie_mem_noc }, +}; + +static struct qcom_icc_node * const aggre1_noc_nodes[] =3D { + [MASTER_QSPI_0] =3D &qhm_qspi, + [MASTER_QUP_1] =3D &qhm_qup1, + [MASTER_UFS_MEM] =3D &xm_ufs_mem, + [MASTER_USB3_0] =3D &xm_usb3_0, + [SLAVE_A1NOC_SNOC] =3D &qns_a1noc_snoc, +}; + +static const struct qcom_icc_desc eliza_aggre1_noc =3D { + .nodes =3D aggre1_noc_nodes, + .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), + .qos_requires_clocks =3D true, +}; + +static struct qcom_icc_bcm * const aggre2_noc_bcms[] =3D { + &bcm_ce0, +}; + +static struct qcom_icc_node * const aggre2_noc_nodes[] =3D { + [MASTER_QUP_2] =3D &qhm_qup2, + [MASTER_CRYPTO] =3D &qxm_crypto, + [MASTER_IPA] =3D &qxm_ipa, + [MASTER_SOCCP_AGGR_NOC] =3D &qxm_soccp, + [MASTER_QDSS_ETR] =3D &xm_qdss_etr_0, + [MASTER_QDSS_ETR_1] =3D &xm_qdss_etr_1, + [MASTER_SDCC_1] =3D &xm_sdc1, + [MASTER_SDCC_2] =3D &xm_sdc2, + [SLAVE_A2NOC_SNOC] =3D &qns_a2noc_snoc, +}; + +static const struct qcom_icc_desc eliza_aggre2_noc =3D { + .nodes =3D aggre2_noc_nodes, + .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), + .bcms =3D aggre2_noc_bcms, + .num_bcms =3D ARRAY_SIZE(aggre2_noc_bcms), + .qos_requires_clocks =3D true, +}; + +static struct qcom_icc_bcm * const clk_virt_bcms[] =3D { + &bcm_qup1, + &bcm_qup2, +}; + +static struct qcom_icc_node * const clk_virt_nodes[] =3D { + [MASTER_QUP_CORE_1] =3D &qup1_core_master, + [MASTER_QUP_CORE_2] =3D &qup2_core_master, + [SLAVE_QUP_CORE_1] =3D &qup1_core_slave, + [SLAVE_QUP_CORE_2] =3D &qup2_core_slave, +}; + +static const struct qcom_icc_desc eliza_clk_virt =3D { + .nodes =3D clk_virt_nodes, + .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), + .bcms =3D clk_virt_bcms, + .num_bcms =3D ARRAY_SIZE(clk_virt_bcms), +}; + +static struct qcom_icc_bcm * const cnoc_cfg_bcms[] =3D { + &bcm_cn0, + &bcm_cn1, +}; + +static struct qcom_icc_node * const cnoc_cfg_nodes[] =3D { + [MASTER_CNOC_CFG] =3D &qsm_cfg, + [SLAVE_AHB2PHY_SOUTH] =3D &qhs_ahb2phy0, + [SLAVE_AHB2PHY_NORTH] =3D &qhs_ahb2phy1, + [SLAVE_CAMERA_CFG] =3D &qhs_camera_cfg, + [SLAVE_CLK_CTL] =3D &qhs_clk_ctl, + [SLAVE_CRYPTO_0_CFG] =3D &qhs_crypto0_cfg, + [SLAVE_DISPLAY_CFG] =3D &qhs_display_cfg, + [SLAVE_GFX3D_CFG] =3D &qhs_gpuss_cfg, + [SLAVE_I3C_IBI0_CFG] =3D &qhs_i3c_ibi0_cfg, + [SLAVE_I3C_IBI1_CFG] =3D &qhs_i3c_ibi1_cfg, + [SLAVE_IMEM_CFG] =3D &qhs_imem_cfg, + [SLAVE_CNOC_MSS] =3D &qhs_mss_cfg, + [SLAVE_PCIE_0_CFG] =3D &qhs_pcie_0_cfg, + [SLAVE_PRNG] =3D &qhs_prng, + [SLAVE_QDSS_CFG] =3D &qhs_qdss_cfg, + [SLAVE_QSPI_0] =3D &qhs_qspi, + [SLAVE_QUP_1] =3D &qhs_qup1, + [SLAVE_QUP_2] =3D &qhs_qup2, + [SLAVE_SDCC_2] =3D &qhs_sdc2, + [SLAVE_TCSR] =3D &qhs_tcsr, + [SLAVE_TLMM] =3D &qhs_tlmm, + [SLAVE_UFS_MEM_CFG] =3D &qhs_ufs_mem_cfg, + [SLAVE_USB3_0] =3D &qhs_usb3_0, + [SLAVE_VENUS_CFG] =3D &qhs_venus_cfg, + [SLAVE_VSENSE_CTRL_CFG] =3D &qhs_vsense_ctrl_cfg, + [SLAVE_CNOC_MNOC_HF_CFG] =3D &qss_mnoc_hf_cfg, + [SLAVE_CNOC_MNOC_SF_CFG] =3D &qss_mnoc_sf_cfg, + [SLAVE_PCIE_ANOC_CFG] =3D &qss_pcie_anoc_cfg, + [SLAVE_QDSS_STM] =3D &xs_qdss_stm, + [SLAVE_TCU] =3D &xs_sys_tcu_cfg, +}; + +static const struct qcom_icc_desc eliza_cnoc_cfg =3D { + .nodes =3D cnoc_cfg_nodes, + .num_nodes =3D ARRAY_SIZE(cnoc_cfg_nodes), + .bcms =3D cnoc_cfg_bcms, + .num_bcms =3D ARRAY_SIZE(cnoc_cfg_bcms), +}; + +static struct qcom_icc_bcm * const cnoc_main_bcms[] =3D { + &bcm_cn0, +}; + +static struct qcom_icc_node * const cnoc_main_nodes[] =3D { + [MASTER_GEM_NOC_CNOC] =3D &qnm_gemnoc_cnoc, + [MASTER_GEM_NOC_PCIE_SNOC] =3D &qnm_gemnoc_pcie, + [SLAVE_AOSS] =3D &qhs_aoss, + [SLAVE_IPA_CFG] =3D &qhs_ipa, + [SLAVE_IPC_ROUTER_CFG] =3D &qhs_ipc_router, + [SLAVE_SOCCP] =3D &qhs_soccp, + [SLAVE_TME_CFG] =3D &qhs_tme_cfg, + [SLAVE_APPSS] =3D &qss_apss, + [SLAVE_CNOC_CFG] =3D &qss_cfg, + [SLAVE_DDRSS_CFG] =3D &qss_ddrss_cfg, + [SLAVE_BOOT_IMEM] =3D &qxs_boot_imem, + [SLAVE_IMEM] =3D &qxs_imem, + [SLAVE_BOOT_IMEM_2] =3D &qxs_modem_boot_imem, + [SLAVE_SERVICE_CNOC] =3D &srvc_cnoc_main, + [SLAVE_PCIE_0] =3D &xs_pcie_0, + [SLAVE_PCIE_1] =3D &xs_pcie_1, +}; + +static const struct qcom_icc_desc eliza_cnoc_main =3D { + .nodes =3D cnoc_main_nodes, + .num_nodes =3D ARRAY_SIZE(cnoc_main_nodes), + .bcms =3D cnoc_main_bcms, + .num_bcms =3D ARRAY_SIZE(cnoc_main_bcms), +}; + +static struct qcom_icc_bcm * const gem_noc_bcms[] =3D { + &bcm_sh0, + &bcm_sh1, +}; + +static struct qcom_icc_node * const gem_noc_nodes[] =3D { + [MASTER_GPU_TCU] =3D &alm_gpu_tcu, + [MASTER_SYS_TCU] =3D &alm_sys_tcu, + [MASTER_APPSS_PROC] =3D &chm_apps, + [MASTER_GFX3D] =3D &qnm_gpu, + [MASTER_LPASS_GEM_NOC] =3D &qnm_lpass_gemnoc, + [MASTER_MSS_PROC] =3D &qnm_mdsp, + [MASTER_MNOC_HF_MEM_NOC] =3D &qnm_mnoc_hf, + [MASTER_MNOC_SF_MEM_NOC] =3D &qnm_mnoc_sf, + [MASTER_COMPUTE_NOC] =3D &qnm_nsp_gemnoc, + [MASTER_ANOC_PCIE_GEM_NOC] =3D &qnm_pcie, + [MASTER_SNOC_SF_MEM_NOC] =3D &qnm_snoc_sf, + [MASTER_WLAN_Q6] =3D &qxm_wlan_q6, + [MASTER_GIC] =3D &xm_gic, + [SLAVE_GEM_NOC_CNOC] =3D &qns_gem_noc_cnoc, + [SLAVE_LLCC] =3D &qns_llcc, + [SLAVE_MEM_NOC_PCIE_SNOC] =3D &qns_pcie, +}; + +static const struct qcom_icc_desc eliza_gem_noc =3D { + .nodes =3D gem_noc_nodes, + .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), + .bcms =3D gem_noc_bcms, + .num_bcms =3D ARRAY_SIZE(gem_noc_bcms), +}; + +static struct qcom_icc_node * const lpass_ag_noc_nodes[] =3D { + [MASTER_LPIAON_NOC] =3D &qnm_lpiaon_noc, + [SLAVE_LPASS_GEM_NOC] =3D &qns_lpass_ag_noc_gemnoc, +}; + +static const struct qcom_icc_desc eliza_lpass_ag_noc =3D { + .nodes =3D lpass_ag_noc_nodes, + .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), +}; + +static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] =3D { + &bcm_lp0, +}; + +static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] =3D { + [MASTER_LPASS_LPINOC] =3D &qnm_lpass_lpinoc, + [SLAVE_LPIAON_NOC_LPASS_AG_NOC] =3D &qns_lpass_aggnoc, +}; + +static const struct qcom_icc_desc eliza_lpass_lpiaon_noc =3D { + .nodes =3D lpass_lpiaon_noc_nodes, + .num_nodes =3D ARRAY_SIZE(lpass_lpiaon_noc_nodes), + .bcms =3D lpass_lpiaon_noc_bcms, + .num_bcms =3D ARRAY_SIZE(lpass_lpiaon_noc_bcms), +}; + +static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] =3D { + [MASTER_LPASS_PROC] =3D &qxm_lpinoc_dsp_axim, + [SLAVE_LPICX_NOC_LPIAON_NOC] =3D &qns_lpi_aon_noc, +}; + +static const struct qcom_icc_desc eliza_lpass_lpicx_noc =3D { + .nodes =3D lpass_lpicx_noc_nodes, + .num_nodes =3D ARRAY_SIZE(lpass_lpicx_noc_nodes), +}; + +static struct qcom_icc_bcm * const mc_virt_bcms[] =3D { + &bcm_mc0, +}; + +static struct qcom_icc_node * const mc_virt_nodes[] =3D { + [MASTER_LLCC] =3D &llcc_mc, + [SLAVE_EBI1] =3D &ebi, +}; + +static const struct qcom_icc_desc eliza_mc_virt =3D { + .nodes =3D mc_virt_nodes, + .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), + .bcms =3D mc_virt_bcms, + .num_bcms =3D ARRAY_SIZE(mc_virt_bcms), +}; + +static struct qcom_icc_bcm * const mmss_noc_bcms[] =3D { + &bcm_mm0, + &bcm_mm1, +}; + +static struct qcom_icc_node * const mmss_noc_nodes[] =3D { + [MASTER_CAMNOC_NRT_ICP_SF] =3D &qnm_camnoc_nrt_icp_sf, + [MASTER_CAMNOC_RT_CDM_SF] =3D &qnm_camnoc_rt_cdm_sf, + [MASTER_CAMNOC_SF] =3D &qnm_camnoc_sf, + [MASTER_VIDEO_MVP] =3D &qnm_video_mvp, + [MASTER_VIDEO_V_PROC] =3D &qnm_video_v_cpu, + [MASTER_CNOC_MNOC_SF_CFG] =3D &qsm_sf_mnoc_cfg, + [MASTER_CAMNOC_HF] =3D &qnm_camnoc_hf, + [MASTER_MDP] =3D &qnm_mdp, + [MASTER_CNOC_MNOC_HF_CFG] =3D &qsm_hf_mnoc_cfg, + [SLAVE_MNOC_SF_MEM_NOC] =3D &qns_mem_noc_sf, + [SLAVE_SERVICE_MNOC_SF] =3D &srvc_mnoc_sf, + [SLAVE_MNOC_HF_MEM_NOC] =3D &qns_mem_noc_hf, + [SLAVE_SERVICE_MNOC_HF] =3D &srvc_mnoc_hf, +}; + +static const struct qcom_icc_desc eliza_mmss_noc =3D { + .nodes =3D mmss_noc_nodes, + .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), + .bcms =3D mmss_noc_bcms, + .num_bcms =3D ARRAY_SIZE(mmss_noc_bcms), +}; + +static struct qcom_icc_bcm * const nsp_noc_bcms[] =3D { + &bcm_co0, +}; + +static struct qcom_icc_node * const nsp_noc_nodes[] =3D { + [MASTER_CDSP_PROC] =3D &qxm_nsp, + [SLAVE_CDSP_MEM_NOC] =3D &qns_nsp_gemnoc, +}; + +static const struct qcom_icc_desc eliza_nsp_noc =3D { + .nodes =3D nsp_noc_nodes, + .num_nodes =3D ARRAY_SIZE(nsp_noc_nodes), + .bcms =3D nsp_noc_bcms, + .num_bcms =3D ARRAY_SIZE(nsp_noc_bcms), +}; + +static struct qcom_icc_bcm * const pcie_anoc_bcms[] =3D { + &bcm_sn4, +}; + +static struct qcom_icc_node * const pcie_anoc_nodes[] =3D { + [MASTER_PCIE_ANOC_CFG] =3D &qsm_pcie_anoc_cfg, + [MASTER_PCIE_0] =3D &xm_pcie3_0, + [MASTER_PCIE_1] =3D &xm_pcie3_1, + [SLAVE_ANOC_PCIE_GEM_NOC] =3D &qns_pcie_mem_noc, + [SLAVE_SERVICE_PCIE_ANOC] =3D &srvc_pcie_aggre_noc, +}; + +static const struct qcom_icc_desc eliza_pcie_anoc =3D { + .nodes =3D pcie_anoc_nodes, + .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), + .bcms =3D pcie_anoc_bcms, + .num_bcms =3D ARRAY_SIZE(pcie_anoc_bcms), + .qos_requires_clocks =3D true, +}; + +static struct qcom_icc_bcm * const system_noc_bcms[] =3D { + &bcm_sn0, + &bcm_sn2, + &bcm_sn3, +}; + +static struct qcom_icc_node * const system_noc_nodes[] =3D { + [MASTER_A1NOC_SNOC] =3D &qnm_aggre1_noc, + [MASTER_A2NOC_SNOC] =3D &qnm_aggre2_noc, + [MASTER_CNOC_SNOC] =3D &qnm_cnoc_data, + [MASTER_NSINOC_SNOC] =3D &qnm_nsinoc_snoc, + [SLAVE_SNOC_GEM_NOC_SF] =3D &qns_gemnoc_sf, +}; + +static const struct qcom_icc_desc eliza_system_noc =3D { + .nodes =3D system_noc_nodes, + .num_nodes =3D ARRAY_SIZE(system_noc_nodes), + .bcms =3D system_noc_bcms, + .num_bcms =3D ARRAY_SIZE(system_noc_bcms), +}; + +static const struct of_device_id qnoc_of_match[] =3D { + { .compatible =3D "qcom,eliza-aggre1-noc", .data =3D &eliza_aggre1_noc }, + { .compatible =3D "qcom,eliza-aggre2-noc", .data =3D &eliza_aggre2_noc }, + { .compatible =3D "qcom,eliza-clk-virt", .data =3D &eliza_clk_virt }, + { .compatible =3D "qcom,eliza-cnoc-cfg", .data =3D &eliza_cnoc_cfg }, + { .compatible =3D "qcom,eliza-cnoc-main", .data =3D &eliza_cnoc_main }, + { .compatible =3D "qcom,eliza-gem-noc", .data =3D &eliza_gem_noc }, + { .compatible =3D "qcom,eliza-lpass-ag-noc", .data =3D &eliza_lpass_ag_no= c }, + { .compatible =3D "qcom,eliza-lpass-lpiaon-noc", .data =3D &eliza_lpass_l= piaon_noc }, + { .compatible =3D "qcom,eliza-lpass-lpicx-noc", .data =3D &eliza_lpass_lp= icx_noc }, + { .compatible =3D "qcom,eliza-mc-virt", .data =3D &eliza_mc_virt }, + { .compatible =3D "qcom,eliza-mmss-noc", .data =3D &eliza_mmss_noc }, + { .compatible =3D "qcom,eliza-nsp-noc", .data =3D &eliza_nsp_noc }, + { .compatible =3D "qcom,eliza-pcie-anoc", .data =3D &eliza_pcie_anoc }, + { .compatible =3D "qcom,eliza-system-noc", .data =3D &eliza_system_noc }, + { } +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver =3D { + .probe =3D qcom_icc_rpmh_probe, + .remove =3D qcom_icc_rpmh_remove, + .driver =3D { + .name =3D "qnoc-eliza", + .of_match_table =3D qnoc_of_match, + .sync_state =3D icc_sync_state, + }, +}; + +static int __init qnoc_driver_init(void) +{ + return platform_driver_register(&qnoc_driver); +} +core_initcall(qnoc_driver_init); + +static void __exit qnoc_driver_exit(void) +{ + platform_driver_unregister(&qnoc_driver); +} +module_exit(qnoc_driver_exit); + +MODULE_DESCRIPTION(" Qualcomm Eliza NoC driver"); +MODULE_LICENSE("GPL"); --=20 2.48.1