From nobody Fri Apr 17 04:49:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D548218CBE1; Mon, 23 Feb 2026 13:58:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771855094; cv=none; b=VVA1E/Wz2QNGqx7/hBQWUUD+LreTt/EGaNkWhVrLREYVNAvNUu6DD5abMJQ8D7pwFs6QEgezNM957EomLkz5XqJydUy4cx1+D8GFILvu1akZwYRJqPvtmTsOTVwnJdU/v5mlf7WB77c7uYhsf7YN2u00WNWqNLyglGk+Yfrj5SQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771855094; c=relaxed/simple; bh=DjznovYY9GnY3ffzu+BYF+CpnJqumh0Ejt8gP/xAFC0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FdtSiknDBYpD2SMC+2OdgyPq6URtIXQ+YMqxHkb0z5w5wrJRFhFtJXDEQt5b8DlL+r2/iVJ9PSlOpZtgBtCTXmHLM3E9LoZyaAXj2DeZ0KrmJ9poOukEsYue4vgv/cG0QZ6odOvr0m9iGCKygEifUjeqEHgYNxyju/+Bw8ndUUM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=r+baHfSw; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="r+baHfSw" Received: by smtp.kernel.org (Postfix) with ESMTPS id B346FC19424; Mon, 23 Feb 2026 13:58:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1771855094; bh=DjznovYY9GnY3ffzu+BYF+CpnJqumh0Ejt8gP/xAFC0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=r+baHfSwrqu2f3L9q4d2MJkk0sUKotG9SpSFBWFkovWBXoIlJLT98Q6AssTrNaWWj UnjwEqd2HK8+hwpqvH0/H37/gNc3QVvw0KjroHhOsBoIIQq/7qRtIBacGmRtKs9zd1 J8abbEXpn9o+V8Pm3H8SoFNS1Hye/PLbjib9BT1GOvAquuqN3MxG7FLUEwr8C95waF f6DXUHoNODcSPpdrVknNPjceepy4/zBPtuAq5JW7mJzsuK4WGndoMl51//j+737zmQ 0mZo2wpjWyK+haq0FyOJlsD74FyxKrYuzSR55oA1c4QeYQ2gBT6t+c028obEh0mP3Y qphqq3NHQZAqg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4956EA4FC2; Mon, 23 Feb 2026 13:58:14 +0000 (UTC) From: Jan Petrous via B4 Relay Date: Mon, 23 Feb 2026 14:58:04 +0100 Subject: [PATCH v5 1/4] net: stmmac: platform: read channels irq Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260223-dwmac_multi_irq-v5-1-8fc699a5fac4@oss.nxp.com> References: <20260223-dwmac_multi_irq-v5-0-8fc699a5fac4@oss.nxp.com> In-Reply-To: <20260223-dwmac_multi_irq-v5-0-8fc699a5fac4@oss.nxp.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, "Jan Petrous (OSS)" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771855093; l=2333; i=jan.petrous@oss.nxp.com; s=20240922; h=from:subject:message-id; bh=P2zfXa4c18tSAED8W/f714pESbYNY0ZOt8TdNWG7VK0=; b=hiXarSrsA/JbiyKr+PsMd6bbjrGyHXX8vk7ry0gBoLO10unCvRxYzZb5C9C9xTtP2sfCSNG6y lDgDWZJqVCYDGYHr4WLUBkolMSdTx7eXCG92CyX+8rPkB9U869DQROt X-Developer-Key: i=jan.petrous@oss.nxp.com; a=ed25519; pk=Ke3wwK7rb2Me9UQRf6vR8AsfJZfhTyoDaxkUCqmSWYY= X-Endpoint-Received: by B4 Relay for jan.petrous@oss.nxp.com/20240922 with auth_id=217 X-Original-From: "Jan Petrous (OSS)" Reply-To: jan.petrous@oss.nxp.com From: "Jan Petrous (OSS)" Read IRQ resources for all rx/tx channels, to allow Multi-IRQ mode for platform glue drivers. Reviewed-by: Matthias Brugger Signed-off-by: Jan Petrous (OSS) --- .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 40 ++++++++++++++++++= +++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/driver= s/net/ethernet/stmicro/stmmac/stmmac_platform.c index 5c9fd91a1db9..6166a9b0c0bb 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -700,6 +700,9 @@ EXPORT_SYMBOL_GPL(stmmac_pltfr_find_clk); int stmmac_get_platform_resources(struct platform_device *pdev, struct stmmac_resources *stmmac_res) { + char name[16]; + int i; + memset(stmmac_res, 0, sizeof(*stmmac_res)); =20 /* Get IRQ information early to have an ability to ask for deferred @@ -735,7 +738,42 @@ int stmmac_get_platform_resources(struct platform_devi= ce *pdev, =20 stmmac_res->addr =3D devm_platform_ioremap_resource(pdev, 0); =20 - return PTR_ERR_OR_ZERO(stmmac_res->addr); + if (IS_ERR(stmmac_res->addr)) + return PTR_ERR(stmmac_res->addr); + + /* RX channels irq */ + for (i =3D 0; i < MTL_MAX_RX_QUEUES; i++) { + scnprintf(name, sizeof(name), "rx-queue-%d", i); + stmmac_res->rx_irq[i] =3D platform_get_irq_byname_optional(pdev, + name); + if (stmmac_res->rx_irq[i] <=3D 0) { + if (stmmac_res->rx_irq[i] =3D=3D -EPROBE_DEFER) + return -EPROBE_DEFER; + dev_dbg(&pdev->dev, "IRQ rx-queue-%d not found\n", i); + + /* Stop on first unset rx-queue-%i property member */ + stmmac_res->rx_irq[i] =3D 0; + break; + } + } + + /* TX channels irq */ + for (i =3D 0; i < MTL_MAX_TX_QUEUES; i++) { + scnprintf(name, sizeof(name), "tx-queue-%d", i); + stmmac_res->tx_irq[i] =3D platform_get_irq_byname_optional(pdev, + name); + if (stmmac_res->tx_irq[i] <=3D 0) { + if (stmmac_res->tx_irq[i] =3D=3D -EPROBE_DEFER) + return -EPROBE_DEFER; + dev_dbg(&pdev->dev, "IRQ tx-queue-%d not found\n", i); + + /* Stop on first unset tx-queue-%i property member */ + stmmac_res->tx_irq[i] =3D 0; + break; + } + } + + return 0; } EXPORT_SYMBOL_GPL(stmmac_get_platform_resources); =20 --=20 2.47.0 From nobody Fri Apr 17 04:49:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E970A26738D; Mon, 23 Feb 2026 13:58:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771855095; cv=none; b=k03zqvUKvI052atpjK7BLmFR4Pzvfj6kTwU+AOOipRS8BOzdPPDKsOri2Mm7H8Z9jXz+JBm5rs0FH6tYCVvDkYSgKgng//69Wu/RRCcLh+4J/7b+/a+6eDXc+8WUlHnpERebl3mqvKfJmHAz9WCEcvIYX6qm3TrId6bRORUmwY4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771855095; c=relaxed/simple; bh=pZOGCtqCdGmQ5EyeK5P9mdp8/Ieo5wfdcMyGgN8hA6M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rhnjLmh0fcnlNW8iGSCjFeGaA9y7Vwvnkieq7M6JPaSqSboBS/Jjm7CBcuWXd3nBe/jM4FDqHMnwEEu4qhpOVnFnIBaayHBSYHthO8WVC32Wb6/tFMYV5sPkBdEOqzDFOGYpm+93A3wxIb7WPQH+IUA4kKmaJPG/66hJTBcvRuM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Si4U1+HH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Si4U1+HH" Received: by smtp.kernel.org (Postfix) with ESMTPS id C9F88C2BCAF; Mon, 23 Feb 2026 13:58:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1771855094; bh=pZOGCtqCdGmQ5EyeK5P9mdp8/Ieo5wfdcMyGgN8hA6M=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Si4U1+HHGDdwApNgCgBU3L4MQ2WynddhvpJZyvjo+g6J7K+XeplI0CAJOklySfS0e OPl1UUWvRBCi/bsKC+r8PLJN18EjyDWRMa+LewmF+vcojnv3Z1HTOMhYXimj2q8Alt jGP2XSYyzzbvgSU4q3j4j5L66c3g6QkFmjbaI3HWzch/ewOCiVKH9ztWeF18hDafR3 awcTse3OCDB61vHADnH8Z1hMgtQWSWyD4kGlzvxvAC4aNRmGOzdhxwlb7PCct7TJpg qbvOxaWBcybn+MPJ49KRTvWMVqqRdEoaoxEZEH10oHtVTiYuuUGM4CfFmBSe1Nd4CO cJo219fdlwUiA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B999BEA4FC3; Mon, 23 Feb 2026 13:58:14 +0000 (UTC) From: Jan Petrous via B4 Relay Date: Mon, 23 Feb 2026 14:58:05 +0100 Subject: [PATCH v5 2/4] dt-bindings: net: nxp,s32-dwmac: Declare per-queue interrupts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260223-dwmac_multi_irq-v5-2-8fc699a5fac4@oss.nxp.com> References: <20260223-dwmac_multi_irq-v5-0-8fc699a5fac4@oss.nxp.com> In-Reply-To: <20260223-dwmac_multi_irq-v5-0-8fc699a5fac4@oss.nxp.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, "Jan Petrous (OSS)" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771855093; l=3405; i=jan.petrous@oss.nxp.com; s=20240922; h=from:subject:message-id; bh=gQkWPW6Agu54gNIpdO0qRffYb4VG4bnlmEhwhDlFr00=; b=jc9lh1vecb9mybYO4ehOuqpkp71pwzZLjz/g/NY9z1MldT2Bur/6GMyRv7wxMXu4VrGEaeWBb jr8N9BQM0QlBhsyM8e4wQrE2T2MIUo+l1T72x+rqWmOeTGtl+PggQ8a X-Developer-Key: i=jan.petrous@oss.nxp.com; a=ed25519; pk=Ke3wwK7rb2Me9UQRf6vR8AsfJZfhTyoDaxkUCqmSWYY= X-Endpoint-Received: by B4 Relay for jan.petrous@oss.nxp.com/20240922 with auth_id=217 X-Original-From: "Jan Petrous (OSS)" Reply-To: jan.petrous@oss.nxp.com From: "Jan Petrous (OSS)" The DWMAC IP on NXP S32G/R SoCs has connected queue-based IRQ lines, set them to allow using Multi-IRQ mode. Reviewed-by: Matthias Brugger Signed-off-by: Jan Petrous (OSS) --- .../devicetree/bindings/net/nxp,s32-dwmac.yaml | 44 ++++++++++++++++++= +--- 1 file changed, 39 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Doc= umentation/devicetree/bindings/net/nxp,s32-dwmac.yaml index 1b2934f3c87c..3a0e41b63c3d 100644 --- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -# Copyright 2021-2024 NXP +# Copyright 2021-2026 NXP %YAML 1.2 --- $id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml# @@ -16,6 +16,8 @@ description: the SoC S32R45 has two instances. The devices can use RGMII/RMII/MII interface over Pinctrl device or the output can be routed to the embedded SerDes for SGMII connectivity. + The DWMAC instances have connected all RX/TX queues interrupts, + enabling load balancing of data traffic across all CPU cores. =20 properties: compatible: @@ -45,10 +47,22 @@ properties: FlexTimer Modules connect to GMAC_0. =20 interrupts: - maxItems: 1 + minItems: 11 + maxItems: 11 =20 interrupt-names: - const: macirq + items: + - const: macirq + - const: tx-queue-0 + - const: rx-queue-0 + - const: tx-queue-1 + - const: rx-queue-1 + - const: tx-queue-2 + - const: rx-queue-2 + - const: tx-queue-3 + - const: rx-queue-3 + - const: tx-queue-4 + - const: rx-queue-4 =20 clocks: items: @@ -88,8 +102,28 @@ examples: <0x0 0x4007c004 0x0 0x4>; /* GMAC_0_CTRL_STS */ nxp,phy-sel =3D <&gpr 0x4>; interrupt-parent =3D <&gic>; - interrupts =3D ; - interrupt-names =3D "macirq"; + interrupts =3D , + /* CHN 0: tx, rx */ + , + , + /* CHN 1: tx, rx */ + , + , + /* CHN 2: tx, rx */ + , + , + /* CHN 3: tx, rx */ + , + , + /* CHN 4: tx, rx */ + , + ; + interrupt-names =3D "macirq", + "tx-queue-0", "rx-queue-0", + "tx-queue-1", "rx-queue-1", + "tx-queue-2", "rx-queue-2", + "tx-queue-3", "rx-queue-3", + "tx-queue-4", "rx-queue-4"; snps,mtl-rx-config =3D <&mtl_rx_setup>; snps,mtl-tx-config =3D <&mtl_tx_setup>; clocks =3D <&clks 24>, <&clks 17>, <&clks 16>, <&clks 15>; --=20 2.47.0 From nobody Fri Apr 17 04:49:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 22B182701BB; Mon, 23 Feb 2026 13:58:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771855095; cv=none; b=DcbCGlT368MLxufATVnGY2kn9mI6dsF9RpijujOmNDyfBgqKCt9F8mkIhwuce9fecyg48TPbPSb6rCKKVo+BEBGFu5QCEMb218IgN1EYnfaVuRQIt8EtpE+1wHkG0pYEuXf9h5KGT9Kc31rhGe3dSVBrpKv2awe7NZQrNjjNm5A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771855095; c=relaxed/simple; bh=t5KwaNb/RUlMNvnjAQljSY30lTI+e060jlUtQ9txKe8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EzqRH1nojGhsP2x41SXhpEqv77cBI8fQmQjifURc53zOd/E4ye6zevlJ8n5dSvZ5CijSUO+MeLvG84cElrsLrVBdi9Oq/7uf0A61NdJs1ZthCzELJl6KbArS1Lre6hypg8m2Yq/kocE9pIjXQXsiYg0PUGF73K77L90GX4kod1M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CB0i1sYa; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CB0i1sYa" Received: by smtp.kernel.org (Postfix) with ESMTPS id D5178C2BC87; Mon, 23 Feb 2026 13:58:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1771855094; bh=t5KwaNb/RUlMNvnjAQljSY30lTI+e060jlUtQ9txKe8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=CB0i1sYaGvAKnvJDXjpHisBs89VSjY27mSJhKAj0XGlOraz8vvxd2/WyynOn4xUJj b2hg9udlqGeeiJIN1vL1iTYASn+XRKntSYGERBlxiVDMXx4bL1Bg4I1dZM6nlRXvQJ koDoawYnCB6tVDFudFvVOV4BqtgZGRQohybGp28nESZEmUGoNw/Gv3jRTUDSaoYd1A vRHlQxPfM4FWrUWSW1z/WZknkWf59fkv4eKF8z2RGKZfvUJjbkIrVKNoGQ5HlVmd13 ETu9twtV70eXq/Tn3suvMZacDyPHnifgdHOhURSbT/DyT70tg1GPHGbsfW0LmZEMj9 GFaxrGk0Ak98g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB717EA4FC1; Mon, 23 Feb 2026 13:58:14 +0000 (UTC) From: Jan Petrous via B4 Relay Date: Mon, 23 Feb 2026 14:58:06 +0100 Subject: [PATCH v5 3/4] arm64: dts: s32: set Ethernet channel irqs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260223-dwmac_multi_irq-v5-3-8fc699a5fac4@oss.nxp.com> References: <20260223-dwmac_multi_irq-v5-0-8fc699a5fac4@oss.nxp.com> In-Reply-To: <20260223-dwmac_multi_irq-v5-0-8fc699a5fac4@oss.nxp.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, "Jan Petrous (OSS)" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771855093; l=4163; i=jan.petrous@oss.nxp.com; s=20240922; h=from:subject:message-id; bh=GJtLVXXJ6B4rcW9eI+Zdnzjbg44iN/frnopr12Ti4EU=; b=TmoJDDNlTmMgV+Qqkl8ZoPkRk6WcQvMR/GbsNwsLdbJ2rG5Dyepdv0jdKiQzldQ7FqOj9HWgF u+Wyy0NwaVWAFSohZpnwMJYVrnBYfIp5UIx3X0ji+TpnxElk+AyTYo+ X-Developer-Key: i=jan.petrous@oss.nxp.com; a=ed25519; pk=Ke3wwK7rb2Me9UQRf6vR8AsfJZfhTyoDaxkUCqmSWYY= X-Endpoint-Received: by B4 Relay for jan.petrous@oss.nxp.com/20240922 with auth_id=217 X-Original-From: "Jan Petrous (OSS)" Reply-To: jan.petrous@oss.nxp.com From: "Jan Petrous (OSS)" The GMAC Ethernet controller found on S32G2/S32G3 and S32R45 contains up to 5 RX and 5 TX channels. It can operate in two interrupt modes: 1) Sharing IRQ mode: only MAC IRQ line is used for all channels. 2) Multiple IRQ mode: every channel uses two IRQ lines, one for RX and second for TX. Specify all IRQ twins for all channels. Reviewed-by: Matthias Brugger Signed-off-by: Jan Petrous (OSS) --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 26 +++++++++++++++++++++++--- arch/arm64/boot/dts/freescale/s32g3.dtsi | 26 +++++++++++++++++++++++--- 2 files changed, 46 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts= /freescale/s32g2.dtsi index 51d00dac12de..5a553d503137 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -3,7 +3,7 @@ * NXP S32G2 SoC family * * Copyright (c) 2021 SUSE LLC - * Copyright 2017-2021, 2024-2025 NXP + * Copyright 2017-2021, 2024-2026 NXP */ =20 #include @@ -732,8 +732,28 @@ gmac0: ethernet@4033c000 { reg =3D <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ interrupt-parent =3D <&gic>; - interrupts =3D ; - interrupt-names =3D "macirq"; + interrupts =3D , + /* CHN 0: tx, rx */ + , + , + /* CHN 1: tx, rx */ + , + , + /* CHN 2: tx, rx */ + , + , + /* CHN 3: tx, rx */ + , + , + /* CHN 4: tx, rx */ + , + ; + interrupt-names =3D "macirq", + "tx-queue-0", "rx-queue-0", + "tx-queue-1", "rx-queue-1", + "tx-queue-2", "rx-queue-2", + "tx-queue-3", "rx-queue-3", + "tx-queue-4", "rx-queue-4"; snps,mtl-rx-config =3D <&mtl_rx_setup>; snps,mtl-tx-config =3D <&mtl_tx_setup>; status =3D "disabled"; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts= /freescale/s32g3.dtsi index e314f3c7d61d..b43e6f001f4d 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright 2021-2025 NXP + * Copyright 2021-2026 NXP * * Authors: Ghennadi Procopciuc * Ciprian Costea @@ -809,8 +809,28 @@ gmac0: ethernet@4033c000 { reg =3D <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ interrupt-parent =3D <&gic>; - interrupts =3D ; - interrupt-names =3D "macirq"; + interrupts =3D , + /* CHN 0: tx, rx */ + , + , + /* CHN 1: tx, rx */ + , + , + /* CHN 2: tx, rx */ + , + , + /* CHN 3: tx, rx */ + , + , + /* CHN 4: tx, rx */ + , + ; + interrupt-names =3D "macirq", + "tx-queue-0", "rx-queue-0", + "tx-queue-1", "rx-queue-1", + "tx-queue-2", "rx-queue-2", + "tx-queue-3", "rx-queue-3", + "tx-queue-4", "rx-queue-4"; snps,mtl-rx-config =3D <&mtl_rx_setup>; snps,mtl-tx-config =3D <&mtl_tx_setup>; status =3D "disabled"; --=20 2.47.0 From nobody Fri Apr 17 04:49:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 22B862701CB; Mon, 23 Feb 2026 13:58:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771855095; cv=none; b=tbKKgtSJ5DCLuvrCZBphoxm+Va5rf9c1wTMWkW9iRgy+IaXofz3tSfV0hvmeNsaTRKMfD0KlLJ/QfU/ThaX18qSiXrUaD/UTbkvkteF/N9iXbFNvJHO/jZ0iV5QQ/tX5vp8Ysgv3+bC7bpFFnMFJJHAL6+bOIiNnl0F0WzahGkA= ARC-Message-Signature: i=1; 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b=E3MAzkDwIOjAm0HWClU6Rvfh5Y2EQNH0mqshoiDVSvkiwQed5Arj1Zuq6KItL78ML Z57NI7NwTsmqFkbfIXtT6hHEtnG9LTwDlCX+gYnL7bTWzWnc4DhIVwwKrfQSyzUwF9 HQ3HseMFYA/xN571OJNGMMTUHKBam4+bKznTqs4n0OCHWr0PnHiLr8fM5Da2EGaW2/ RCS2FD/wG6oag7StV93LMmSo4UnDOWdgMjvelNovUtdxD4Td10bAQ2fGQtYnfLqilr H+OSpm3TqdOGKHtWAy7MPSpooxnlCudQlsofGCn9Fqr96Ao+aWb+dtArWL3HriFXmo 1LdHvGgv7lbhA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD626EA4FC4; Mon, 23 Feb 2026 13:58:14 +0000 (UTC) From: Jan Petrous via B4 Relay Date: Mon, 23 Feb 2026 14:58:07 +0100 Subject: [PATCH v5 4/4] stmmac: s32: enable support for Multi-IRQ mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260223-dwmac_multi_irq-v5-4-8fc699a5fac4@oss.nxp.com> References: <20260223-dwmac_multi_irq-v5-0-8fc699a5fac4@oss.nxp.com> In-Reply-To: <20260223-dwmac_multi_irq-v5-0-8fc699a5fac4@oss.nxp.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, "Jan Petrous (OSS)" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771855093; l=3826; i=jan.petrous@oss.nxp.com; s=20240922; h=from:subject:message-id; bh=jkQq847xhb2eYi7ZpXwtstlwheGp8bBouoJWdRAdL7I=; b=uNAw/qBP+ZRZKnsOp91pohZ5uydpZcNiHmWPoOdZckfvptrqJXOwWX9sN/C0qgOPefhVBXYdz 7wvVGrk5nHJB3XKllqHIcWW+GvPozLi+hQNy+IybBUzVi+kLDhykdu2 X-Developer-Key: i=jan.petrous@oss.nxp.com; a=ed25519; pk=Ke3wwK7rb2Me9UQRf6vR8AsfJZfhTyoDaxkUCqmSWYY= X-Endpoint-Received: by B4 Relay for jan.petrous@oss.nxp.com/20240922 with auth_id=217 X-Original-From: "Jan Petrous (OSS)" Reply-To: jan.petrous@oss.nxp.com From: "Jan Petrous (OSS)" To get enabled Multi-IRQ mode, the driver checks: 1) property of 'snps,mtl-xx-config' subnode defines 'snps,xx-queues-to-use' bigger then one, ie: ethernet@4033c000 { compatible =3D "nxp,s32g2-dwmac"; ... snps,mtl-rx-config =3D <&mtl_rx_setup>; ... mtl_rx_setup: rx-queues-config { snps,rx-queues-to-use =3D <2>; }; 2) queue based IRQs are set, ie: ethernet@4033c000 { compatible =3D "nxp,s32g2-dwmac"; ... interrupts =3D , /* CHN 0: tx, rx */ , , /* CHN 1: tx, rx */ , ; interrupt-names =3D "macirq", "tx-queue-0", "rx-queue-0", "tx-queue-1", "rx-queue-1"; If those prerequisites are met, the driver switch to Multi-IRQ mode, using per-queue IRQs for rx/tx data pathr: [ 1.387045] s32-dwmac 4033c000.ethernet: Multi-IRQ mode (per queue IRQs)= selected Now the driver owns all queues IRQs: root@s32g399aevb3:~# grep eth /proc/interrupts 29: 0 0 0 0 0 0 0 0 GICv3 89 Level eth0:mac 30: 0 0 0 0 0 0 0 0 GICv3 91 Level eth0:rx-0 31: 0 0 0 0 0 0 0 0 GICv3 93 Level eth0:rx-1 32: 0 0 0 0 0 0 0 0 GICv3 95 Level eth0:rx-2 33: 0 0 0 0 0 0 0 0 GICv3 97 Level eth0:rx-3 34: 0 0 0 0 0 0 0 0 GICv3 99 Level eth0:rx-4 35: 0 0 0 0 0 0 0 0 GICv3 90 Level eth0:tx-0 36: 0 0 0 0 0 0 0 0 GICv3 92 Level eth0:tx-1 37: 0 0 0 0 0 0 0 0 GICv3 94 Level eth0:tx-2 38: 0 0 0 0 0 0 0 0 GICv3 96 Level eth0:tx-3 39: 0 0 0 0 0 0 0 0 GICv3 98 Level eth0:tx-4 Otherwise, if one of the prerequisite don't met, the driver continue with MAC IRQ mode: [ 1.387045] s32-dwmac 4033c000.ethernet: MAC IRQ mode selected And only MAC IRQ will be attached: root@s32g399aevb3:~# grep eth /proc/interrupts 29: 0 0 0 0 0 0 0 0 GICv3 89 Level eth0:mac What represents the original MAC IRQ mode and is fully backward compatible. Reviewed-by: Matthias Brugger Signed-off-by: Jan Petrous (OSS) --- drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c b/drivers/net/= ethernet/stmicro/stmmac/dwmac-s32.c index af594a096676..4aad7077c9d6 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c @@ -2,7 +2,7 @@ /* * NXP S32G/R GMAC glue layer * - * Copyright 2019-2024 NXP + * Copyright 2019-2026 NXP * */ =20 @@ -165,6 +165,16 @@ static int s32_dwmac_probe(struct platform_device *pde= v) plat->core_type =3D DWMAC_CORE_GMAC4; plat->pmt =3D 1; plat->flags |=3D STMMAC_FLAG_SPH_DISABLE; + + /* Check for multi-IRQ config. Assumption: symmetrical rx/tx queues */ + if (plat->rx_queues_to_use > 1 && + (res.rx_irq[0] > 0 && res.tx_irq[0] > 0)) { + plat->flags |=3D STMMAC_FLAG_MULTI_MSI_EN; + dev_info(dev, "Multi-IRQ mode (per queue IRQs) selected\n"); + } else { + dev_info(dev, "MAC IRQ mode selected\n"); + } + plat->rx_fifo_size =3D 20480; plat->tx_fifo_size =3D 20480; =20 --=20 2.47.0