From nobody Sun Apr 5 20:06:38 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2B222EFDA4 for ; Mon, 23 Feb 2026 15:38:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771861083; cv=none; b=C8ogcW3Z8z1W756pOREkBf09kB1v5IUO3RIpOYPwbmnKu24J6n3LQk3SoonRTWZk1Pv6MhqZzD7jqSjtTjbSEzUOMSKvVxgBPSEpIWY86QTzxwHtsjUfcvRD8QXz+SL2RBDxqHCJjMUtrhmVYIAPkAz1NemPNJtjACI7Wf5e62w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771861083; c=relaxed/simple; bh=ZJhZIon/fjcaufe2HaSY/5xlurC+ejRJ25ruSgZ0viQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CGo6iAm8WIKYvjP95cbqQGu8JoRUZ60nUzuhpzqQ31pca1x4QTiNYUymP4K66eA0jm+GuBKDhSzWtsAvppDUP5zFDGRE320Wf/PlY3D0hxJjls0VYqyJeyXcXfFH6DYokFcb80F1/0dYmTcj7gSjVGAOwx3MlEkkX7FC9ZdsAgY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=U+ygIY2y; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=E9NG0LgH; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="U+ygIY2y"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="E9NG0LgH" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 61NAYdln322207 for ; Mon, 23 Feb 2026 15:37:59 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= GZxK/NzSSMmuW+dwLBRWgJMn3AMRKMXxbCaIsI3e8/Q=; b=U+ygIY2yAVsQyAFD 1mNWq1mb+zFSkl9KfN5cR+xNWSNFa/JBEXMzB2J+IQI970iWXT3RH6Z8ZtICGy42 2cmZMXCYTataEDM8VccGOP4xVQugMIFgcgi4qxoNixT004+YHk4jnVC6mysTeiDa SJ4Wx3x5jBvERA0UpyPcSvuB0InxbvyuKn+oS5uOOEq9oxEjLAvI/Cw3PZaycg9r K2DWsSOMcUnyTcQ7nHzt+BkbZGiDwEORBEix2ft0xlyEU1wGzmb+k7EZWHwjC2id z7ZSfk+mWFfCZ4OHd0+vxYKVDQ5WUt8q3bcc22h5+ltisSWzLOVuHnMM5pBPKMBr liLuxw== Received: from mail-qk1-f197.google.com (mail-qk1-f197.google.com [209.85.222.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cgn8y0wk7-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 23 Feb 2026 15:37:59 +0000 (GMT) Received: by mail-qk1-f197.google.com with SMTP id af79cd13be357-8cb706313beso631265585a.3 for ; Mon, 23 Feb 2026 07:37:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1771861079; x=1772465879; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=GZxK/NzSSMmuW+dwLBRWgJMn3AMRKMXxbCaIsI3e8/Q=; b=E9NG0LgHySkaC2rFWVHX1Is8u8c+pwSvGA0YAGyPcZH65D/Cu1GVWhfbS+U032LfaP VGD6CbwF+qpA1ZEYJS2usPfswZN8p4qhmsulstP5inTyeA4FtiDamUuUceypPCwVR9pK DeOrDD/p+aa4FXHFUmXS5st6qhsGD3FmgZWRx6AvwlJFTKQzFWRUmiAtB50rAxTedsY5 w80hKxMFLoYy/R/W83ZRV8uy0MXGvOLOzHPfpN2ENAgFfGGsHsNnTmfb3QRzb2ViyeJl 0LT+yacA7Tk9DATRhIhLasWJMol2bEaOPQ5Y6PBPXhW4GbgILTGi3AK/eV0mZ+WOb6T/ +6iQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771861079; x=1772465879; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=GZxK/NzSSMmuW+dwLBRWgJMn3AMRKMXxbCaIsI3e8/Q=; b=H2nEJeNWCxrVixlUYbBKkcGQcz7iy2hNnMa5o2tKRxBPrLAFYbnxFcHjXi8tTw3cbR 59qvPufVPooM6klzfMaxNDvsygTkczUyS28Ac5Awl6//FuxxQyXVZtSl3iKS6MpxxNBo 6aiwGwObMvst33hbH5jsV95N0BrwO7XOfiRjsYl/lmzAtdjzvDUl85l1xceUevEzwmBg 0QH1c2t+KC1YzNc1WJTSNgKj3gHl5/oQfwxDb/LtUozQLPU/vbsY075ci8/FmI7wd8WY o7wY/foo5c9GCiRhHSctpQfVpyVRGvGSA6yBdbaoHHl30rs/MB7VuzMFpOthkbY2vgZs vH1Q== X-Forwarded-Encrypted: i=1; AJvYcCWdn5DHJVkeI3jkXQHVUcqhzBYEKo2QJrfjEOh1CeWVcUZSB1h0/nA+6bc0JtGh2nr5Z3nn1rPnQyStJPY=@vger.kernel.org X-Gm-Message-State: AOJu0YyxGV09innViApPI8gA8uvNuv2CFyPUQ4yvw9hCFm1a6TFoD4Zo 8oPIZ9s51vU1i+Dwsr3SwVuTrQxDjp4Z6aQQsU7p3J+M8LnErrVFZbFIlkXjT3ya2P+33XlUe3w YD3xNaZsKPH6r07w3mjmQvuJQgazdMzAzzxfn7zHiFUSsmrwFqHf2Nib/NTyXhWtWccg= X-Gm-Gg: AZuq6aK9rKVMa2Mfod/vFtbTmgW6sTzI3CmgG/Wd4lbPAWpXikFHgzb72tS42xGAdok O7GIjg2IG+jCJT9kx+nruWhMO9Ti8D6BIERAiAVpGQtcJIZIUuPIMG4QapYqHwZOOL/MN/7B9UP xtzz0T9bBzkPXbWaGSNBmBbNara8PD8Q30bNFr6KRvtDolaIbHePDX0/oIYs7pM1LHS+hTuSyD7 hfkbpIFMmYsn6U0vEM5TPq93P5a8gpQGhJyBhzESPpGmMf8AVgbVgj8BbROHEmSujtrUOHg7X8h NyhHAkC6kOqbosWQxoO69IbhsGW3mDozvA9UhyMV72+hSawbofHdNOu8tubj8yfGsvfm3up6GsZ mez82xweesQggCvq1+d8xauhDC+P23A== X-Received: by 2002:a05:620a:46a9:b0:8cb:2732:81ef with SMTP id af79cd13be357-8cb8ca0d770mr1154473985a.35.1771861078590; Mon, 23 Feb 2026 07:37:58 -0800 (PST) X-Received: by 2002:a05:620a:46a9:b0:8cb:2732:81ef with SMTP id af79cd13be357-8cb8ca0d770mr1154469085a.35.1771861078014; Mon, 23 Feb 2026 07:37:58 -0800 (PST) Received: from hackbox.lan ([86.121.162.109]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43970d4c96csm21880679f8f.30.2026.02.23.07.37.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Feb 2026 07:37:57 -0800 (PST) From: Abel Vesa Date: Mon, 23 Feb 2026 17:37:44 +0200 Subject: [PATCH RFT v2 2/3] arm64: dts: qcom: glymur: Add USB related nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260223-dts-qcom-glymur-add-usb-support-v2-2-f4e0f38db21d@oss.qualcomm.com> References: <20260223-dts-qcom-glymur-add-usb-support-v2-0-f4e0f38db21d@oss.qualcomm.com> In-Reply-To: <20260223-dts-qcom-glymur-add-usb-support-v2-0-f4e0f38db21d@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Wesley Cheng Cc: Pankaj Patil , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, Abel Vesa , Wesley Cheng X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=openpgp-sha256; l=18928; i=abel.vesa@oss.qualcomm.com; h=from:subject:message-id; bh=upt0jnxRG4VtJ/WIK9XnCHDgH9guv0V9Dzpg13vjR6g=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBpnHROpmyZZ/aHStWB07p2JdUpHxTWiHmFx837m A3oABluDXCJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCaZx0TgAKCRAbX0TJAJUV VkdIEACUGJZO2wITTPX11oDRbXdyZhJsAIpUhIf2TTlFgiVON5BIM5Rs/r6g/tmwDuyDKJpWT7J 8zmKSESlVz2JbR0ZFPspcufnzlv+AeCmKDxGaN6+Lc6Fj7ZdS2cufze/zz+wv6dx9bfxzWqoJaS iVlBXnl85+21Jdx5jnogFNQ/zy6JlEWp7MAepkcgkTr3jFcb7FTWU7Oc2qWD5CZ5rB8uTBVUsYu NhfTJMxWD20u94TLQ7Oyh+xVRaVU7FErkw89nq8QwCDyAfauOKT3ilJ58ZQMFLdCBVMWx3Uk3du jnMipsux2fbMimfROiv0nNzR8yQ77H2GNhnpS+H4cvpRZmQL1aYMhrV1f/ww5vVkdqEnBdkaBR7 ltjZ64Rm222xafH3U1CiWBDmAP/AjLfA07coWDN7gc2wZVRsFF/alPwj8BndDcxFFjUnqT94gbx flNGhi/hlBdXut3EYSl5YzoKASz2t1/v3tSWYoCvkqeDP03YVWLh2xA2KuDzDzL5pFv3bsI0wuI hFC9OxCnRMVuS4q3u2DkFR0BlZl9ZUSclhpaSrt8qmENiYIsIYdF7FiTFisuWPWnLyXX2zoWaH2 X60PaCNP4F8Lx312F6MsSmAtO4+Qd3kKnnvuMOefOApx4pzYIPaGGWR4Ao66IiGn5OAzpEdvhHa l30OHSqYfwOu4gg== X-Developer-Key: i=abel.vesa@oss.qualcomm.com; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjIzMDEzMyBTYWx0ZWRfX7taE2F5JPepL YdUHduVofh3ik5e+Ir0PsZNxJ0+kuYeMsQOMHPoLRtSt4CFhPMqk0fDKcnutXBwCHJKXkBP+JOq 9MSSjhMFgiOihj6i/hgsm/j3N6RK8jjlObIR/aHZ4AzoIkuPiRaKUC6q5XCq4GllDia/AD8cSPW U3QYk+mnWFu3HFPw2e8GQF+XySb21gk1zAU8+dd1dN2/0mcz2S1eAtmovTP1hi7RTij81lo0+Vg icQbM3iZzWPDkgzv/H4sL525C7pmivqgaSCSK+Vw2i9LA1Bpe80rgatn0PLIoi6n8M9/isjzKGH Evme64erUwRHKamv/E0f4QzNJStv4NGoEl4hsLO5GcwdCgXc0JfTjters/mTmCQJ20BV7ciEpRZ GqR3bq+LrcCprWkqek7hNigpfARUSgNaKBWZb6skcBO8rq792REECjlNBjr4mLGaRGodG0aSusx upfrDYTnQBlsHq8bVnQ== X-Authority-Analysis: v=2.4 cv=edYwvrEH c=1 sm=1 tr=0 ts=699c7457 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=oauzzCmhM186DRC0Y2yWPg==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=8wER65Pd3tfT56eRIC8A:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-GUID: Aul7OqCG2Hx14Y4QPs0COWmFTjc6urHu X-Proofpoint-ORIG-GUID: Aul7OqCG2Hx14Y4QPs0COWmFTjc6urHu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-23_03,2026-02-23_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 phishscore=0 clxscore=1015 priorityscore=1501 spamscore=0 impostorscore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602230133 From: Wesley Cheng The Glymur USB system contains 3 USB type C ports, 1 USB multiport controller and a USB 2.0 only controller. This encompasses 5 SS USB QMP PHYs (3 combo and 2 uni) and 6 M31 eUSB2 PHYs. All controllers are SNPS DWC3 based, so describe them as flattened DWC3 QCOM nodes. Signed-off-by: Wesley Cheng Co-developed-by: Abel Vesa Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/glymur.dtsi | 691 +++++++++++++++++++++++++++++++= +++- 1 file changed, 686 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qco= m/glymur.dtsi index e269cec7942c..2aa9af8c96ce 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -750,11 +750,11 @@ gcc: clock-controller@100000 { <0>, /* UFS PHY RX Symbol 0 */ <0>, /* UFS PHY RX Symbol 1 */ <0>, /* UFS PHY TX Symbol 0 */ - <0>, /* USB3 PHY 0 */ - <0>, /* USB3 PHY 1 */ - <0>, /* USB3 PHY 2 */ - <0>, /* USB3 UNI PHY pipe 0 */ - <0>, /* USB3 UNI PHY pipe 1 */ + <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_mp_qmpphy0 QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_mp_qmpphy1 QMP_USB43DP_USB3_PIPE_CLK>, <0>, /* USB4 PHY 0 pcie pipe */ <0>, /* USB4 PHY 0 Max pipe */ <0>, /* USB4 PHY 1 pcie pipe */ @@ -2264,6 +2264,254 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, }; }; =20 + usb_hs_phy: phy@fa0000 { + compatible =3D "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + reg =3D <0x0 0x00fa0000 0x0 0x154>; + #phy-cells =3D <0>; + + clocks =3D <&tcsr TCSR_USB2_1_CLKREF_EN>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; + + status =3D "disabled"; + }; + + usb_mp_hsphy0: phy@fa1000 { + compatible =3D "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg =3D <0x0 0x00fa1000 0x0 0x29c>; + #phy-cells =3D <0>; + + clocks =3D <&tcsr TCSR_USB2_1_CLKREF_EN>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; + + status =3D "disabled"; + }; + + usb_mp_hsphy1: phy@fa2000 { + compatible =3D "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg =3D <0x0 0x00fa2000 0x0 0x29c>; + #phy-cells =3D <0>; + + clocks =3D <&tcsr TCSR_USB2_2_CLKREF_EN>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; + + status =3D "disabled"; + }; + + usb_mp_qmpphy0: phy@fa3000 { + compatible =3D "qcom,glymur-qmp-usb3-uni-phy"; + reg =3D <0x0 0x00fa3000 0x0 0x2000>; + + clocks =3D <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&tcsr TCSR_USB3_0_CLKREF_EN>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; + clock-names =3D "aux", + "clkref", + "ref", + "com_aux", + "pipe"; + + power-domains =3D <&gcc GCC_USB3_MP_SS0_PHY_GDSC>; + + resets =3D <&gcc GCC_USB3_MP_SS0_PHY_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; + reset-names =3D "phy", + "phy_phy"; + + clock-output-names =3D "usb3_uni_phy_0_pipe_clk_src"; + #clock-cells =3D <0>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_mp_qmpphy1: phy@fa5000 { + compatible =3D "qcom,glymur-qmp-usb3-uni-phy"; + reg =3D <0x0 0x00fa5000 0x0 0x2000>; + + clocks =3D <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&tcsr TCSR_USB3_1_CLKREF_EN>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; + clock-names =3D "aux", + "clkref", + "ref", + "com_aux", + "pipe"; + + power-domains =3D <&gcc GCC_USB3_MP_SS1_PHY_GDSC>; + + resets =3D <&gcc GCC_USB3_MP_SS1_PHY_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; + reset-names =3D "phy", + "phy_phy"; + + clock-output-names =3D "usb3_uni_phy_1_pipe_clk_src"; + + #clock-cells =3D <0>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_0_hsphy: phy@fd3000 { + compatible =3D "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg =3D <0x0 0x00fd3000 0x0 0x29c>; + #phy-cells =3D <0>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + status =3D "disabled"; + }; + + usb_0_qmpphy: phy@fd5000 { + compatible =3D "qcom,glymur-qmp-usb3-dp-phy"; + reg =3D <0x0 0x00fd5000 0x0 0x8000>; + + clocks =3D <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names =3D "aux", + "ref", + "com_aux", + "usb3_pipe"; + + resets =3D <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; + + reset-names =3D "phy", + "common"; + + power-domains =3D <&gcc GCC_USB_0_PHY_GDSC>; + + #clock-cells =3D <1>; + #phy-cells =3D <1>; + + mode-switch; + orientation-switch; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb_0_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + + usb_0_qmpphy_usb_ss_in: endpoint { + remote-endpoint =3D <&usb_0_dwc3_ss>; + }; + }; + + port@2 { + reg =3D <2>; + + usb_dp_qmpphy_dp_in: endpoint { + }; + }; + }; + }; + + usb_1_hsphy: phy@fdd000 { + compatible =3D "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg =3D <0x0 0x00fdd000 0x0 0x29c>; + #phy-cells =3D <0>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_SEC_BCR>; + + status =3D "disabled"; + }; + + usb_1_qmpphy: phy@fde000 { + compatible =3D "qcom,glymur-qmp-usb3-dp-phy"; + reg =3D <0x0 0x00fde000 0x0 0x8000>; + + clocks =3D <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>, + <&tcsr TCSR_USB4_1_CLKREF_EN>; + clock-names =3D "aux", + "ref", + "com_aux", + "usb3_pipe", + "clkref"; + + power-domains =3D <&gcc GCC_USB_1_PHY_GDSC>; + + resets =3D <&gcc GCC_USB3_PHY_SEC_BCR>, + <&gcc GCC_USB3PHY_PHY_SEC_BCR>; + reset-names =3D "phy", + "common"; + + #clock-cells =3D <1>; + #phy-cells =3D <1>; + + mode-switch; + orientation-switch; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb_1_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + + usb_1_qmpphy_usb_ss_in: endpoint { + remote-endpoint =3D <&usb_1_dwc3_ss>; + }; + }; + + port@2 { + reg =3D <2>; + + usb_1_qmpphy_dp_in: endpoint { + }; + }; + }; + }; + cnoc_main: interconnect@1500000 { compatible =3D "qcom,glymur-cnoc-main"; reg =3D <0x0 0x01500000 0x0 0x17080>; @@ -3367,6 +3615,439 @@ lpass_ag_noc: interconnect@7e40000 { #interconnect-cells =3D <2>; }; =20 + usb_2_hsphy: phy@88e0000 { + compatible =3D "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg =3D <0x0 0x088e0000 0x0 0x29c>; + #phy-cells =3D <0>; + + clocks =3D <&tcsr TCSR_USB2_4_CLKREF_EN>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_TERT_BCR>; + + status =3D "disabled"; + }; + + usb_2_qmpphy: phy@88e1000 { + compatible =3D "qcom,glymur-qmp-usb3-dp-phy"; + reg =3D <0x0 0x088e1000 0x0 0x8000>; + + clocks =3D <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>, + <&tcsr TCSR_USB4_2_CLKREF_EN>; + clock-names =3D "aux", + "ref", + "com_aux", + "usb3_pipe", + "clkref"; + + power-domains =3D <&gcc GCC_USB_2_PHY_GDSC>; + + resets =3D <&gcc GCC_USB3_PHY_TERT_BCR>, + <&gcc GCC_USB3PHY_PHY_TERT_BCR>; + reset-names =3D "phy", + "common"; + + #clock-cells =3D <1>; + #phy-cells =3D <1>; + + mode-switch; + orientation-switch; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb_2_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + + usb_2_qmpphy_usb_ss_in: endpoint { + remote-endpoint =3D <&usb_2_dwc3_ss>; + }; + }; + + port@2 { + reg =3D <2>; + + usb_2_qmpphy_dp_in: endpoint { + }; + }; + }; + }; + + usb_0: usb@a600000 { + compatible =3D "qcom,glymur-dwc3", "qcom,snps-dwc3"; + reg =3D <0x0 0x0a600000 0x0 0xfc100>; + + clocks =3D <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + interrupts-extended =3D <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 90 IRQ_TYPE_EDGE_BOTH>, + <&pdc 60 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_EDGE_BOTH>; + interrupt-names =3D "dwc_usb3", + "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains =3D <&gcc GCC_USB30_PRIM_GDSC>; + resets =3D <&gcc GCC_USB30_PRIM_BCR>; + + iommus =3D <&apps_smmu 0x1420 0x0>; + phys =3D <&usb_0_hsphy>, + <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names =3D "usb2-phy", + "usb3-phy"; + + snps,hird-threshold =3D /bits/ 8 <0x0>; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,has-lpm-erratum; + tx-fifo-resize; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + + usb-role-switch; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb_0_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + + usb_0_dwc3_ss: endpoint { + remote-endpoint =3D <&usb_0_qmpphy_usb_ss_in>; + }; + }; + }; + }; + + usb_1: usb@a800000 { + compatible =3D "qcom,glymur-dwc3", "qcom,snps-dwc3"; + reg =3D <0x0 0x0a800000 0x0 0xfc100>; + + clocks =3D <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + interrupts-extended =3D <&intc GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 88 IRQ_TYPE_EDGE_BOTH>, + <&pdc 87 IRQ_TYPE_EDGE_BOTH>, + <&pdc 76 IRQ_TYPE_EDGE_BOTH>; + interrupt-names =3D "dwc_usb3", + "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + resets =3D <&gcc GCC_USB30_SEC_BCR>; + power-domains =3D <&gcc GCC_USB30_SEC_GDSC>; + + iommus =3D <&apps_smmu 0x1460 0x0>; + + phys =3D <&usb_1_hsphy>, + <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names =3D "usb2-phy", + "usb3-phy"; + + snps,hird-threshold =3D /bits/ 8 <0x0>; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,has-lpm-erratum; + tx-fifo-resize; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + + usb_1_dwc3_ss: endpoint { + remote-endpoint =3D <&usb_1_qmpphy_usb_ss_in>; + }; + }; + }; + }; + + usb_2: usb@a000000 { + compatible =3D "qcom,glymur-dwc3", "qcom,snps-dwc3"; + reg =3D <0x0 0x0a000000 0x0 0xfc100>; + + clocks =3D <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, + <&gcc GCC_USB30_TERT_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, + <&gcc GCC_USB30_TERT_SLEEP_CLK>, + <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + interrupts-extended =3D <&intc GIC_SPI 871 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 89 IRQ_TYPE_EDGE_BOTH>, + <&pdc 81 IRQ_TYPE_EDGE_BOTH>, + <&pdc 75 IRQ_TYPE_EDGE_BOTH>; + interrupt-names =3D "dwc_usb3", + "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + resets =3D <&gcc GCC_USB30_TERT_BCR>; + power-domains =3D <&gcc GCC_USB30_TERT_GDSC>; + + iommus =3D <&apps_smmu 0x420 0x0>; + + phys =3D <&usb_2_hsphy>, + <&usb_2_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names =3D "usb2-phy", + "usb3-phy"; + + snps,hird-threshold =3D /bits/ 8 <0x0>; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,has-lpm-erratum; + tx-fifo-resize; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb_2_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + + usb_2_dwc3_ss: endpoint { + remote-endpoint =3D <&usb_2_qmpphy_usb_ss_in>; + }; + }; + }; + }; + + usb_hs: usb@a2f8800 { + compatible =3D "qcom,glymur-dwc3", "qcom,snps-dwc3"; + reg =3D <0x0 0x0a200000 0x0 0xfc100>; + + clocks =3D <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>, + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_SLEEP_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + assigned-clocks =3D <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>; + assigned-clock-rates =3D <19200000>, <200000000>; + + interrupts-extended =3D <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 92 IRQ_TYPE_EDGE_BOTH>, + <&pdc 57 IRQ_TYPE_EDGE_BOTH>, + <&intc GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "dwc_usb3", + "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "hs_phy_irq"; + + resets =3D <&gcc GCC_USB20_PRIM_BCR>; + + power-domains =3D <&gcc GCC_USB20_PRIM_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + iommus =3D <&apps_smmu 0x0ce0 0x0>; + + interconnects =3D <&aggre3_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "usb-ddr", + "apps-usb"; + + phys =3D <&usb_hs_phy>; + phy-names =3D "usb2-phy"; + + snps,hird-threshold =3D /bits/ 8 <0x0>; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,has-lpm-erratum; + tx-fifo-resize; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + + dr_mode =3D "host"; + + maximum-speed =3D "high-speed"; + + status =3D "disabled"; + }; + + usb_mp: usb@a400000 { + compatible =3D "qcom,glymur-dwc3-mp", "qcom,snps-dwc3"; + reg =3D <0x0 0x0a400000 0x0 0xfc100>; + + clocks =3D <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_SLEEP_CLK>, + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + interrupts-extended =3D <&intc GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 12 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 11 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 13 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 78 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 77 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "dwc_usb3", + "pwr_event_1", + "pwr_event_2", + "hs_phy_1", + "hs_phy_2", + "dp_hs_phy_1", + "dm_hs_phy_1", + "dp_hs_phy_2", + "dm_hs_phy_2", + "ss_phy_1", + "ss_phy_2"; + + resets =3D <&gcc GCC_USB30_MP_BCR>; + power-domains =3D <&gcc GCC_USB30_MP_GDSC>; + + iommus =3D <&apps_smmu 0xda0 0x0>; + + phys =3D <&usb_mp_hsphy0>, + <&usb_mp_qmpphy0>, + <&usb_mp_hsphy1>, + <&usb_mp_qmpphy1>; + phy-names =3D "usb2-0", + "usb3-0", + "usb2-1", + "usb3-1"; + + snps,hird-threshold =3D /bits/ 8 <0x0>; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,has-lpm-erratum; + tx-fifo-resize; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + + dr_mode =3D "host"; + + status =3D "disabled"; + }; + + dispcc: clock-controller@af00000 { compatible =3D "qcom,glymur-dispcc"; reg =3D <0x0 0x0af00000 0x0 0x20000>; --=20 2.48.1